CN112000527A

CN112000527A - FPGA engineering test method of federated learning system

Info

Publication number: CN112000527A
Application number: CN202010664239.4A
Authority: CN
Inventors: 程孝典; 王玮; 胡水海
Original assignee: Shenzhen Zhixing Technology Co Ltd
Current assignee: Shenzhen Zhixing Technology Co Ltd
Priority date: 2020-07-10
Filing date: 2020-07-10
Publication date: 2020-11-27

Abstract

The embodiment of the specification provides an FPGA engineering test method, wherein the FPGA is applied to a heterogeneous processing system for federal learning, the heterogeneous processing system comprises an upper computer and the FPGA, and the test method comprises the following steps: the upper computer sends configuration data and test source data to the FPGA, wherein the configuration data comprises appointed test configuration data; and the FPGA receives the test source data and processes the test source data in the specified test module according to the configuration data to obtain test result data. By the aid of the FPGA engineering test mode, the specified test module of the FPGA can be tested, and once the test module is abnormal, the abnormal condition of the specified test module of the FPGA can be directly positioned.

Description

FPGA engineering test method of federated learning system

Technical Field

The embodiment of the specification relates to the field of federal learning generally, in particular to an FPGA engineering test method used in a federal learning system.

Background

Federated learning is a distributed learning-based architecture that spreads the computation of machine learning over the databases of the participating parties for cryptographic distributed computation. In order to coordinate nodes of distributed computation, gradient related data needs to be transmitted, privacy protection needs to be performed on the gradient related data, and complexity of related algorithms is high. The federal learning system has a huge demand on computing performance, and a field Programmable Gate array (fpga) (field Programmable Gate array) provides powerful computing performance for federal learning.

When the FPGA is subjected to engineering test, if the complete function of the FPGA is directly tested, because the FPGA engineering of the federal learning system has more calculation modules and control modules, the structure is complex, more test points are directly tested, and when the test is wrong, the working state of the FPGA is difficult to judge from the outside and the fault is difficult to position.

Disclosure of Invention

In view of the foregoing, embodiments of the present description provide an FPGA engineering test method for federated learning heterogeneous processing systems. By using the FPGA engineering test method of the heterogeneous processing system, engineering test can be performed on the designated module, the range of troubleshooting is reduced, and the efficiency of the FPGA engineering test is improved.

According to an aspect of an embodiment of the present specification, there is provided an FPGA engineering test method, where the FPGA is applied to a heterogeneous processing system of federal learning, the heterogeneous processing system includes an upper computer and an FPGA, and the test method includes: the upper computer sends configuration data to the FPGA, wherein the configuration data comprises specified test configuration data; the upper computer sends test source data to the FPGA; and the FPGA receives the test source data and correspondingly processes the test source data in a specified test module according to the configuration data to obtain test result data.

Optionally, in an example of the above aspect, the test method further includes: the specified test configuration data comprises specified link module test configuration data, and if the FPGA receives the specified link module test configuration data, the FPGA processes the source data only in the link module.

According to another aspect of the embodiments of the present specification, there is provided an FPGA engineering test method, where the FPGA is applied to a heterogeneous processing system of federal learning, the heterogeneous processing system includes an upper computer and an FPGA, the FPGA includes a plurality of computing modules, and the test method includes: the upper computer sends configuration data to the FPGA, wherein the configuration data comprises bypass test configuration data of a specified computing module; the upper computer sends test source data to the FPGA; and the FPGA receives the test source data, and forwards the test source data in a specified calculation module according to the configuration data without performing calculation processing to obtain test result data.

Optionally, in an example of the above aspect, the test method further includes: the upper computer receives the test result data; and the upper computer compares the test source data sent to the FPGA with the received test result data, and if the test source data sent to the FPGA is consistent with the received test result data, the test result data specified by the FPGA are determined to be normal.

Optionally, in an example of the above aspect, the FPGA includes a plurality of computing modules, and the test method further includes: the specified test configuration data comprises calculation test configuration data of a specified calculation module, and if the FPGA receives the calculation test configuration data of the specified calculation module, the FPGA only performs calculation processing of the specified calculation module and does not perform calculation processing of other calculation modules when processing the test source data.

Optionally, in an example of the above aspect, the test method further includes: the appointed test module configuration data comprises appointed full-module test configuration data, and if the FPGA receives the appointed full-module test configuration data, the FPGA processes data of all modules when processing test source data, including calculation processing of all calculation modules.

Optionally, in an example of the above aspect, the test method further includes: the upper computer receives the test result data; the upper computer obtains standard result data according to the test source data and the configuration data sent to the FPGA; and the upper computer compares the standard result data with the test result data, and if the standard result data is consistent with the test result data, the data processing result of the FPGA specified test is determined to be normal.

Optionally, in one example of the above aspect, the test method includes: the test source data is to-be-encrypted or to-be-decrypted data learned by the federation.

According to another aspect of the embodiments of the present specification, there is provided a method for engineering testing of an FPGA link module, where the FPGA is applied to a heterogeneous processing system for federal learning, the heterogeneous processing system includes an upper computer and an FPGA, and the testing method includes: the upper computer sends test source data to a preset address in the FPGA memory; the upper computer reads test result data from the preset address in the FPGA memory; and the upper computer compares the read test result data with the sent test source data, and if the read test result data is consistent with the sent test source data, the upper computer determines that the link module is normal.

According to another aspect of embodiments of the present specification, there is provided a machine-readable storage medium storing executable instructions that, when executed, cause a machine to perform a task processing method as described above.

Drawings

A further understanding of the nature and advantages of the present disclosure may be realized by reference to the following drawings. In the drawings, similar components or features may have the same reference numerals.

Fig. 1 illustrates an example architectural diagram of a heterogeneous processing system 1 in accordance with embodiments of the present description.

FIG. 2 shows a flowchart of a method for a heterogeneous processing system to perform FPGA engineering testing, according to an embodiment of the present description.

FIG. 3 is a flow diagram illustrating a method for specifying bypass testing of a compute module in FPGA engineering tests performed by a heterogeneous processing system according to an embodiment of the present description.

Fig. 4 is a flowchart illustrating a test sequence specified in the FPGA engineering test method according to an embodiment of the present specification.

Detailed Description

The subject matter described herein will now be discussed with reference to example embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and thereby implement the subject matter described herein, and are not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as needed. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. In addition, features described with respect to some examples may also be combined in other examples.

As used herein, the term "include" and its variants mean open-ended terms in the sense of "including, but not limited to. The term "based on" means "based at least in part on". The terms "one embodiment" and "an embodiment" mean "at least one embodiment". The term "another embodiment" means "at least one other embodiment". The terms "first," "second," and the like may refer to different or the same object. Other definitions, whether explicit or implicit, may be included below. The definition of a term is consistent throughout the specification unless the context clearly dictates otherwise.

Federal learning is an important machine learning framework in the field of Artificial Intelligence (AI). The machine learning framework can realize the sharing of data of two parties on the premise of ensuring the data security, privacy and legality of different enterprises, organizations or users, for example, the machine learning framework is used for training and learning AI, and therefore the data island limitation is broken.

Data is the basis of machine learning, and in order to ensure that data is shared between different enterprises or users in a secure and private manner, multi-party secure computing processing needs to be performed on the data. An example of multi-party security computation may include homomorphic cryptographic operations. Homomorphic cryptographic operations are complex mathematical operations with high bit widths and large integers, which are very computationally intensive, and involve requirements on computational real-time and performance, thus making computing systems highly demanding on hardware processors.

A federated learning system is a heterogeneous processing system formed on the basis of a CPU and an FPGA, wherein the CPU is responsible for controlling and scheduling the overall system task of the heterogeneous processing system, and the FPGA is responsible for realizing the parallel processing of processing tasks (such as algorithm tasks). The FPGA is a programmable hardware chip and has the characteristics of high flexibility, high parallelism and low delay processing. Algorithm design or control logic can be customized in the FPGA, algorithm implementation on the FPGA belongs to hardware implementation, the final running state is a specific circuit structure, and the concept of an operating system and instructions is avoided, so that the FPGA can highly and parallelly and quickly complete data processing, and the efficiency of processing private data in federal learning is greatly improved.

The heterogeneous processing system applied to federal learning and the FPGA engineering test method thereof according to the embodiment of the present specification will be described below with reference to the accompanying drawings.

Fig. 1 illustrates an example architectural diagram of a heterogeneous processing system 1 in accordance with embodiments of the present description. As shown in fig. 1, the heterogeneous processing system includes an upper computer 10 and an FPGA accelerator card 20.

The upper computer 10 includes a Central Processing Unit (CPU) 110 and a CPU memory 120. Furthermore, the CPU has a data interface module 111. The FPGA accelerator card 20 includes an FPGA chip 210 (hereinafter referred to as FPGA) and an FPGA memory 220. Furthermore, the FPGA has a data interface module 211. The upper computer 10 is responsible for controlling and scheduling the overall system tasks of the heterogeneous processing system. The FPGA accelerator card 20 is responsible for implementing the processing of processing tasks (e.g., algorithmic tasks). Data transmission and communication can be carried out between the upper computer and the FPGA through the

data interface modules

111 and 211.

The upper computer 10 further comprises a data high-speed interface 130, the FPGA accelerator card further comprises a high-speed data interface 230, and data transmission and communication can be carried out between the upper computer and the FPGA through the high-

speed data interfaces

130 and 230, so that data and information interaction between the FPGA (210) and the upper computer 10 is completed. The data transmitted between the FPGA210 and the upper computer 10 may include source data (hereinafter referred to as "test source data") required for task processing and configuration data. Data transmission and communication between the FPGA (210) and the upper computer 10 can be implemented by using a local real-time high-speed communication protocol (e.g., PCIe) instead of a remote communication protocol (e.g., TCP/IP), so that communication delay can be greatly reduced. After receiving the test source data and the configuration data from the upper computer 10, the FPGA (210) may perform corresponding processing to obtain task result data, and provide the task result data to the upper computer 10.

The configuration data is sent to the register management module 214, and the register management module 214 controls the read/write operations for the configuration data in the computing module. The configuration data is sent to compute component 2150 through register management module 214. When the compute component includes multiple compute modules, the register management module 214 sends the configuration data to the multiple compute modules, respectively.

The source data is sent to the data read/write control module 212, and the data read/write control module 212 controls the read/write operations for the data in the FPGA memory 220. The source data is written to the FPGA memory 220 by the read/write control module 212. The task management module 213 obtains the task processing source data from the FPGA memory 220 through the data read/write control module 212, and distributes the task processing source data to the computing modules in the computing component 2150 for processing, so as to obtain task processing result data. The task management module 213 writes the task processing result data into the FPGA memory through the data read/write control module 212, and the data read/write control module 212 reads the task result data in the FPGA memory and sends the task result data to the upper computer 10 through the data interface module 211 and the data high-speed interface 230.

Optionally, the source data is sent to the task management module 213, the source data is written into the FPGA memory 220 through the task management module 213, when the task processing is completed, the task result data is sent to the FPGA memory 220 through the task management module 213, and then sent back to the upper computer 10 through the data interface module 211 and the data high-speed interface 230.

When carrying out engineering test to FPGA, if directly test FPGA's complete function, because FPGA is inside to have more calculation module and control module, the structure is complicated, directly tests test point more, and when testing wrong, FPGA's operating condition is difficult to follow the outside and judges, is difficult to fix a position the problem.

In block 201, the upper computer sends configuration data to the FPGA, where the configuration data includes specified test configuration data;

specifically, the configuration information may further include algorithm configuration information, and the FPGA determines an algorithm for executing data processing according to the configuration data; the configuration information can also comprise bit width information, and the FPGA determines the bit width of the data to be processed according to the configuration data; the configuration information can also comprise working state information, and the FPGA can determine whether to start data processing work according to the configuration data; the configuration information can also comprise data volume information, and the FPGA determines the data volume of the data to be processed according to the configuration data. In the application, the configuration data further includes specified test configuration data, and the FPGA performs source data processing in a specified module according to the configuration data.

The configuration data stored by the register may include one or more bits, for example, 32 bits. A bit or bits of a register are used to describe a state or indicate a result. Specifically, the specified test configuration data may include a plurality of bits for instructing the module to perform corresponding processing on the test source data, for example, to test the computing function of the computing module and perform computing processing on the test source data; and testing the bypass of the computing module, and forwarding the test source data.

The specified test may specify testing the link module, may also specify testing the bypass of the compute module, may also specify testing the compute module, and may also specify testing the full module.

At block 202, the upper computer sends test source data to the FPGA;

at block 203, the FPGA receives the test source data and processes the test source data in a designated test module according to the configuration data to obtain test result data.

Specifically, the test module may be a link module, a calculation module, or a full module. When the specified test is the test of the specified link module, the test source data only carries out data processing in the link module; when the specified test is to carry out the bypass test on the specified computing module, the test source data is forwarded and processed in the specified computing module without being processed; when the appointed test is the calculation test of an appointed calculation module, the FPGA only performs the calculation process of the appointed calculation module and does not perform the calculation process of other calculation modules when processing the test source data; and when the specified test is to specify the test of the whole module, the FPGA processes the data of all the modules when processing the test source data, including the calculation processing of all the calculation modules.

According to the invention, the configuration data sent to the FPGA by the upper computer comprises the specified test configuration data, and data processing is carried out in the specified test module according to the configuration data, so that test result data is obtained.

And when the FPGA receives the bypass test configuration data of the specified calculation module, the FPGA skips the calculation processing of the specified calculation module when processing the test source data.

In particular, fig. 3 shows a flowchart of a method for specifying bypass testing of a compute module in FPGA engineering tests performed by a heterogeneous processing system according to an embodiment of the present specification. The FPGA engineering test method according to an embodiment of the present specification is described in more detail below with reference to fig. 1 and 3.

At block 301, the upper computer sends specified compute module bypass test configuration data to the FPGA register management module.

The upper computer is a personal host or a server and refers to a Processing device capable of directly sending out an operation command, the upper computer comprises a processor and a memory, the processor can be a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), or a Field Programmable Gate Array (FPGA), the FPGA is the processor of the upper computer and is different from the FPGA in the FPGA acceleration card in the figure 1, the FPGA acceleration card is actually a lower computer, and the FPGA is the processor in the lower computer.

Optionally, the upper computer sends the configuration information to the FPGA, and data transmission and communication between the upper computer and the FPGA can be implemented by using a local real-time high-speed communication protocol (e.g., PCIe) instead of a remote communication protocol (e.g., TCP/IP), so that communication delay can be greatly reduced.

Optionally, the high-

speed interface modules

111 and 211 may use a dma (direct memory access) mode or a PIO mode to perform data transmission. DMA is an efficient data transfer mechanism. In actual operation, the configuration data can be directly transferred from the upper computer 10 to the register of the FPGA without excessive intervention of the upper computer.

At block 302, the register management module forwards the configuration information to registers within the respective compute modules.

Specifically, as shown in fig. 1, in a specific implementation manner, a processor of the upper computer is a CPU, the CPU (110) sends bypass test configuration data of a specified computing module to the FPGA (210) through the data interface module 111 and the data high-speed interface 130, the FPGA (210) receives the configuration data through the data high-speed interface 230 and the data interface module 211, and the register management module 214 is in communication connection with the data interface module 211 to store the configuration information in registers of the multiple computing modules, respectively. Specifically, as shown in fig. 1, register a (21511) stored in calculation module a (2151), register a (21521) stored in calculation module B (2152), and so on.

Optionally, the test configuration data may also be sent to the register of the computing module a and the register of the computing module B through the task management module.

At block 303, the upper computer generates test source data.

Specifically, the upper computer can generate data which accords with practical application according to the characteristics of the data in the federal learning scene, for example, the data to be encrypted is generated to be used for the FPGA to perform encryption calculation processing, or the data to be decrypted is generated to be used for the FPGA to perform decryption calculation processing.

At block 304, the upper computer sends test source data to the FPGA memory.

The mode that the upper computer sends the test source data to the FPGA can be realized by adopting a local real-time high-speed communication protocol (such as PCIe) instead of a remote communication protocol (such as TCP/IP) by referring to the mode that the upper computer sends the configuration data to the FPGA, so that the communication delay can be greatly reduced.

Optionally, the high-

speed interface modules

111 and 211 may use a dma (direct memory access) mode or a PIO mode to perform data transmission. DMA is an efficient data transfer mechanism. In actual operation, the test configuration data can be directly transferred from the host computer 10 to the FPGA memory 220 without requiring excessive host computer intervention.

Specifically, as shown in fig. 1, the CPU (110) transmits the test source data to the FPGA (210) through the data interface module 111 and the data high-speed interface 130, and the FPGA receives the test source data through the data high-speed interface 230 and the data interface module 211 and writes the test source data into the FPGA memory 220 through the data read/write control module 212.

At block 305, the host computer sends a start job instruction to the FPGA and begins to wait for the FPGA job to complete. Specifically, as shown in fig. 1, the task management module 213 may include a register 2131, the upper computer 10 configures a work start register to the task management module 213 through the register management module 214, and the task management module 213 may start the calculation processing of the corresponding calculation module after detecting the change of the corresponding register data. At block 306, the task management module reads the test source data from the FPGA memory through the read/write control module.

At block 307, the task management module issues the test source data to the compute module.

In the federal learning heterogeneous processing system, the FPGA plays a role of a high-speed arithmetic unit and undertakes realization of complex arithmetic to reduce the working pressure of an upper computer, so that the computing component usually comprises a plurality of computing modules to compute data in parallel. Specifically, as shown in FIG. 1, the task management module 213 sends the source data to the compute component 2150. Alternatively, the computing component 2150 may include a plurality of computing modules, for example, the computing component 2150 includes a plurality of computing modules, such as computing module a (2151), computing module B (2152), and the like, and the plurality of computing modules may be connected in series as shown in fig. 1. Optionally, the compute component 2150 may also include multiple compute modules working in parallel, e.g., hundreds of identical and working in parallel compute modules a to which the task management module 213 distributes source data.

At block 308, the calculation module reads the value of its own register, knows that a bypass test needs to be performed, and directly forwards the data to the next module.

Specifically, as shown in fig. 1, the computing module a reads the configuration data of the register a, and the configuration data stored in the computing module a is the configuration data that specifies the computing module a to perform the bypass test, so that the source data sent to the computing module a is not computed in the computing module a, but only forwarded. And then entering the next computing module B, and continuing to read the configuration data of the computing module B, wherein the configuration data stored in the computing module B is the configuration data for specifying the computing module B to perform the bypass test, and the source data sent to the computing module B is not subjected to computing processing in the computing module B, but only subjected to forwarding processing. By analogy, the corresponding processing mode of the test source data in the computing module is obtained by reading the configuration information stored in each computing module, and the corresponding processing can be forwarding processing of the test source data or calculation processing of the test source data.

The bypass test of the specified computing module tests the transceiving function of the computing module, can skip the source data computing processing of the specified computing module, and only carries out the bypass test on the computing module.

At block 309, the task management module gets the returned test result data and forwards it to the FPGA memory.

Specifically, as shown in fig. 1, after the computing component 2150 completes the corresponding processing, the test result data is obtained and sent back to the task management module 213, and the task management module 213 sends the corresponding test result data to the FPGA memory 220 through the data read/write controller 212.

At block 310, the FPGA sends a job complete signal to the upper computer.

Specifically, when the FPGA is in a test result data transmission ready state, the FPGA may send an interrupt control request to the upper computer 10, and when the upper computer receives the interrupt control request, the upper computer may respond to the interrupt control request according to an actual situation to prepare to receive the test result data transmitted from the FPGA.

Optionally, the state of the FPGA may also be detected in a polling manner by the upper computer, and when the upper computer repeatedly reads the value of the FPGA state register until the FPGA is detected to be in a test result data transmission ready state, the upper computer is ready to receive the test result data transmitted from the FPGA.

At block 311, the upper computer reads the test result data in the FPGA memory.

Specifically, the upper computer 10 may read the test result data in the FPGA memory 220 in the manner described with reference to the block 310.

At block 312, the upper computer compares whether the output test result data of the FPGA is consistent with the input test source data.

Specifically, the upper computer 10 compares the received test result data transmitted by the FPGA with the test source data previously sent to the FPGA.

At block 313, the upper computer outputs the test results.

Specifically, since the configuration data sent to the FPGA by the upper computer 10 is the configuration data of the bypass of the designated calculation module, the test source data is not processed in the calculation module, and thus the test result data is not changed. Therefore, if the comparison result shows that the two data are consistent, the output test result is normal, which represents that the bypass of the computing module works normally; if the comparison result shows that the two data are inconsistent, the test result is output to be abnormal, which represents that the bypass of the computing module has a fault, the fault elimination processing can be carried out on the bypass of the computing module instead of the whole FPGA module, so that the fault elimination range is reduced, the fault treatment speed can be improved, and the FPGA engineering test efficiency is further improved.

And the specified link module test configuration data is the configuration data for performing engineering test on the link module in the FPGA. When the FPGA receives test configuration data of a specified link module, the FPGA processes the test source data only in the link module when processing the test source data. The link module is a part for data transmission and control interaction between the FPGA and an upper computer and mainly comprises an existing data channel IP core, an interface IP and a Memory control (Memory) IP core. The data channel IP core comprises one or more of a data bit width conversion module, a frequency conversion module, an arbitration module (distributed to different memories) and the like; the interface IP is responsible for analyzing the transmission protocol; as shown in fig. 1, the memory control IP core is responsible for the interaction of the FPGA (210) and the FPGA memory (220).

Specifically, reference may be made to the various blocks of fig. 3 and the description above regarding the various blocks. Different from the bypass for testing the FPGA computing module, as shown in fig. 1, the test configuration data of the designated link module may be stored in the task management module 213 through the register management module 214, and the task management module 213 may read the configuration data, not distribute the source data to each computing component 2150, but directly return the source data as the test result data to the FPGA memory 220 through the read-write control module 212, and finally send the test result data to the upper computer 10.

The configuration data sent to the FPGA by the upper computer 10 is the configuration data of the designated link module, that is, the configuration data for testing the link module. Because the source data is not processed in the computing module, but is directly returned to the FPGA memory from the task management module, the test result data is not changed. Therefore, if the comparison result shows that the two data are consistent, the output test result is normal, which represents that the link module works normally; if the comparison result shows that the two data are inconsistent, the output test result is abnormal, which represents that the link module has a fault, the fault can be eliminated for the link module, and the whole FPGA module does not need to be eliminated, so that the fault elimination range is reduced, the fault treatment speed can be increased, and the FPGA test efficiency is improved.

Optionally, since the link module actually needs to write less code, which is faster than the rest of the logic function modules, the link module code may be written independently from the engineering code, and the code of the link module is written preferentially, and when the code of another hardware module is not completed, the hardware test is performed preferentially over the other logic function module, for example, the hardware test is performed preferentially over the calculation module. Specifically, the upper computer sends data to a predetermined address in the FPGA memory, then reads the data from the same predetermined address in the FPGA memory, and compares whether the read data is the same as the sent data. If the data link is the same as the data link, the data link is considered to work normally. By the mode, whether the link module has faults can be preferentially determined, if the faults are processed in time, compared with the hardware test of the whole module, the method can narrow the fault troubleshooting range, find the faults of the link module in time and process the faults in time so as to ensure the normal operation of the link module.

The calculation test configuration data of the designated calculation module is configuration data for testing the calculation function of the designated calculation module in the FPGA, and may be one or more of the designated calculation modules, or all of the designated calculation modules.

Specifically, as shown in fig. 1, the CPU (110) sends the test configuration data of the designated computing module to the FPGA (210) through the data interface module 111 and the data high-speed interface 130, the FPGA (210) receives the configuration data through the data high-speed interface 230 and the data interface module 211, and the register management module 214 and the data interface module 211 are in communication connection to store the configuration information in the registers of the plurality of computing modules, respectively. Specifically, as shown in fig. 1, register a (21511) stored in calculation module a (2151), register a (21521) stored in calculation module B (2152), and so on.

And reading the configuration data of the register A by the computing module A, wherein the configuration data stored by the computing module A is test configuration data for specifying the computing test of the computing module A, and the test source data transmitted to the computing module A is computed in the computing module A. And entering the next computing module B, continuing to read the configuration data of the computing module B, wherein the configuration data stored in the computing module B is test configuration data for performing bypass test on the computing module B, and forwarding the test source data transmitted to the computing module B in the computing module B. By analogy, whether the calculation processing of the source data is carried out in the calculation module is obtained by reading the configuration information stored in each calculation module. In this way, only the specified calculation module can be subjected to calculation processing, and the other calculation modules can be subjected to bypass processing. Whether the designated calculation module is abnormal or not can be tested in a targeted manner, the range of troubleshooting is narrowed, and the targeted troubleshooting is facilitated, so that the efficiency of the whole FPGA engineering test is accelerated.

The CPU calculates the source data in the CPU to obtain standard result data, and compares the test result data with the standard result data to determine whether the test result data is normal. Specifically, an internal algorithm library of the CPU can be called, and the test source data is processed by the same data processing method as that in the FPGA specified calculation module, so that standard result data is obtained.

Because the FPGA receives the test configuration data of the appointed calculation module, the FPGA only performs the calculation processing of the appointed calculation module and does not perform the calculation processing of other calculation modules when processing the test source data. Therefore, a certain calculation module can be processed in a targeted manner, so that test result data for the certain calculation module can be obtained. Whether the appointed calculation module is normal or abnormal can be judged through the test result data, and once the abnormity is confirmed, the abnormity can be directly positioned to the appointed calculation module, so that the fault troubleshooting range is reduced, and the FPGA engineering test efficiency is improved.

And designating the full-module test configuration data as the configuration data for performing engineering test on all modules in the FPGA, wherein all modules comprise a link module, a calculation module and the like.

And reading the configuration data of the register A by the computing module A, wherein the configuration data stored by the computing module A is test configuration data for specifying the computing module A to perform computing test, and performing computing processing on the test source data transmitted to the computing module A in the computing module A. And the computing module B reads the configuration data of the computing module B, and if the configuration data stored by the computing module B is the test configuration data for performing the computing test on the specified computing module B, the computing module B performs computing processing on the test source data transmitted to the computing module B. And in the same way, determining that all calculation modules need to perform calculation processing.

The CPU calculates the test source data in the CPU to obtain standard result data, and compares the test result data with the standard result data to determine whether the test result data is normal. The specific method can refer to the example of the test of the previously specified calculation module.

At block 401, testing of a link module is specified.

When the FPGA engineering test is carried out, the link module is tested firstly, so that whether the related components of the CPU and the FPGA interface and the data link module are abnormal or not is confirmed, once the abnormality occurs, the fault can be quickly positioned and timely solved, the test step can be directly carried out after only the code of the link module is written, and the test step does not need to be carried out after all the codes are finished. And when the FPGA engineering test of the link module is carried out, the simulation test can be carried out on other FPGA modules at the same time, and the efficiency of the FPGA overall engineering test can be further improved.

At block 402, a bypass test is specified for a compute module.

And after the link module is confirmed to be normal, performing bypass test on the computing module, namely confirming whether the main data channels of the FPGA except the computing module work normally, and if the main data channels are abnormal, finding out faults in time. Because the link module is checked before and the link module is confirmed to be normal, the fault is directly positioned to the interface part of the FPGA and the calculation module to be abnormal, the range of checking the fault is further narrowed, and the fault is rapidly processed.

At block 403, a computational test is specified for the computational module.

After confirming that the bypass test of the computing module is normal, the computing function of the computing module is tested, the computing component applied to federal learning comprises a plurality of computing modules, as shown in fig. 1, the computing component 2150 comprises computing modules a (2151) and (2152) and the like. At this time, the plurality of calculation modules can be directly tested, and if the test result data is normal, the plurality of calculation modules are determined to be normal; if the test result is abnormal, the plurality of calculation modules are assigned one by one to be tested, for example, the calculation function of the calculation module a is assigned to be tested, the calculation function of the calculation module B is tested after the calculation module a is confirmed to be normal, if the calculation module B is not abnormal, all the subsequent modules are tested, if the calculation module B is abnormal, the calculation module B is detected and verified, the fault point is analyzed, and the like, and all the calculation modules of the calculation component 2150 are finally confirmed to be normal.

At block 404, testing of the full module is specified.

And finally, after the computing assembly is confirmed to be normal, performing performance and stability tests on the full modules of the FPGA to thoroughly check whether all the modules are normal, and if the modules are abnormal, performing corresponding specified tests according to actual conditions to further check the reduced-range troubleshooting faults.

By the FPGA engineering test method, the modules of the FPGA are tested step by step from small to large, so that the accuracy of positioning the fault is improved, the fault can be determined as soon as possible, and the efficiency of FPGA engineering test is improved.

Further, in order to test the operation performance of the FPGA project, as shown in fig. 3, the heterogeneous processing system may also monitor the time from the time when the upper computer sends the start working instruction 315 to the FPGA to the time when the upper computer outputs the test result 313, and by automatically counting the time and the calculated data amount automatically counted by the FPGA, the throughput and the bandwidth of the FPGA operation may be obtained, thereby providing the performance parameter index of the FPGA.

Optionally, in another example, the FPGA may not include the data read/write control module 212. Accordingly, the FPGA accelerator card does not include the FPGA memory 220, and the data interface module 211 is communicably connected with the task management module 213 and performs bidirectional communication. The task management module 213 is configured to acquire source data from the interface module 211 and supply test result data of the calculation component 2150 to the interface module 211, thereby to the host computer 10.

According to one embodiment of the present description, a program product, such as a machine-readable medium (e.g., a non-transitory machine-readable medium), is provided. A machine-readable medium may have instructions (i.e., elements described above as being implemented in software) that, when executed by a machine, cause the machine to perform various operations and functions described above in connection with fig. 1-4 in the various embodiments of the present specification. Specifically, a system or apparatus may be provided which is provided with a readable storage medium on which software program code implementing the functions of any of the above embodiments is stored, and causes a computer or processor of the system or apparatus to read out and execute instructions stored in the readable storage medium.

In this case, the program code itself read from the readable medium can realize the functions of any of the above-described embodiments, and thus the machine-readable code and the readable storage medium storing the machine-readable code form part of the present invention.

Examples of the readable storage medium include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-R, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs), magnetic tapes, nonvolatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer or from the cloud via a communications network.

As described above with reference to fig. 1 through 4, a heterogeneous processing system and an FPGA engineering test method according to an embodiment of the present specification are described. It will be understood by those skilled in the art that various changes and modifications may be made in the above-disclosed embodiments without departing from the spirit of the invention. Accordingly, the scope of the invention should be determined from the following claims.

It should be noted that not all steps and units in the above flows and system structure diagrams are necessary, and some steps or units may be omitted according to actual needs. The execution order of the steps is not fixed, and can be determined as required. The apparatus structures described in the above embodiments may be physical structures or logical structures, that is, some units may be implemented by the same physical entity, or some units may be implemented by a plurality of physical entities, or some units may be implemented by some components in a plurality of independent devices.

The detailed description set forth above in connection with the appended drawings describes exemplary embodiments but does not represent all embodiments that may be practiced or fall within the scope of the claims. The term "exemplary" used throughout this specification means "serving as an example, instance, or illustration," and does not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The FPGA engineering test method is characterized in that the FPGA is applied to a heterogeneous processing system for federal learning, the heterogeneous processing system comprises an upper computer and the FPGA, and the test method comprises the following steps:

the upper computer sends configuration data to the FPGA, wherein the configuration data comprises specified test configuration data;

the upper computer sends test source data to the FPGA;

and the FPGA receives the test source data and correspondingly processes the test source data in a specified test module according to the configuration data to obtain test result data.

2. The testing method of claim 1, further comprising:

the specified test configuration data comprises specified link module test configuration data, and if the FPGA receives the specified link module test configuration data, the FPGA processes the test source data only in the link module when processing the test source data.

3. The FPGA engineering test method is characterized in that the FPGA is applied to a heterogeneous processing system for federal learning, the heterogeneous processing system comprises an upper computer and the FPGA, the FPGA comprises a plurality of computing modules, and the test method comprises the following steps:

the upper computer sends configuration data to the FPGA, wherein the configuration data comprises bypass test configuration data of a specified computing module;

the upper computer sends test source data to the FPGA;

and the FPGA receives the test source data, and forwards the test source data in a specified calculation module according to the configuration data without performing calculation processing to obtain test result data.

4. The testing method of any one of claims 1 to 3, further comprising:

the upper computer receives the test result data;

and the upper computer compares the test source data sent to the FPGA with the received test result data, and if the test source data sent to the FPGA is consistent with the received test result data, the test result data specified by the FPGA are determined to be normal.

5. The test method of claim 1, wherein the FPGA comprises a plurality of computing modules, the test method further comprising:

the specified test configuration data comprises calculation test configuration data of a specified calculation module, and if the FPGA receives the calculation test configuration data of the specified calculation module, the FPGA only performs calculation processing of the specified calculation module and does not perform calculation processing of other calculation modules when processing the test source data.

6. The testing method of claim 1, further comprising:

the appointed test module configuration data comprises appointed full-module test configuration data, and if the FPGA receives the appointed full-module test configuration data, the FPGA processes data of all modules when processing test source data, including calculation processing of all calculation modules.

7. The test method of claim 5 or 6, further comprising: the upper computer receives the test result data;

the upper computer obtains standard result data according to the test source data and the configuration data sent to the FPGA;

and the upper computer compares the standard result data with the test result data, and if the standard result data is consistent with the test result data, the data processing result of the FPGA specified test is determined to be normal.

8. The testing method of claim 7, wherein the testing method comprises: the test source data is to-be-encrypted or to-be-decrypted data learned by the federation.

9. The method for the engineering test of the FPGA link module is characterized in that the FPGA is applied to a heterogeneous processing system for federal learning, the heterogeneous processing system comprises an upper computer and the FPGA, and the test method comprises the following steps:

the upper computer sends test source data to a preset address in the FPGA memory;

the upper computer reads the test result data from the preset address in the FPGA memory;

and the upper computer compares the read test result data with the sent test source data, and if the read test result data is consistent with the sent test source data, the upper computer determines that the link module is normal.

10. A machine-readable storage medium having stored thereon executable instructions that, when executed, cause a machine to perform the method of any one of claims 1 to 9.