CN111999064A

CN111999064A - Engine health monitoring unit

Info

Publication number: CN111999064A
Application number: CN202010613031.XA
Authority: CN
Inventors: 张俊伟; 李争超; 谷新宇; 李亮; 舒伟华; 李姣
Original assignee: AECC South Industry Co Ltd
Current assignee: AECC South Industry Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-11-27

Abstract

The invention discloses an engine health monitoring unit, which comprises a main processor system and a multi-channel communication and signal acquisition system, wherein the main processor system comprises a main processor, a memory and an Ethernet interface and is used for storing and managing engine data, diagnosing states, predicting health, predicting trends, making maintenance decisions and the like; the multi-channel communication and signal acquisition system comprises a DSP processor, an FPGA chip and a dual-port RAM, wherein the DSP processor is used for synchronously acquiring data of each engine according to a set period, identifying important faults according to the synchronously acquired data of each engine, outputting alarm signals to an on-board alarm indicator lamp and transmitting a synchronized combined data packet to a main processor; and the FPGA chip is used for receiving the data of each engine, preprocessing the data and transmitting the preprocessed data to the DSP processor. The invention improves the performances of system reliability, safety and the like, overcomes the performance bottleneck, and can better meet the requirement of engine health management and the identification of important faults.

Description

Engine health monitoring unit

Technical Field

The invention relates to the technical field of health monitoring of aero-engines, in particular to an engine health monitoring unit.

Background

The engine health monitoring unit is an airborne part of the engine health management system and is responsible for standard functions of the engine state monitoring unit such as engine data acquisition, data screening and engine state detection, and gradually undertakes data analysis functions such as engine health prediction, trend prediction and maintenance decision along with rapid improvement of hardware performance of an embedded system, and simultaneously can send a state detection result and a health prediction result of the engine to an avionic system of the airplane in real time through an airborne bus communication interface for display, so that airplane maintenance personnel can make proper decisions on engine maintenance work or troubleshooting work. The engine health monitoring unit can also store the acquired engine data, state detection and data analysis results in an internal large-capacity storage device, so that the engine data, the state detection and the data analysis results can be quickly exported through a special maintenance cable of the engine health monitoring unit connected with a ground analysis system on the ground, and more comprehensive data analysis and maintenance decision can be carried out by means of the powerful performance of a computer of the ground analysis system.

The existing engine health monitoring unit is generally a hardware architecture of a high-performance embedded processor and an external extended FPGA chip, health monitoring unit control software runs on the processor, the FPGA chip extends an external interface of the processor, manages other memory chips mounted on an external bus of the processor, and performs primary processing on communication data, analog signals and switching value signals which are planned to be acquired.

However, as the system requirements of the engine health monitoring unit are increasingly complicated, more engine parameter data with different attributes and different sources need to be acquired by the engine health monitoring unit, and if a hardware architecture of a single processor is still adopted, the acquisition of the data occupies too many processor resources, so that the performance of the engine health monitoring unit is quickly subjected to a bottleneck, and data management and analysis functions such as data screening, state detection, health prediction, trend prediction and the like cannot be better realized to meet the engine health management requirements.

In addition, after the engine health monitoring unit acquires data of an engine electronic control system, data of an aircraft avionics system and acquired data of a sensor special for the health monitoring unit, some engine faults with higher severity are often monitored in real time, warning information is immediately output when the faults occur, and technical requirements for immediate processing of pilots are required, such as low lubricating oil level faults, engine vibration overrun faults, lubricating oil abrasive dust standard exceeding faults and the like.

Therefore, continuing to employ a single processor architecture, it is no longer appropriate to put the data acquisition function and the alarm function for certain levels of importance faults into practice with other engine health monitoring functions.

Disclosure of Invention

The invention provides an engine health monitoring unit, which aims to solve the technical problems that the existing engine health monitoring unit is easy to have performance bottleneck, cannot better realize data management and analysis functions to meet the engine health management requirement, cannot identify part of important faults and cannot output alarms in time.

The technical scheme adopted by the invention is as follows:

an engine health monitoring unit comprises a main processor system and a multi-channel communication and signal acquisition system which are connected by a circuit,

the main processor system comprises a main processor, a memory and an Ethernet interface which are connected by a circuit and is used for storing and managing acquired engine data, diagnosing state, predicting health, predicting trend, making maintenance decision, uploading data to a ground analysis system, downloading system configuration parameters from the ground analysis system and upgrading a program;

the multichannel communication and signal acquisition system comprises a DSP processor, an FPGA chip and a dual-port RAM, wherein the DSP processor and the FPGA chip are connected by a circuit, the dual-port RAM is used for realizing data transmission between the DSP processor and a main processor, the DSP processor is used for synchronously acquiring data of each engine according to a set period, identifying important faults according to the synchronously acquired data of each engine, outputting alarm signals to an on-board alarm indicator lamp and transmitting a synchronous combined data packet to the main processor; the FPGA chip is used for receiving and preprocessing the data of each engine collected by the multi-path engine health monitoring sensor and then transmitting the preprocessed data to the DSP processor.

Further, the FPGA chip includes:

4 rotating speed measuring interface modules, 1 lubricating oil level measuring interface module, 4 vibration signal measuring interface modules, 6 RS422 receiving interface modules and 1 ARINC429 transceiver interface module,

the 4 rotating speed measurement interface modules comprise a delay filter, a pulse counter, a control register, a data register and a state register, and are used for receiving square wave periodic signals after filtering and shaping of a rotating speed signal conditioning circuit, firstly, narrow pulses with microsecond magnitude caused by external interference are filtered through the delay filter, then, counter difference values between rising edges or falling edges of the square wave periodic signals are measured in the pulse counter by utilizing clock signals inside an FPGA chip, after the difference values are continuously obtained for 2 times, the average values are automatically obtained and written into the data register, the control register is used for enabling rotating speed measurement and configuring rising edge/falling edge collection, and the state register is used for indicating rotating speed measurement ending state information; the 4 paths of rotating speed signals respectively correspond to a rotating speed measuring module and work independently and in parallel, and after the rotating speed measuring result is inquired and read by the DSP processor at regular time, the rotating speed value is obtained through calculation and processing;

the lubricating oil level measuring interface module comprises an SPI (serial peripheral interface), a control register, a data register and a state register, and is used for receiving 2-path lubricating oil level signals conditioned by the lubricating oil level conditioning circuit by means of an external single ADC (analog to digital converter) chip, regularly reading a sampling result of the ADC chip through the SPI, writing the sampling result into the data register for a DSP (digital signal processor) to read, controlling the sampling parameters by the control register, and indicating the state of the sampling process by the state register;

the vibration signal measurement interface module comprises an SPI interface, a control register, a state register, an original data cache, a frequency domain data cache, a digital filtering module, an FFT conversion module and a data cache module, and is used for continuously sampling 4 paths of vibration signals conditioned by a vibration signal conditioning circuit according to a set period through an ADC chip, reading sampling results through the SPI interface, and respectively writing the sampling results into the data caches distributed to the vibration signal measurement modules, wherein the data caches are double caches and are used for alternately storing the sampled vibration data to ensure that the newly sampled data can still be correctly stored when the data processing is carried out at the later stage, after the data cache 1 is full of data, the data is taken out from the cache 1 and is transmitted to the digital filtering module and the FFT conversion module to carry out digital filtering and fast Fourier transform to obtain frequency domain data, and the newly sampled data is written into the data cache 2, the digital filtering can filter noise and interference superposed in an original sampling signal, then the fast Fourier transform is carried out to obtain frequency domain data, the original data cache and the frequency domain data cache respectively store the filtered vibration signal original data and the frequency domain data for the DSP processor to read and then combine with other engine parameters to realize the judgment of the vibration overrun fault, the control register is used for controlling the sampling parameters, and the state register is used for indicating the state of the sampling process;

the RS422 receiving interface module comprises a baud rate generator, a serial-parallel conversion module, a multi-stage FIFO, a control register, a state register and a data register, wherein the control register is used for setting the baud rate, a stop bit, a data bit and a check bit, the serial-parallel conversion module is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and the state register is used for indicating a receiving result, a check result and an FIFO state; the depth of the multi-stage FIFO meets the storage requirement of the most communication data received within a fixed period interval at a set baud rate, the data register is read by a DSP processor so as to take out the received data cached in the multi-stage FIFO, and 6 RS422 receiving modules respectively correspond to 6 paths of RS422 interfaces and can simultaneously receive the data;

the ARINC429 transceiver interface module comprises a receiving part and a transmitting part, wherein the data flow direction of the transmitting part is opposite to that of the receiving part, the receiving part and the transmitting part both comprise a baud rate generator, a serial-parallel conversion module, a multi-stage FIFO, a control register, a state register and a data register, the control register is used for setting the baud rate, a stop bit, a data bit and a check bit, the serial-parallel conversion module is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and the state register is used for indicating a receiving result, a check result and an FIFO state; the depth of the multi-stage FIFO meets the storage requirement of the most communication data received within a fixed period interval at a set baud rate, wherein a serial-parallel conversion module in the receiving part is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and a data register is used for a DSP processor to read so as to take out the received data cached in the multi-stage FIFO; the data register in the sending part is used for receiving data contents to be sent by the DSP, and serial data signals are output according to a set baud rate through parallel-serial conversion after the data contents are cached by the multi-stage FIFO;

the ARINC429 transceiver module has a parameter word of 32 bits and does not include a start bit and a stop bit, the serial-parallel conversion module can receive the parameter word of 32 bits long, and the multi-stage FIFO and the data register are 32 bits.

Furthermore, the multi-channel communication and signal acquisition system also comprises a vibration signal conditioning circuit, a rotating speed signal conditioning circuit and a lubricating oil level conditioning circuit,

the vibration signal conditioning circuit is connected with each vibration sensor circuit and is used for converting output signals of each vibration sensor into voltage signals, amplifying and filtering the voltage signals, sampling the voltage signals by a high-speed ADC (analog to digital converter) sampling chip, and uploading ADC sampling results to the FPGA chip through an SPI (serial peripheral interface);

the rotating speed signal conditioning circuit is connected with the rotating speed sensor circuits and is used for obtaining square wave periodic signals after the output signals of the rotating speed sensors are subjected to proportional amplification and filtering shaping and uploading the square wave periodic signals to the FPGA chip, and finally the FPGA chip collects the frequency of the square wave periodic signals to obtain digitized rotating speed signals;

the lubricating oil level conditioning circuit is connected with lubricating oil level sensor circuits of the left engine and the right engine and used for conditioning output signals of the lubricating oil level sensors to corresponding analog voltage signals, sampling is carried out by the high-speed ADC sampling chip to obtain digital signals, and ADC sampling results are uploaded to the FPGA chip through the SPI.

Further, the power supply system comprises an input power supply filter circuit connected with a power supply circuit, the output end of the input power supply filter circuit is respectively connected with the first power supply conversion circuit and the second power supply conversion circuit, the power supply is provided by an on-board dc 28V power supply when the engine health monitoring unit is installed on the aircraft, the ground analysis system provides the ground analysis, the input power filter circuit is used for filtering noise and interference superposed on an external power supply, inhibiting surge peak current or voltage, and providing overcurrent protection by including a self-recovery fuse, the first power conversion circuit is used for converting 28V direct current into direct current power of various voltages required by devices in the multi-channel communication and signal acquisition system, the second power conversion circuit is used for providing the direct current power supply with various required voltages for the main processor system.

Furthermore, the dual-port RAM is used for realizing data transmission between the DSP processor and the main processor, and the left and right sets of address data buses are respectively connected to the DSP processor and the main processor and used for reading and writing by the DSP processor and the main processor in turn according to a period;

the dual-port RAM comprises two storage areas, wherein one storage area is used for storing a data packet sent to the main processor by the DSP processor, the other storage area is used for storing a data packet returned to the DSP processor by the main processor, and when the DSP processor acquires complete and effective engine data, airplane data and sensor data according to a period and confirms that the dual-port RAM chip is in a writable state, all data are packaged and written into the storage area distributed for the data packet in the dual-port RAM; when the main processor writes back the inquired engine health data into the other storage area of the dual-port RAM chip according to an ARINC429 inquiry instruction in a data packet sent by the DSP processor, the DSP processor reads the returned data in time and further sends the returned data to the aircraft avionics system for display through an ARINC429 transceiver interface module, and a pilot or an engine maintenance person judges the state of the engine to perform fault diagnosis or engine maintenance.

Furthermore, the DSP processor and the main processor are connected through two GPIOs to serve as synchronous signals between the DSP processor and the main processor, including GPIO1 and GPIO2, the GPIO1 is the DSP processor output to the main processor, GPIO2 is the main processor output to the DSP processor, used for mutually informing the opposite side whether the data reading and writing in the double-end RAM are finished or not, informing the opposite side to take away the data, the DSP processor inquires the state of the GPIO2 before writing data, ensures that the main processor reads a data packet returned by the main processor from the dual-port RAM after the main processor does not read and write data, then the DSP processor writes the data packet obtained by synchronizing and combining various types of collected data and communication data into a corresponding storage area, then changes the state of the GPIO1 to notify the host processor to take data sent by the DSP processor in the dual port RAM, and if the ARINC429 transceiver module receives an ARINC429 query command, and the main processor packs the inquired data content and writes the data content into the dual-port RAM and waits for the DSP processor to take away the data content.

And furthermore, the alarm signals output by the DSP processor comprise 4 paths of alarm signals, namely, a lubricating oil level low alarm, a vibration overrun alarm, a lubricating oil abrasive dust standard exceeding alarm and an EMU fault alarm, 4 GPIO pins of the DSP processor drive a switch tube to output, the 4 paths of alarm signals all adopt a low-end switch form, when the low-end switch form is adopted, the switch is driven to be closed only when the engine monitoring unit normally works and the alarm fault is not identified, the alarm indicating lamp normally displays, and when the engine health monitoring unit identifies the alarm fault, the alarm indicating lamp is turned off by disconnecting the switch to prompt a pilot to process the alarm information.

The pilot dials the manual event trigger switch, the switch is closed, the external switch quantity is processed by the comparator circuit and then is connected to the GPIO interface of the DSP processor, the GPIO interface detects that the switch quantity changes from high to low, the changed switch state information is inserted into a data packet sent to the main processor, the main processor is informed to carry out snapshot storage of data, the main processor self-checking signal is sampled by the DSP processor and then is used for judging the self-checking result of the main processor system, self-checking qualification or fault is indicated through high-low conversion, and then the DSP processor determines the output state of EMU fault alarm according to the self-checking result.

Furthermore, the DSP processor is provided with three levels of annular caches for caching communication data and collected data, each level of cache allocates space for all the communication data and the collected data, each type of data allocates storage space according to the system definition size, the DSP processor collects once communication data and collected data according to a set period and writes the communication data and the collected data of one level of the three levels of annular caches into a double-port RAM in a circulating manner, and the set period is consistent with the communication periods of 6 RS422 receiving interface modules and ARINC429 receiving and sending interface modules, the sampling periods of the vibration sensor, the rotating speed sensor, the lubricating oil level sensor and external switching value and the calculation period of frequency domain data;

the DSP processor is also used for setting a timer interrupt and inquiring state registers of all RS422 receiving interface modules and ARINC429 receiving and transmitting interface modules in the timer interrupt to check whether new receiving data exists, if the new receiving data exists, all the receiving data in the multistage FIFO are taken out by continuously reading corresponding data registers in all the interface modules, and preliminary judgment of data frames is carried out, wherein the data frames of the RS422 receiving interface modules are realized by a standard state machine, and the data frames of the ARINC429 receiving and transmitting interface modules are realized by analyzing parameter word identification parameter data of ARINC 429.

Further, the writing, by the DSP processor, the communication data and the collected data of one of the first-level caches in the third-level ring cache into the dual port RAM according to the set period specifically includes:

when no communication data enters a three-level annular cache of the DSP processor, after the 2 nd acquisition period is finished and the 3 rd period acquisition is started, the DSP processor reads out cache contents corresponding to the acquisition data written in the 1 st acquisition period, writes the cache contents into the dual-port RAM and receives the cache contents by the main processor;

when the communication data of the RS422 receiving interface module or the ARINC429 receiving and transmitting interface module with a certain channel is received for the first time, the counting of the timed interrupt is immediately cleared, the timing is restarted from 0, and the communication data received by the channel is written into the cache in which the current collected data is written; and writing the communication data of other channels which are started to be received into the cache in which the current acquired data is written before timing is restarted and a cycle time point is reached, writing the communication data of other channels which are started to be received into the next-level cache as the acquired data after timing is restarted and a cycle time point is reached, and writing the data in the first-level cache into the dual-port RAM when timing is restarted and two cycle time points are reached, so that the data is sent.

Compared with the prior art, the invention has the following beneficial effects:

the engine health monitoring unit of the invention sets up the main processor, including DSP processor and FPGA multi-channel communication and signal acquisition system of the chip, thus has proposed a kind of dual processor framework which realizes the engine health and monitors, has carried on the rational partition to the engine health management function, has designed the specialized multi-channel communication and signal acquisition system, is used for realizing the acquisition of the engine data and discerning some important engine trouble and outputting the alarm information in real time specially, the invention is favorable to confirming the different subsystems of the engine health monitoring unit as different safety design assurance levels, adopt different design guidance thoughts, adopt various measures in the multi-channel communication and signal acquisition system to improve the system reliability, reduce the failure rate, promote the security, and put the design focus on optimizing and implementing the health management algorithm in the main processor system, and the system performance is improved. Meanwhile, the asynchronous communication data and the collected data from different sources can be synchronized, various types of data which simultaneously occur and enter a system are configured, synchronized, combined and associated in a data packet, the difference of the actual occurrence time of various types of data in the data packet does not exceed a timing period, and the whole data packet is used as all relevant data of an engine at a certain moment and is used for further judging the state of the engine in an engine health management algorithm, and engine maintenance state and fault information jointly determined after the data in different states are combined are identified.

In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a block diagram of an engine health monitoring unit in accordance with a preferred embodiment of the present invention

Fig. 2 is a schematic diagram of internal functional modules of an FPGA chip according to a preferred embodiment of the present invention.

FIG. 3 is a three-level ring cache of the preferred embodiment of the present invention.

Fig. 4 is a schematic diagram of an RS422 serial port receiving state machine according to the preferred embodiment of the present invention.

Fig. 5 is a schematic diagram of a data collection and unloading sequence when no communication data exists after power-on according to the preferred embodiment of the present invention.

Fig. 6 is a timing diagram illustrating the first time communication data is received after power-up according to the preferred embodiment of the present invention.

Fig. 7 is a schematic diagram of the alarm signal output of the preferred embodiment of the present invention.

Fig. 8 is a schematic diagram of a dual port RAM connection in accordance with a preferred embodiment of the present invention.

FIG. 9 is a diagram of the main program of the DSP processor according to the preferred embodiment of the present invention.

FIG. 10 is a flow chart of the DSP processor timer interrupt process according to the preferred embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to FIG. 1, a preferred embodiment of the present invention provides an engine health monitoring unit comprising a main processor system and a multi-channel communication and signal acquisition system in circuit connection.

the multichannel communication and signal acquisition system comprises a DSP processor, an FPGA chip and a dual-port RAM, wherein the DSP processor and the FPGA chip are connected by a circuit, the dual-port RAM is used for realizing data transmission between the DSP processor and a main processor, the DSP processor is used for synchronously acquiring data of each engine according to a set period, identifying important faults according to the synchronously acquired data of each engine, outputting alarm signals to an on-board alarm indicator lamp and transmitting a synchronous combined data packet to the main processor; the FPGA chip is used for receiving and preprocessing the data of each engine collected by the multi-path engine health monitoring sensor and then transmitting the data to the DSP processor, and the set period is 48 ms.

The engine health monitoring unit of the embodiment is divided into a multi-channel communication and signal acquisition system and a main processor system. The multi-channel communication and signal acquisition system is responsible for realizing the functions of the engine health monitoring unit, such as acquiring engine data through communication and acquisition, identifying important faults according to the acquired data, outputting alarm signals, transmitting synchronized combined data packets to the main processor system and the like; the main processor system is responsible for realizing other health management functions of the engine health monitoring unit, such as state diagnosis, health prediction, trend prediction, maintenance decision and the like, and processing, analyzing, storing and uploading the acquired data.

The embodiment completely divides the alarm function of important faults into a multi-channel communication and signal acquisition system, thereby ensuring that each internal component module can adopt different safety design assurance levels when the engine health monitoring unit is designed. For example, the main processor system can be developed according to the E level, pay more attention to the excavation of the performance potential thereof, and design and realize a more perfect health management algorithm; and the module related to the alarm function in the multi-channel communication and signal acquisition system is distributed with higher safety design assurance level, such as C level, a system architecture with lower failure rate is selected during design, a series model with higher quality level is selected as a component, and a sufficient and sufficient signal return circuit and corresponding fault isolation measures are designed.

The main processor system comprises a main processor of the engine health monitoring unit, an embedded operating system (such as Linux, VxWorks, mu C/OS II and the like) can be further transplanted to the main processor for multitask management, an embedded file system (such as YAFFS2, JFFS2 and the like) is transplanted to store and manage engine data, and health management algorithms such as state diagnosis, health prediction, trend prediction, maintenance decision and the like are designed and realized. The main processor system also includes a multi-chip NAND FLASH storage device to store large volumes of data. The main processor system comprises a 1-path high-speed Ethernet interface which is used for carrying out network communication with the ground analysis system and quickly uploading data, the Ethernet interface is also used for downloading configuration parameters and maintaining and upgrading main processor software from the ground analysis system by the engine health monitoring unit, and when necessary, program working codes of the DSP processor can be received through the Ethernet interface and sent to the DSP processor through the dual-port RAM, and the DSP processor is further controlled to upgrade programs on line.

As can be seen, the engine health monitoring unit of the present embodiment employs a dual processor architecture: the main processor selects a processor/single chip microcomputer with strong performance to transplant an embedded operating system to realize multi-task calling and switching management, transplants an embedded file system to realize data management and storage, realizes health management algorithms such as state diagnosis, health prediction, trend prediction, maintenance decision and the like on the acquired engine data by using strong computing capacity, and respectively stores the original data, the processed data and the diagnosis and prediction results according to a predefined file format; the secondary processor is used as the core of an independent multi-channel communication and signal acquisition system, is specially responsible for the acquisition and synchronous work of engine data, judges certain important faults according to the acquired data, and outputs alarm information when the faults occur to require an aircraft operator to immediately process the faults.

The multi-channel communication and signal acquisition system with the secondary processor is characterized in that a hardware framework of a DSP processor and an FPGA chip is further selected, the DSP processor expands an external interface through the FPGA chip and manages an external bus of the DSP processor, and meanwhile, the FPGA chip carries out primary processing and acquisition on signals of a multi-channel engine health monitoring special sensor.

As shown in fig. 2, in a preferred embodiment of the present invention, the FPGA chip includes:

the 4 rotating speed measurement interface modules comprise a delay filter, a pulse counter, a control register, a data register and a state register, and are used for receiving square wave periodic signals after filtering and shaping of a rotating speed signal conditioning circuit, firstly, narrow pulses with microsecond magnitude caused by external interference are filtered through the delay filter, then, counter difference values between rising edges or falling edges of the square wave periodic signals are measured in the pulse counter by utilizing clock signals inside an FPGA chip, after the difference values are continuously obtained for 2 times, the average values are automatically obtained and written into the data register, the control register is used for enabling rotating speed measurement and configuring rising edge/falling edge collection, and the state register is used for indicating rotating speed measurement ending state information; the 4 paths of rotating speed signals respectively correspond to a rotating speed measuring module and work independently and in parallel, after the rotating speed measuring result is inquired and read by the DSP processor at regular time, the rotating speed value is obtained through calculation and processing, and the rotating speed value is combined with other engine parameters at the same time point to be judged and transmitted;

the vibration signal measurement interface module comprises an SPI interface, a control register, a state register, an original data cache, a frequency domain data cache, a digital filtering module, an FFT conversion module and a data cache module, wherein the vibration signal measurement interface module continuously samples 4 paths of vibration signals conditioned by a vibration signal conditioning circuit according to a set period through an independent ADC chip, after a sampling result is read through the SPI interface, the vibration signals are respectively written into the data caches distributed to the vibration signal measurement modules, the data caches are set to be double caches and used for alternately storing the sampled vibration data, the newly sampled data can still be correctly stored when the data processing is carried out at the later stage, after the data caches 1 are full of data, the data are taken out from the data caches 1 and are transmitted to the digital filtering module and the FFT conversion module for carrying out digital filtering and fast Fourier transform to obtain frequency domain data, the newly sampled data is written into a data cache 2, digital filtering can filter superposed noise and interference in original sampling signals, then fast Fourier transform is carried out to obtain frequency domain data, the original data cache and the frequency domain data cache respectively store the filtered vibration signal original data and the frequency domain data for the DSP processor to read and then combine with other engine parameters to realize judgment of vibration overrun faults, a control register is used for controlling sampling parameters, the state register is used for indicating the state of the sampling process, and SPI interfaces and control registers of 4 vibration signal measurement interface modules are shared; in each set period of 48ms, the ADC chip is continuously sampling, the number of sampling points in 48ms depends on the sampling rate, in an embodiment of the present invention, the sampling rate is 43Ksps, the number of sampling points in 48ms is 2064, the first 2048 sampling points are taken for fourier transform, and the depth of the obtained frequency domain data is 2048. And the DSP reads the original data cache and the frequency domain data cache of the vibration signal after the digital filtering, and performs further processing by combining other engine parameters (such as rotating speed) to realize the judgment of the vibration overrun fault. Each path of vibration signal is provided with a corresponding vibration signal measurement interface module, wherein a control register and an SPI interface are shared parts, and ADC sampling control of 4 paths of vibration signals is completed together.

The RS422 receiving interface module comprises a baud rate generator, a serial-parallel conversion module, a multi-stage FIFO, a control register, a state register and a data register, wherein the control register is used for setting the baud rate, a stop bit, a data bit and a check bit, the serial-parallel conversion module is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and the state register is used for indicating a receiving result, a check result and an FIFO state; the depth of the multi-stage FIFO meets the storage requirement of the most communication data received within a fixed period interval by setting the baud rate, such as 1ms timing interval, the baud rate of 115200bps, the most 12 bytes of data are communicated, the FIFO depth is set to 16 stages, and the requirement can be met. The data register is used for being read by the DSP processor so as to take out the received data cached in the multi-stage FIFO, and the 6 RS422 receiving interface modules respectively correspond to the 6 paths of RS422 interfaces and can receive the data simultaneously.

The ARINC429 transceiver interface module comprises a receiving part and a transmitting part, wherein the receiving part and the transmitting part respectively comprise a baud rate generator, a serial-parallel conversion module, a multi-stage FIFO, a control register, a state register and a data register, the control register is used for setting the baud rate, a stop bit, a data bit and a check bit, the serial-parallel conversion module is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and the state register is used for indicating the receiving result, the check result and the FIFO state; the depth of the multi-stage FIFO meets the storage requirement of the maximum communication data received within a fixed period interval by a set baud rate. The receiving part is similar to the RS422 receiving interface module, except that the ARINC429 receiving/transmitting interface module has 32-bit data word and does not contain start bit and stop bit, so that the multistage FIFO and the data register for serial-parallel conversion can correctly receive the data word with length of 32 bit. The data flow direction of the sending part is opposite to that of the receiving part, wherein a serial-parallel conversion module in the receiving part is used for acquiring data bytes and writing the data bytes into the multi-stage FIFO, and a data register is used for being read by a DSP processor so as to take out the received data cached in the multi-stage FIFO; and a data register in the sending part is used for receiving data contents to be sent by the DSP processor, and outputting serial data signals according to a set baud rate through parallel-serial conversion after the data contents are cached by the multi-stage FIFO. In the embodiment, by utilizing the programmable characteristic and the parallel operation characteristic of the FPGA chip, one FPGA chip is selected to expand the external interface of the DSP processor, and the communication data and the collected data are subjected to primary processing.

Receiving 4 paths of engine data of a left engine electronic controller AB two channels and a right engine electronic controller AB two channels from an RS422 interface expanded by an FPGA chip and two paths of lubricating oil abrasive dust data respectively corresponding to a left engine and a right engine, receiving aircraft data sent by an aircraft avionic system from an ARINC429 interface expanded by the FPGA chip, returning the engine health data to the aircraft avionic system for display according to an inquiry instruction sent by the aircraft avionic system, reading the detected 4 paths of rotating speed data, 2 paths of lubricating oil level data and 4 paths of vibration signal data from the FPGA chip, identifying lubricating oil low fault, vibration oil level fault and lubricating oil abrasive dust standard exceeding fault defined in system safety analysis according to communication data and collected data, and outputting corresponding alarm signals, and outputting fault alarm information of an engine health monitoring unit according to a self-detection result output by a main processor system and a result of a self-detection program run by a DSP processor, an onboard manual event operated by a pilot triggers a switch signal to be sampled and periodically writes communication data, collected data and some state parameters of the DSP processor into the dual port RAM to be transmitted to the main processor for data analysis.

In the preferred embodiment of the invention, the multi-channel communication and signal acquisition system further comprises a vibration signal conditioning circuit, a rotating speed signal conditioning circuit and an oil level conditioning circuit,

the vibration signal conditioning circuit is connected with each vibration sensor circuit, and is used for converting charge signals output by each vibration sensor (the vibration sensor is a piezoelectric acceleration sensor, and output signals are charge type signals) into voltage signals through an integrating circuit, amplifying and filtering weak voltage signals to obtain voltage signals meeting the ADC sampling voltage range, and connecting the voltage signals to an ADC chip.

The rotating speed signal conditioning circuit is connected with each rotating speed sensor circuit and used for carrying out proportional amplification on output signals of each rotating speed sensor (the rotating speed sensor is a magnetoelectric sensor and outputs voltage signals along with the rotation of a rotor) through voltage signals by a difference circuit, an amplification circuit and a filter circuit, carrying out waveform shaping by a comparator and an inverter to obtain square wave periodic pulses and uploading the square wave periodic pulses to an FPGA chip, and finally carrying out rotating speed measurement by the FPGA chip according to the frequency of the square wave periodic signals to obtain digitized rotating speed signals.

The lubricating oil level conditioning circuit is connected with lubricating oil level sensor circuits of left and right engines and used for amplifying and filtering voltage signals output by the lubricating oil level sensor to corresponding analog voltage signals, sampling is carried out by a high-speed ADC sampling chip to obtain digital signals, ADC sampling results are uploaded to an FPGA chip through an SPI interface, and the FPGA chip controls the ADC chip to carry out sampling at fixed time intervals through the SPI interface.

In a preferred embodiment of the present invention, the engine health monitoring unit further includes a power supply system, the power supply system includes an input power filter circuit connected to the power supply circuit, an output end of the input power filter circuit is respectively connected to a first power conversion circuit and a second power conversion circuit, the power supply is provided by an onboard dc 28V power supply when the engine health monitoring unit is installed in an onboard, and is provided by a ground analysis system when the engine health monitoring unit is installed on the ground, the input power filter circuit is used for filtering noise and interference superimposed on an external power supply, suppressing surge peak current or voltage, and including a self-recovery fuse to provide overcurrent protection, the first power conversion circuit is used for converting the 28V dc into +15V, -15V, 5V, 3.3V, and a voltage required by devices in the multichannel communication and signal acquisition system, The second power supply conversion circuit is used for providing the required 5V, 3.3V, 1.8V and 1.2V direct-current power supplies for the main processor system.

The embodiment provides the main processor system and the multi-channel communication and signal acquisition system with respective independent power conversion circuits, which is beneficial to realizing better power distribution and thermal design, is also beneficial to reducing the failure rate of the power circuit in the multi-channel communication and signal acquisition system, and meets the requirement of safety assurance level.

As shown in fig. 8, in the preferred embodiment of the present invention, the dual-port RAM is used to implement data transmission between the DSP processor and the main processor, and the left and right sets of address data buses are respectively connected to the DSP processor and the main processor, and are used to be alternately read and written by the DSP processor and the main processor according to a period;

the DSP processor sends a packet to the host processor every 48ms by writing the buffered data into the dual port RAM. The dual-port RAM comprises two storage areas, wherein one storage area is used for storing a data packet sent to the main processor by the DSP processor, the other storage area is used for storing a data packet returned to the DSP processor by the main processor, and when the DSP processor acquires complete and effective engine data, airplane data and sensor data according to a period and confirms that the dual-port RAM chip is in a writable state, all data are packaged and written into the storage area distributed for the data packet in the dual-port RAM; when the main processor writes back the inquired engine health data into the other storage area of the dual-port RAM chip according to an ARINC429 inquiry instruction in a data packet sent by the DSP processor, the DSP processor reads the returned data in time and further sends the returned data to the aircraft avionics system for display through an ARINC429 transceiver interface module, and a pilot or an engine maintenance person judges the state of the engine to perform fault diagnosis or engine maintenance.

In addition, when the dual-port RAM chip is used as a channel for fast transmission of large-capacity data between a DSP processor and a main processor, the DSP processor and the main processor are connected through two GPIOs to serve as synchronous signals between the DSP processor and the main processor, the GPIO1 and the GPIO2 are included, the GPIO1 is used for outputting the DSP processor to the main processor, the GPIO2 is used for outputting the main processor to the DSP processor and mutually informing the opposite side whether the data reading and writing in the dual-port RAM are completed or not and informing the opposite side to take away the data, the DSP processor inquires the state of the GPIO2 before writing the data to ensure that the main processor reads a data packet returned from the dual-port RAM after the data is not read and written by the main processor to avoid reading and writing conflicts, then the DSP processor synchronizes various types of collected data and communication data and writes the combined data packet into a corresponding storage area, then changes the state of the GPIO1 and informs, if ARINC429 transceiver module receives ARINC429 inquiry command, the main processor packs the inquired data content and writes the data content into the dual-port RAM and waits for the DSP processor to take away.

In one embodiment of the invention, the IDT70V28L is selected by the dual port RAM chip, the IDT70V28L has the capacity of 64 Kx 16 bits, the fast access time of 20ns is high, and the typical working power consumption is 0.44W. The DSP processor is connected with a left-end bus of the dual-port RAM, the dual-port RAM is mapped to an area of an external storage space of the dual-port RAM, the main processor is connected with a right-end bus of the dual-port RAM, and the internal storage space of the dual-port RAM chip is directly read and written through bus connection.

In the preferred embodiment of the invention, the alarm signals output by the DSP processor comprise 4 paths of alarm signals, namely, an oil level low alarm, a vibration overrun alarm, an oil wear standard exceeding alarm and an EMU fault alarm, 4 GPIO pins of the DSP processor drive a switch tube to output, and in order to ensure that the alarm signals can still be reliably output when the engine health monitoring unit fails, the 4 paths of alarm signals all adopt a low-end switch form, which is shown in figure 7. The low-end switch has the advantages that the switch is driven to be closed only when the engine monitoring unit works normally and the alarm fault is not identified, and the alarm indicating lamp displays normally. When the engine health monitoring unit identifies an alarm fault, the alarm indicating lamp is turned off by disconnecting the switch to prompt the pilot to process the alarm information, and even if the engine health monitoring unit is damaged and cannot work normally, the alarm indicating lamp is in a turned-off state by default to prompt the pilot to process the alarm information.

In a preferred embodiment of the present invention, the engine monitoring unit further includes an external manual event trigger switch, after the pilot toggles the manual event trigger switch, the switch is closed, an external switching value of the switch is processed by the comparator circuit and then connected to a GPIO interface of the DSP processor, the GPIO interface detects that the switching value changes from high to low, inserts the changed switch state information into a data packet sent to the main processor, and notifies the main processor to perform snapshot storage of data, the main processor self-check signal is sampled by the DSP processor and then used for determining a self-check result of the main processor system, and the self-check is passed or failed through high-low conversion, and then the DSP processor determines the output state of the EMU fault alarm in combination with the self-check result of the DSP processor.

In a preferred embodiment of the present invention, the DSP processor is provided with three levels of ring buffers for buffering communication data and collected data, each level of buffer allocates a space for all communication data and collected data, each type of data allocates a storage space according to its system-defined size, the DSP processor collects once communication data and collected data according to a set period and writes them cyclically into one of the three levels of ring buffers, and writes the communication data and collected data of one of the three levels of ring buffers into a dual port RAM according to a set period, the set period is consistent with communication periods of 6 RS422 receiving interface modules and ARINC429 transceiver interface modules, sampling periods of the vibration sensor, the rotation speed sensor, the lubricant level sensor and external switching values, and a calculation period of frequency domain data; the DSP processor is also used for setting a timer interrupt and inquiring state registers of all RS422 receiving interface modules and ARINC429 receiving and transmitting interface modules in the timer interrupt to check whether new receiving data exists, if the new receiving data exists, all the receiving data in the multistage FIFO are taken out by continuously reading corresponding data registers in all the interface modules, and preliminary judgment of data frames is carried out, wherein the data frames of the RS422 receiving interface modules are realized by a standard state machine, and the data frames of the ARINC429 receiving and transmitting interface modules are realized by analyzing parameter word identification parameter data of ARINC 429.

The common realization scheme for receiving serial port communication data by the embedded processor/single chip microcomputer is serial port receiving interruption, and the advantages of response timeliness and better real-time property are realized by utilizing the interruption. However, for the multi-channel communication and signal acquisition system of the present invention, the number of channels is large, and data from multiple sources may enter the system at the same time, and if the interrupt mode is still adopted, a more complicated interrupt priority and interrupt nested structure need to be designed, which is likely to cause the problem that communication data is lost due to untimely processing.

Therefore, the DSP processor of this embodiment is configured to receive multi-channel serial communication data in a timed-query manner: in order to solve the bottleneck of insufficient peripheral interfaces of the DSP processor, the embodiment obtains 6 RS422 interfaces and 1-way ARINC429 interface by FPGA chip extension; in order to ensure that all serial port data in the query time interval are processed in time, a multi-stage FIFO with enough depth is designed for each serial port channel to receive data in the FPGA chip to buffer the received data, and the DSP processor only needs to read the data in the FIFO when receiving the data in a query mode; the method comprises the steps that by means of an external bus of a DSP (digital signal processor), a control register, a state register and a data register of an interface expanded by an FPGA (field programmable gate array) chip are mapped into a bus storage space of the DSP, a fixed address is distributed to each register, the DSP writes the control register to configure attributes of each serial port channel, such as baud rate, data bits, check bits and the like, reads the state register to obtain the state of each serial port, such as port attributes, FIFO full/empty states and the like, reads the data register to take serial port receiving data, an outlet of the FIFO is associated with the data register, and a plurality of data in a plurality of stages of FIFOs can be taken out through the continuous multi-time data reading register.

The serial port communication data and the signal acquisition data of different channels acquired by the DSP processor are typical asynchronous data, and in order to synchronize the data and generate time correlation so as to comprehensively judge all parameters and engine states of an engine at a certain moment in data analysis and calculation, the DSP processor is provided with a three-level annular cache for caching the communication and the acquisition data, and the structure of the three-level annular cache is shown in figure 3. Space is distributed for all communication data and collected data in each level of cache, storage space is distributed for each type of data according to the system definition size, engine data of a right engine and a left engine AB, oil and wear debris data of the right engine and the left engine, and avionic data of an airplane are all communication data, vibration signal original data are data of collected 4 paths of vibration sensor signals, vibration signal frequency domain data are frequency domain data obtained by Fourier transformation of 4 paths of vibration signal original data on an FPGA chip respectively, the sensor collected data comprise collected data of 4 paths of rotating speed sensors, oil level signal data of 2 paths of oil, external switching value input such as manual event triggering and the like, and DSP state and fault words comprise a result of data receiving by a DSP processor communication program, a result of collecting sensor signals, a DSP self-checking result and the like, for example, whether each channel receives a data frame, whether the data frame is qualified or not, whether the range of the data collected in each channel is judged/the change rate is judged, the self-checking result of the DSP, and the identified alarm information and fault information.

In order to reduce the difficulty of synchronization among multi-channel communication data and increase the relevance among the data, the engine health monitoring unit sets the communication periods of the 6-channel RS422 interface and the 1-channel ARINC429 interface to be T, and in one embodiment of the invention, the T is 48 ms. Correspondingly, after the vibration signal is continuously sampled for 48ms according to the required sampling rate, primary spectrum conversion is carried out on the original data within 48ms, and frequency domain data of the original data are calculated. The sampling period of the revolution speed sensor, the oil level sensor signal and the external switching value input is also 48 ms. And the DSP processor writes the collected and communicated data in the primary cache into the dual-port RAM every 48ms, so that the data are sent to the main processor to carry out data analysis.

The DSP processor enables 1 timed interrupt with 1ms period, status registers of a plurality of serial port channels are inquired in the interrupt to check whether new received data exists, if the new received data exists, all the received data in the FIFO are taken out by continuously reading the data register corresponding to the channel, and preliminary judgment of data frames is carried out. The judgment of the RS422 serial data frame is realized by a standard state machine, as shown in fig. 4. The RS422 serial port data frame receiving is firstly in a frame head searching state, after a frame head conforming to a protocol is received, the state is switched to a data receiving state, data receiving is started, after data content meeting the frame length requirement is received, the state is switched to a data frame checking state, checking words of the data frame are calculated and compared with the checking words contained in the data frame to determine the correctness of the data frame, after the data frame checking is completed, the state is switched back to the frame head searching state, and the frame head is searched from the serial port receiving data again.

The ARINC429 bus communication does not need a state machine, each ARINC429 parameter word is 32 bits, and after the parameter words are received, the analysis is carried out according to an ARINC429 communication protocol, parameter data are identified from the parameter words and are written into a cache.

When the DSP processor is powered on, the peripheral is initialized, 1ms timed interruption is enabled, received data of the RS422 interfaces of the 6 channels and the ARINC429 interfaces of the 1 channel are counted and read in a query mode in the timed interruption, and when ARINC429 sends data to wait for sending, the data are written into corresponding data registers in the FPGA chip and then are sent to the aircraft avionics system by the FPGA chip. And acquiring a rotating speed sensor signal, a lubricating oil level signal, vibration original data, frequency domain data, external input switching value and other acquired data every 48ms, and circularly writing the acquired data into one of the 3-level caches.

In a preferred embodiment of the present invention, the writing, by the DSP processor, the communication data and the collected data of one of the level three ring caches into the dual port RAM according to a set period specifically includes:

as shown in fig. 5, when no communication data enters the third-level ring cache of the DSP processor, after the 2 nd acquisition cycle is finished, and when the 3 rd cycle acquisition is started, the DSP processor reads out and writes the cache content corresponding to the acquisition data written in the 1 st acquisition cycle into the dual-port RAM, and receives the cache content by the main processor;

as shown in fig. 6, when the communication data of the RS422 receiving interface module or the ARINC429 transceiver interface module having a certain channel is received for the first time, the count of 1ms timer interrupt is immediately cleared, the timing is restarted from 0, and the communication data received by the channel is written into the cache in which the currently acquired data is written; and writing the communication data of other channels which are started to be received into the second-level buffer before the timekeeping is carried out again and the communication data of other channels which are started to be received after the timekeeping is carried out again and the 48ms timepoint are written into the third-level buffer as the collected data, so that the possibility that one channel starts to receive data before the 48ms timepoint, but one frame of complete data is received after the 48ms timepoint, and the frame data crosses the 48ms timepoint is realized. At the time point of 96ms, the communication data and the collected data in the first-level cache are definitely completely updated in place, and no unfinished communication data is received to wait for writing, so that the data in the first-level cache is written into the dual-port RAM when the timing is restarted and the time point of 96ms is reached, and the data is sent.

Through the two scenarios illustrated in fig. 5 and 6, at each interval of 48ms, data buffered in one of the 3-level ring buffers is unloaded to the dual-port RAM, so that a large amount of data is transmitted to the main processor. And the difference of the actual occurrence time between the collected data in the 3-level ring buffer and the communication data of each channel does not exceed 48ms, and the collected data and the communication data can be comprehensively analyzed as all available associated data of a certain time point engine, and the synchronization of asynchronous collected data and communication data of various sources can be completed through the mechanism.

The DSP processor program is a foreground and background program framework, the foreground is a 1ms timed interrupt program, and the background is a while (1) work cycle. The program flow chart is shown in fig. 9 and fig. 10. The 1ms timed interrupt program realizes the receiving and sending of multi-channel communication data and the acquisition of signal data of a sensor special for an engine health monitoring unit, while (1) working cycle in the main function is responsible for writing data in one of the three levels of annular caches into the dual-port RAM in turn and reading data returned by a main processor in the dual-port RAM, thereby completing the data exchange with the main processor. And then comprehensively judging whether a predefined important fault occurs according to the synchronized and combined collected data and communication data, if so, outputting an alarm signal in time, updating the detected fault to the DSP state in the three-level annular cache and the corresponding position of the fault word, and further sending the fault word to a main processor for analysis and storage.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An engine health monitoring unit is characterized by comprising a main processor system and a multi-channel communication and signal acquisition system which are connected by a circuit,

2. The engine health monitoring unit of claim 1,

the FPGA chip comprises:

3. The engine health monitoring unit of claim 2,

the multi-channel communication and signal acquisition system also comprises a vibration signal conditioning circuit, a rotating speed signal conditioning circuit and a lubricating oil level conditioning circuit,

4. The engine health monitoring unit of claim 1,

also comprises a power supply system, the power supply system comprises an input power supply filter circuit connected with the power supply circuit, the output end of the input power supply filter circuit is respectively connected with the first power supply conversion circuit and the second power supply conversion circuit, the power supply is provided by an on-board dc 28V power supply when the engine health monitoring unit is installed on the aircraft, the ground analysis system provides the ground analysis, the input power filter circuit is used for filtering noise and interference superposed on an external power supply, inhibiting surge peak current or voltage, and providing overcurrent protection by including a self-recovery fuse, the first power conversion circuit is used for converting 28V direct current into direct current power of various voltages required by devices in the multi-channel communication and signal acquisition system, the second power conversion circuit is used for providing the direct current power supply with various required voltages for the main processor system.

5. The engine health monitoring unit of claim 3,

the dual-port RAM is used for realizing data transmission between the DSP processor and the main processor, and the left and right sets of address data buses are respectively connected to the DSP processor and the main processor and used for reading and writing by the DSP processor and the main processor in turn according to a period;

6. The engine health monitoring unit of claim 5,

the DSP processor and the main processor are connected through two GPIOs to serve as synchronous signals between the DSP processor and the main processor, and the synchronous signals comprise GPIO1 and GPIO2, the GPIO1 is the DSP processor output to the main processor, GPIO2 is the main processor output to the DSP processor, used for mutually informing the opposite side whether the data reading and writing in the double-end RAM are finished or not, informing the opposite side to take away the data, the DSP processor inquires the state of the GPIO2 before writing data, ensures that the main processor reads a data packet returned by the main processor from the dual-port RAM after the main processor does not read and write data, then the DSP processor writes the data packet obtained by synchronizing and combining various types of collected data and communication data into a corresponding storage area, then changes the state of the GPIO1 to notify the host processor to take data sent by the DSP processor in the dual port RAM, and if the ARINC429 transceiver module receives an ARINC429 query command, and the main processor packs the inquired data content and writes the data content into the dual-port RAM and waits for the DSP processor to take away the data content.

7. The engine health monitoring unit of claim 1,

the alarm signals output by the DSP processor comprise 4 paths of alarm signals, namely, a lubricating oil level low alarm, a vibration overrun alarm, a lubricating oil abrasive dust exceeding alarm and an EMU fault alarm, 4 GPIO pins of the DSP processor drive a switch tube to output the alarm signals, the 4 paths of alarm signals all adopt a low-end switch form, when the low-end switch form is adopted, a switch is driven to be closed only when an engine monitoring unit normally works and the alarm fault is not identified, an alarm indicator lamp normally displays, and when the engine health monitoring unit identifies the alarm fault, the alarm indicator lamp is turned off by disconnecting the switch to prompt a pilot to process the alarm information.

8. The engine health monitoring unit of claim 6,

the pilot toggles the manual event trigger switch, the switch is closed, the external switching value is connected to a GPIO interface of a DSP processor after being processed by a comparator circuit, the GPIO interface detects that the switching value changes from high to low, changed switching state information is inserted into a data packet sent to the main processor to inform the main processor to carry out snapshot storage of data, a main processor self-checking signal is sampled by the DSP processor and used for judging a self-checking result of a main processor system, self-checking qualification or failure is indicated through high-low conversion, and then the DSP processor determines the output state of EMU fault alarm by combining the self-checking result.

9. The engine health monitoring unit of claim 8,

the DSP processor is provided with three levels of annular caches for caching communication data and collected data, each level of cache allocates space for all the communication data and the collected data, each type of data allocates storage space according to the system defined size, the DSP processor collects once communication data and collected data according to a set period and writes the communication data and the collected data of one level of the three levels of annular caches into a dual-port RAM circularly, and the set period is consistent with the communication periods of 6 RS422 receiving interface modules and ARINC429 receiving and sending interface modules, the sampling periods of the vibration sensor, the rotation speed sensor, the lubricating oil level sensor and the external switching value and the calculation period of frequency domain data;

10. The engine health monitoring unit of claim 9,

the step of writing the communication data and the collected data of one level of the three levels of the annular caches into the dual-port RAM by the DSP processor according to a set period specifically comprises the following steps: