CN111987756A

CN111987756A - Charging circuit

Info

Publication number: CN111987756A
Application number: CN202010430704.8A
Authority: CN
Inventors: 夏原野; 陈华捷; 丁庆; 宁志远; 郭瑭瑭
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2020-05-20
Filing date: 2020-05-20
Publication date: 2020-11-24

Abstract

The application discloses charging circuit includes: a DC source providing a DC supply voltage; at least one power converter connected to the DC source for converting the DC supply voltage to an output voltage; at least one output port, which is respectively connected with the power converter and charges the load; the control circuit generates a switch control signal of the power converter according to a state signal of a load and the output voltage so as to adjust the output voltage, wherein the state signal of the load represents whether the output port has a load or not, and the power converter comprises an output capacitor connected between a first end and a second end of the output port; the charging circuit includes a bleed circuit that provides a bleed path for the output capacitance. According to the output capacitor circuit, under the conditions of using simpler devices and low cost, the bleeder circuit multiplexes the power converter or independently provides a bleeder channel for the output capacitor, stable output voltage is output when the output port is loaded, and the output voltage is reduced to a preset value when the output port is not connected with the load.

Description

Charging circuit

Technical Field

The invention relates to a power supply technology, in particular to a charging circuit for multi-path quick charging.

Background

In portable devices such as mobile phones, electronic books, tablet computers, notebook computers and the like, in order to ensure the cruising ability of the portable devices, the capacity of batteries of the portable devices is correspondingly increased, so that the charging time is too long, and the charging efficiency can be effectively improved by adopting a quick charging technology, so that the charging time of the portable devices is remarkably reduced. When the charging circuit is connected with a load, the output voltage of the charging circuit can be quickly established to charge the load; when the charging circuit is disconnected from the load, the output voltage of the charging circuit can be reduced to a preset value within a specified time.

Fig. 1 shows a schematic block diagram of a charging circuit in the prior art. As shown in fig. 1, the charging circuit includes an input circuit 11, a first power converter 12, a second power converter 13, and a control circuit 14. The input circuit 11 includes a capacitor Cin, a transformer T1, a primary power switch Q, a diode D1, and an output capacitor C1, and an input end of the input circuit 11 receives a dc input voltage Vin. The first power converter 12 includes a DC-DC conversion circuit with a load switch, which includes two power switching tubes Q11 and Q12, an inductor L1, a load switch S1, and a capacitor C12, and an output port with a bleed path, which includes a resistor R11 and an output port (not shown in the figure). The second power converter 13 is identical to the first power converter 12 and will not be described in detail here. The first power converter 12 and the second power converter 13 are connected in parallel across the output capacitor C1 of the input circuit 11. Taking the first power converter 12 as an example, when the control circuit 14 detects that the Load1 is connected to the output port of the first power converter 12, the Load switch S1 is turned on, and the power switches Q11 and Q12 are alternately turned on to supply power to the Load 1; upon detecting the removal of the Load1, the Load switch S1 turns off, and the output port voltage (the input voltage of the Load 1) is rapidly lowered to a preset value by the resistor R11.

The circuit shown in fig. 1 can realize two-way quick charging, and two-way voltages are not influenced by each other. But the output requirement of the charging circuit needs to be achieved through a load switch and a bleed channel. The load switch and the discharge channel not only increase the system loss and reduce the system efficiency, but also increase the system cost and volume, and are not beneficial to miniaturization.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a charging circuit, in which a bleeding circuit of the charging circuit multiplexes its power converter or provides a bleeding channel for an output capacitor alone, thereby reducing circuit components and circuit loss.

According to an aspect of the present invention, there is provided a charging circuit including: a DC source providing a DC supply voltage; at least one power converter connected to the DC source for converting the DC supply voltage to an output voltage; at least one output port, which is respectively connected with the power converter and charges the load; the control circuit is used for generating a switch control signal of the power converter according to a state signal of a load and the output voltage so as to adjust the output voltage, wherein the state signal of the load represents whether the output port is connected with the load or not; wherein the power converter comprises an output capacitor connected between a first end and a second end of an output port; the charging circuit further comprises a bleeder circuit, and the bleeder circuit provides a bleeder channel for the output capacitor.

Preferably, when the output port is not connected to a load, the switch control signal controls the corresponding power converter to reduce the output voltage across the output capacitor to a preset value.

Preferably, when a load is connected to the output port, the switch control signal controls the corresponding power converter to generate a stable output voltage.

Preferably, the bleed circuitry of the output capacitance multiplexes the power converter.

Preferably, the power converter is a BUCK circuit.

Preferably, the bleeder circuit comprises a first inductor, a first transistor and a first capacitor, wherein the first transistor and the first inductor are connected to a first end of the direct current source and a first end of the output port; the first capacitor is connected between the first end and the second end of the direct current source; the charges on the output capacitor sequentially flow through the first inductor, the first transistor and the first capacitor to form a bleeder circuit.

Preferably, the bleeder circuit comprises a first inductance and a second transistor, wherein the first inductance and the second transistor are connected in series between a first end and a second end of the output port; the charge on the output capacitor flows through the first inductor and the second transistor in sequence to form a bleeder circuit.

Preferably, the power converter further comprises a first transistor, a second transistor and a first inductor, wherein the first transistor and the first inductor are connected to a first end of the direct current source and a first end of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second end of the output port; the control end of the first transistor is connected with the control circuit and receives a first switch control signal; the control end of the second transistor is connected with the control circuit and receives a second switch control signal.

Preferably, when the output port is connected with a load, the first switch control signal and the second switch control signal have opposite phases and respectively control the first transistor and the second transistor to be alternately switched on and off.

Preferably, when the output port is not connected with a load, the first switch control signal controls the first transistor to be in a synchronous rectification or turn-off state, and the second switch control signal controls the second transistor to be in an alternate on and off state.

Preferably, when the output port is not connected with a load, the first transistor is controlled to be in an off state by the first switch control signal, and the second transistor is controlled to work in a constant current region by the second switch control signal.

Preferably, when the output port is not connected to a load, the first transistor is controlled to be in an off state by the first switch control signal, and the second transistor is controlled to be in an on state by the second switch control signal.

Preferably, the bleeder circuit comprises a first inductor, a first resistor and a third transistor, wherein the first inductor, the first resistor and the third transistor are connected in series between the first end and the second end of the output port; the charge on the output capacitor sequentially flows through the first inductor, the first resistor and the third transistor to form a bleeder circuit.

Preferably, the power converter further comprises a first transistor, a second transistor, and a first inductor, wherein the first transistor and the first inductor are connected to a first terminal of the dc source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second end of the output port; the first resistor and the third transistor are connected in series between a first node between the first transistor and the first inductor and a second end of the output port; the control end of the first transistor is connected with the control circuit and receives a first switch control signal; the control end of the second transistor is connected with the control circuit and receives a second switch control signal; the control end of the third transistor is connected with the control circuit and receives a third switch control signal.

Preferably, when the output port is connected to a load, the first switch control signal and the second switch control signal have opposite phases, and respectively control the first transistor and the second transistor to be alternately turned on and off, and the third switch control signal controls the third transistor to be turned off.

Preferably, when the output port is not connected to a load, the first transistor is controlled to be in an off state by the first switch control signal, the second transistor is controlled to be in an off state by the second switch control signal, and the third transistor is controlled to be in an on state by the third switch control signal.

Preferably, the bleeding circuit comprises a first inductor and a second resistor, wherein the first inductor and the second resistor are connected in series between the first end of the output port and the control circuit; the charges on the output capacitor sequentially flow through the first inductor and the second resistor to form a bleeder circuit.

Preferably, the power converter further comprises a first transistor, a second transistor, and a first inductor, wherein the first transistor and the first inductor are connected to a first terminal of the dc source and a first terminal of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second end of the output port; the second resistor is connected between a first node between the first transistor and the first inductor and the control end of the first transistor; the control end of the first transistor is connected with the control circuit and receives a first switch control signal; the control end of the second transistor is connected with the control circuit and receives a second switch control signal.

Preferably, when the output port is not connected with a load, the first transistor is controlled to be in an off state by the first switch control signal, and the second transistor is controlled to be in an off state by the second switch control signal.

Preferably, the power converter is a buck-boost circuit.

Preferably, the bleeder circuit comprises a sixth transistor, a second inductor, a fourth transistor and a first capacitor, wherein the fourth transistor, the second inductor and the sixth transistor are connected in series between the first end of the direct current source and the first end of the output port; the first capacitor is connected between the first end and the second end of the direct current source; the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor, the fourth transistor and the first capacitor to form a bleeder circuit.

Preferably, the bleeder circuit comprises a sixth transistor, a second inductor and a fifth transistor, wherein the fifth transistor, the second inductor and the sixth transistor are connected in series between the second end of the direct current source and the first end of the output port; and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor and the fifth transistor to form a bleeder circuit.

Preferably, the bleeder circuit comprises a sixth transistor and a seventh transistor, wherein the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port; and the charge on the output capacitor sequentially flows through the sixth transistor and the seventh transistor to form a bleeder circuit.

Preferably, the power converter further includes fourth to seventh transistors and a second inductor, wherein the fourth and fifth transistors are connected in series between the first and second terminals of the direct current source; the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port; a second inductor is connected between a second node between the fourth transistor and the fifth transistor and a third node between the sixth transistor and the seventh transistor; the output capacitor is connected between the first end and the second end of the output port; the control end of the fourth transistor is connected with the control circuit and receives a fourth switch control signal; the control end of the fifth transistor is connected with the control circuit and receives a fifth switch control signal; the control end of the sixth transistor is connected with the control circuit and receives a sixth switch control signal; and the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal.

Preferably, when the output port is connected with a load, the fourth switch control signal and the fifth switch control signal respectively control the fourth transistor and the fifth transistor to be alternately turned on, the sixth switch control signal controls the sixth transistor to be in a turned-on state, and the seventh switch control signal controls the seventh transistor to be in a turned-off state.

Preferably, when the output port is connected with a load, the fourth switch control signal controls the fourth transistor to be in a conducting state, the fifth switch control signal controls the fifth transistor to be in a turn-off state, and the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately conducted.

Preferably, when the output port is connected with a load, the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal respectively control the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor to be alternately turned on.

Preferably, when the output port is not connected with a load, the fourth switch control signal controls the fourth transistor to be in a synchronous rectification or turn-off state, the fifth switch control signal controls the fifth transistor to be alternately turned on and turned off, the sixth switch control signal controls the sixth transistor to be in a turn-on state, and the seventh switch control signal controls the seventh transistor to be in a turn-off state.

Preferably, when the output port is not connected with a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to operate in a constant current region, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to be in an off state, or to operate in a variable resistance region, or to operate in a constant current region, or to be in an on state.

Preferably, when the output port is not connected with a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state or to work in a variable resistance region or to work in a constant current region or to be in an on state, the sixth switch control signal controls the sixth transistor to work in a constant current region, and the seventh switch control signal controls the seventh transistor to work in the constant current region.

Preferably, when the output port is not connected with a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an on state, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an off state or to work in the variable resistance region.

Preferably, when the output port is not connected with a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state or to work in the variable resistance region, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an on state.

Preferably, when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an on state, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an on state.

Preferably, the bleeder circuit comprises a sixth transistor, a second inductor, a third resistor and an eighth transistor, wherein the sixth transistor, the second inductor, the third resistor and the eighth transistor are connected in series between the first end and the second end of the output port; and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor, the third resistor and the eighth transistor to form a bleeder circuit.

Preferably, the power converter further includes fourth to seventh transistors and a second inductor, wherein the fourth and fifth transistors are connected in series between the first and second terminals of the direct current source; the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port; a second inductor is connected between a second node between the fourth transistor and the fifth transistor and a third node between the sixth transistor and the seventh transistor; the third resistor and the eighth transistor are connected in series between a second node between the fourth transistor and the fifth transistor and a second end of the output port; the control end of the fourth transistor is connected with the control circuit and receives a fourth switch control signal; the control end of the fifth transistor is connected with the control circuit and receives a fifth switch control signal; the control end of the sixth transistor is connected with the control circuit and receives a sixth switch control signal; the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal; and the control end of the eighth transistor is connected with the control circuit and receives an eighth switch control signal.

Preferably, when the output port is connected to a load, the fourth switch control signal and the fifth switch control signal respectively control the fourth transistor and the fifth transistor to be alternately turned on, the sixth switch control signal controls the sixth transistor to be in a turned-on state, the seventh switch control signal controls the seventh transistor to be in a turned-off state, and the eighth switch control signal controls the eighth transistor to be in a turned-off state.

Preferably, when the output port is connected to a load, the fourth switch control signal controls the fourth transistor to be in a conducting state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately conducted, and the eighth switch control signal controls the eighth transistor to be in an off state.

Preferably, when the output port is connected with a load, the fourth control signal, the fifth control signal, the sixth control signal and the seventh control signal respectively control the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor to be alternately turned on, and the eighth switch control signal controls the eighth transistor to be in an off state.

Preferably, when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal controls the sixth transistor to be in an on state, the seventh switch control signal controls the seventh transistor to be in an off state, and the eighth switch control signal controls the eighth transistor to be in an on state.

Preferably, the bleeder circuit comprises a sixth transistor, a second inductor and a fourth resistor, wherein the sixth transistor, the second inductor and the fourth resistor are connected in series between the first end of the output port and the control circuit; and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor and the fourth resistor to form a bleeder circuit.

Preferably, the power converter further includes fourth to seventh transistors and a second inductor, wherein the fourth and fifth transistors are connected in series between the first and second terminals of the direct current source; the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port; a second inductor is connected between a second node between the fourth transistor and the fifth transistor and a third node between the sixth transistor and the seventh transistor; the fourth resistor is connected between the second node and the control circuit; the control end of the fourth transistor is connected with the control circuit and receives a fourth switch control signal; the control end of the fifth transistor is connected with the control circuit and receives a fifth switch control signal; the control end of the sixth transistor is connected with the control circuit and receives a sixth switch control signal; and the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal.

Preferably, when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an off state.

Preferably, the bleeder circuit is connected in parallel with the output capacitor.

Preferably, the bleeder circuit comprises a second resistor and a third transistor, and the second resistor and the third transistor are connected in series between a first end and a second end of the output port; the charge on the output capacitor sequentially flows through the second resistor and the third transistor to form a bleeder circuit.

Preferably, the power converter further comprises a first transistor, a second transistor, a first inductor; the first transistor and the first inductor are connected to a first end of the direct current source and a first end of the output port; the second transistor is connected between a first node between the first transistor and the first inductor and a second end of the output port; the first resistor and the third transistor are connected in series between two ends of the output capacitor; the control end of the first transistor is connected with the control circuit and receives a first switch control signal; the control end of the second transistor is connected with the control circuit and receives a second switch control signal; the control end of the third transistor is connected with the control circuit and receives a third switch control signal.

Preferably, the bleeder circuit comprises a third resistor and an eighth transistor, and the charge on the output capacitor sequentially flows through the third resistor and the eighth transistor to form a bleeder circuit.

Preferably, the power converter further includes fourth to eighth transistors and a second inductor, wherein the fourth and fifth transistors are connected in series between the first and second terminals of the direct current source; the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port; a second inductor is connected between a second node between the fourth transistor and the fifth transistor and a third node between the sixth transistor and the seventh transistor; the third resistor and the eighth transistor are connected between two ends of the output capacitor in series; the control end of the fourth transistor is connected with the control circuit and receives a fourth switch control signal; the control end of the fifth transistor is connected with the control circuit and receives a fifth switch control signal; the control end of the sixth transistor is connected with the control circuit and receives a sixth switch control signal; the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal; and the control end of the eighth transistor is connected with the control circuit and receives an eighth switch control signal.

Preferably, when the output port is not connected to the load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal controls the sixth transistor to be in an on state, the seventh switch control signal controls the seventh transistor to be in an off state, and the eighth switch control signal controls the eighth transistor to be in an on state.

According to the charging circuit provided by the embodiment of the invention, under the conditions of using simpler devices and low cost, the bleeder circuit multiplexes the power converter or independently provides a bleeder channel for the output capacitor, stable output voltage is output when the output port is connected with a load, and the output voltage is reduced to a preset value when the output port is not connected with the load, so that the same effect as that of a traditional quick charging circuit (namely the combination of a DC-DC circuit and a load switch) is achieved. Circuit components are reduced, and circuit loss is reduced, so that conversion efficiency is improved; meanwhile, the volume is reduced, and the cost is reduced.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic block diagram of a charging circuit in the prior art.

Fig. 2 shows a schematic block diagram of a charging circuit according to a first embodiment of the present invention.

Fig. 3 shows a schematic block diagram of a control circuit in a charging circuit according to a first embodiment of the present invention.

Fig. 4 illustrates an exemplary operating waveform diagram of the charging circuit shown in fig. 2.

Fig. 5 shows a schematic block diagram of a charging circuit according to a second embodiment of the present invention.

Fig. 6 shows a schematic block diagram of a control circuit in a charging circuit according to a second embodiment of the present invention.

Fig. 7 shows a schematic block diagram of a charging circuit according to a third embodiment of the present invention.

Fig. 8 shows a schematic block diagram of a charging circuit according to a fourth embodiment of the present invention.

Fig. 9 shows a schematic block diagram of a control circuit in a charging circuit according to a fourth embodiment of the present invention.

Fig. 10 shows a schematic block diagram of a charging circuit according to a fifth embodiment of the present invention.

Fig. 11 shows a schematic block diagram of a control circuit in a charging circuit according to a fifth embodiment of the present invention.

Fig. 12 shows a schematic block diagram of a charging circuit according to a sixth embodiment of the present invention.

Fig. 13 shows a schematic block diagram of a control circuit in a charging circuit according to a sixth embodiment of the present invention.

Fig. 14 shows a schematic block diagram of a charging circuit according to a seventh embodiment of the present invention.

Fig. 15 shows a schematic block diagram of a charging circuit according to an eighth embodiment of the present invention.

Fig. 16 shows a schematic block diagram of a control circuit in a charging circuit according to an eighth embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The charging circuit provided by the embodiment of the invention comprises a direct current source, at least one power converter and a control circuit to support the quick charging of at least one output port (such as a USB port). Each power converter is a DC-DC conversion circuit, and the control circuit controls the power converters to charge the loads when the loads are connected and reduce the output voltage of the power converters to a preset value when the loads are not connected. In the embodiment of the invention, the USB port can be type-A, type-C and the like, and the power converter can be boost, buck-boost circuit and the like.

In the following embodiments, a one-way charging circuit will be described as an example (see fig. 2, fig. 5, fig. 7, fig. 8, fig. 10, fig. 12, fig. 14, and fig. 15 in particular). In some other embodiments, the charging circuit comprises at least a two-way charging circuit.

Fig. 2 shows a schematic block diagram of a charging circuit according to a first embodiment of the present invention. As shown in fig. 2, the charging circuit 20 includes a dc source 21, a power converter 22, a control circuit 23, an output port 24, and a bleeding circuit.

Wherein the direct current source 21 provides a direct current supply voltage DC. In the present embodiment, the DC source 21 includes a DC source unit 21a and a first capacitor C1, the DC source unit 21a converts an ac input voltage into a DC supply voltage DC, and the first capacitor C1 filters the DC supply voltage DC output by the DC source unit 21 a. The DC supply voltage DC is, for example, 5V, but is not limited thereto.

The power converter 22 is connected to the DC source 21 and converts the DC supply voltage DC into an output voltage Vo. The power converter includes an output capacitor Cout connected between a first terminal and a second terminal of the output port 24. In this embodiment, the power converter is a buck circuit.

The control circuit 23 is connected to the Load and the power converter 22, and generates a switching control signal of the power converter 22 according to the state signal VL of the Load and the output voltage Vo to regulate the output voltage Vo. The status signal VL of the Load represents whether the Load is connected to the output port 24. When the output port 24 is connected to a Load, the switch control signal controls the corresponding power converter 22 to generate a stable output voltage Vo.

The bleeder circuit provides a bleeder path for the output capacitor Cout. When the output port 24 is not connected to a load, the output capacitor Cout reduces the output voltage Vo to a preset value through the bleeder circuit.

According to the charging circuit provided by the embodiment of the invention, under the conditions of using simpler devices and low cost, the bleeder circuit multiplexing power converter provides a bleeder channel for the output capacitor, outputs stable output voltage when the output port is connected with a load, and reduces the output voltage to a preset value when the output port is not connected with the load, so that the same effect as that of a traditional quick charging circuit (namely the combination of a DC-DC conversion circuit and a load switch) is achieved. Circuit components are reduced, and loss is reduced, so that conversion efficiency is improved; meanwhile, the volume is reduced, and the cost is reduced.

It should be understood that various power converters and control circuits that achieve a rapid decrease in output voltage to a preset value are suitable for use in the present embodiment and are not limited to the power converters and control circuits described in the specification.

As shown in fig. 2, the power converter 22 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout. The first transistor Q1 and the first inductor L are connected in series between the first end of the dc source 21 and the first end of the output port 24, and the output capacitor Cout is connected between the first end and the second end of the output port 24; the second transistor Q2 is connected between a first node a between the first transistor Q1 and the first inductor L1 and the second end of the output port 24. A control terminal of the first transistor Q1 and a control terminal of the second transistor Q2 are connected to the control circuit 23, respectively. The switch control signals include a first switch control signal Vg1 and a second switch control signal Vg 2. Specifically, the control end of the first transistor Q1 is connected to the control circuit 23, and receives a first switch control signal Vg 1; the control terminal of the second transistor Q2 is connected to the control circuit 23 and receives a second switch control signal Vg 2.

The output port 24 is connected to the power converter 22, and the output port 24 charges the Load when the Load is connected thereto, and discharges the output voltage Vo to a predetermined value when the Load is not connected thereto. When the Load is not connected, the bleeder circuit multiplexes the power converter 22 to provide a bleeder channel for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

The bleeder circuit comprises a first inductor L1, a first transistor Q1 and a first capacitor C1, wherein the first capacitor C1 is connected between the first terminal and the second terminal of the direct current source 21; the charge on the output capacitor Cout sequentially flows through the first inductor L1, the first transistor Q1 and the first capacitor C1 to form a bleeding loop.

Or, the bleeder circuit includes a first inductor L1 and a second transistor Q2, and the charges on the output capacitor Cout sequentially flow through the first inductor L1 and the second transistor Q2 to form a bleeder circuit.

When the output port 24 is not connected with a load, the first switch control signal Vg1 controls the first transistor Q1 to be in a synchronous rectification or turn-off state, the second switch control signal Vg2 controls the second transistor Q2 to be alternately turned on and off, so that the power converter 22 is disconnected from the direct current source 21, and when the second transistor Q2 is turned on, the charges on the output capacitor Cout sequentially flow through the first inductor L1 and the second transistor Q2 to form a bleeder circuit, so that the output voltage Vo is reduced to a preset value; when the second transistor Q2 is turned off, the charges on the output capacitor Cout sequentially flow through the first inductor L1, the first transistor Q1 and the first capacitor C1 to form a bleeding loop. When the first transistor Q1 is off, the first transistor Q1 freewheels in reverse through its body diode.

In a preferred embodiment, when the output port 24 is not connected to a load, the first switch control signal Vg1 controls the first transistor Q1 to be in an off state, so that the power converter 22 is disconnected from the dc source 21, the second switch control signal Vg2 controls the second transistor Q2 to operate in a constant current region, and charges on the output capacitor Cout sequentially flow through the first inductor L1 and the second transistor Q2 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

In a preferred embodiment, when the output port 24 is not connected to a load, the first switch control signal Vg1 controls the first transistor Q1 to be in an off state, so that the power converter 22 is disconnected from the dc source 21, the second switch control signal Vg2 controls the second transistor Q2 to be in an on state, and charges on the output capacitor Cout sequentially flow through the first inductor L1 and the second transistor Q2 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

Fig. 4 illustrates an exemplary operation waveform diagram of the charging circuit shown in fig. 1. As shown in fig. 4, at time t0, the Load is removed, the output port 24 is not connected with the Load at this time, the state signal VL of the Load changes from high level to low level, the first switch control signal Vg1 changes from high level to low level, the first transistor Q1 is turned off, and during the period t0-t3, the state signal VL of the Load maintains low level, the first switch control signal Vg1 maintains low level, and the first transistor Q1 is always turned off. At time t0, the second switch control signal Vg2 changes from low to high, the second transistor Q2 is turned on, the output capacitor Cout is discharged through the second transistor Q2, and the current IQ2 of the second transistor Q2 rises in the reverse direction. At time t1, the second switch control signal Vg2 changes from high level to low level, the second transistor Q2 is turned off, the current IQ2 of the second transistor Q2 decreases to 0, and at this time, the charge on the output capacitor Cout charges the first capacitor C1 through the first inductor L1 and the first transistor Q1, and the first transistor Q1 freewheels through a body diode. At time t2, the second switch control signal Vg2 changes from low to high, and the second transistor Q2 is turned on again. During the period from t2 to t3, the second transistor Q2 is turned on and off periodically until the discharge of the output capacitor Cout is completed. At time t3, it is detected that the Load is connected to the output port 24, the state signal VL of the Load changes from low level to high level, the second switch control signal Vg2 changes from high level to low level, the second transistor Q2 is turned off, the first switch control signal Vg1 changes from low level to high level, the first transistor Q1 is turned on, the current IQ1 of the first transistor Q1 rises, and the energy of the dc source 21 is transmitted to the Load via the first transistor Q1 and the first inductor L1. At time t4, the first switch control signal Vg1 changes from high level to low level, the second switch control signal Vg2 changes from low level to high level, the first transistor Q1 turns off, the second transistor Q2 turns on, the current IQ1 of the first transistor Q1 decreases to 0, and the current of the first inductor L1 freewheels via the Load and the second transistor Q2. At time t5, the first switch control signal Vg1 changes to the high level again, the second switch control signal Vg2 changes to the low level, the first transistor Q1 is turned on, and the second transistor Q2 is turned off. During the period t3-t6, the first transistor Q1 and the second transistor Q2 are alternately turned on. At time t6, the Load is removed, the output port 24 is not connected to the Load at this time, the state signal VL of the Load changes from high level to low level, the first switch control signal Vg1 changes from high level to low level, and the second switch control signal Vg2 changes from low level to high level.

Fig. 3 shows a schematic block diagram of a control circuit in a charging circuit according to a first embodiment of the present invention. As shown in fig. 3, the control circuit 23 includes an operational amplifier 231, a sawtooth wave generating module 232, a comparator 233, a first logic module 234, a PWM generating module 235, a second logic module 236, a third logic module 237, and a fourth logic module 238.

The operational amplifier 231 is connected to the output port 24 to obtain a sampling signal of the output voltage Vo, and the sampling signal of the output voltage Vo is compared with a reference voltage Vref to obtain an error signal Vcomp; the sawtooth wave generation module 232 provides a sawtooth wave signal; the comparator 233 is connected to the operational amplifier 231 and the sawtooth wave generation module 232, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the first logic module 234 is connected to the Load and the comparator 233, and generates a first switch control signal Vg1 according to the state signal VL of the Load and the first PWM control signal PWM 1. The PWM generation module 235 provides a second PWM control signal PWM 2; the second logic module 236 is connected to the Load, and generates a first logic signal according to the state signal VL of the Load; the third logic block 237 is connected to the second logic block 236 and the PWM generating block 235, and generates a second logic signal according to the first logic signal and a second PWM control signal PWM 2; the fourth logic block 238 is connected to the first logic block 234 and the third logic block 237, and generates a second switch control signal Vg2 according to the first switch control signal Vg1 and the second logic signal.

In this embodiment, the first logic block 234 is an and gate, the second logic block 236 is an not gate, the third logic block 237 is an and gate, and the fourth logic block 238 is a nor gate.

When the output port 24 is connected to a Load, the first switch control signal Vg1 and the second switch control signal Vg2 have opposite phases and respectively control the first transistor Q1 and the second transistor Q2 to be alternately turned on and off, so as to maintain the stability of the output voltage Vo, i.e., the power converter 22 generates a stable output voltage Vo to charge the Load.

Fig. 5 shows a schematic block diagram of a charging circuit according to a second embodiment of the present invention. The charging circuit 30 includes a dc source 31, a power converter 32, a control circuit 33, an output port 34, and a bleeding circuit.

Compared with the charging circuit of the first embodiment, the charging circuit 30 according to the second embodiment is mainly different in that the bleeder circuit includes a first inductor L1, a first resistor R1 and a third transistor Q3, and the charge on the output capacitor Cout sequentially flows through the first inductor L1, the first resistor R1 and the third transistor Q3 to form a bleeder circuit. The power converter 32 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout, wherein the first transistor Q1 and the first inductor L are connected in series between a first terminal of the dc source 31 and a first terminal of the output port 34, and the output capacitor Cout is connected between the first terminal and a second terminal of the output port 34; the second transistor Q2 is connected between a first node a between the first transistor Q1 and the first inductor L1 and the second end of the output port 34; the first resistor R1 and the third transistor Q3 are connected in series between the first node a and the second end of the output port 34. The control terminal of the first transistor Q1, the control terminal of the second transistor Q2, and the control terminal of the third transistor Q3 are connected to the control circuit 33, respectively.

The switch control signals include a first switch control signal Vg1, a second switch control signal Vg2, and a third switch control signal Vg 3. Specifically, the control end of the first transistor Q1 is connected to the control circuit 33, and receives a first switch control signal Vg 1; the control terminal of the second transistor Q2 is connected to the control circuit 33 and receives a second switch control signal Vg2, and the control terminal of the third transistor Q3 is connected to the control circuit 33 and receives a second switch control signal Vg 3.

The output port 34 is connected to the power converter 32, and the output port 34 charges the Load when the Load is connected thereto, and discharges to reduce the output voltage Vo to a preset value when the Load is not connected thereto. When the Load is not connected, the bleeder circuit multiplexes the power converter 32 to provide a bleed channel for the output capacitor Cout, thereby discharging the charge on the output capacitor Cout.

When the Load is connected to the output port 34, the first switch control signal Vg1 and the second switch control signal Vg2 have opposite phases and respectively control the first transistor Q1 and the second transistor Q2 to be alternately turned on and off, and the third switch control signal Vg3 controls the third transistor Q3 to be in an off state, so as to maintain the stability of the output voltage Vo, that is, the power converter 32 generates a stable output voltage Vo to charge the Load.

Specifically, when the output port 34 is connected with a Load, the first transistor Q1 is turned on, the second transistor Q2 and the third transistor Q3 are turned off, the current of the power converter 32 flows through the first transistor Q1, the first inductor L1 and the Load via the first end of the dc source 31, and finally flows to the ground, when the second transistor Q2 is turned on, the first transistor Q1 and the third transistor Q3 are turned off, the current in the first inductor L1 cannot suddenly change, the current in the first inductor L1 flows through the Load and the second transistor Q2, and then returns to the first inductor L1, thereby forming a free-wheeling loop.

When the Load is removed from the output port 34, the first transistor Q1 and the second transistor Q2 are turned off to cut off the pre-stage voltage, and simultaneously, the third transistor Q3 is turned on, so that the charges on the output capacitor Cout sequentially flow through the first inductor L1, the first resistor R1 and the third transistor Q3 to form a bleeding loop, so that the output voltage Vo is decreased to a preset value.

Specifically, when the output port 34 is not connected to the Load, the first switch control signal Vg1 controls the first transistor Q1 to be in an off state, the second switch control signal Vg2 controls the second transistor Q2 to be in an off state, so that the power converter 32 is disconnected from the dc source 31, the third switch control signal Vg3 controls the third transistor Q3 to be in an on state, and charges on the output capacitor Cout sequentially flow through the first inductor L1, the first resistor R1 and the third transistor Q3 to form a bleeding loop, so as to reduce the output voltage Vo to a preset value.

Fig. 6 shows a schematic block diagram of a control circuit in a charging circuit according to a second embodiment of the present invention. As shown in fig. 6, the control circuit 33 includes an operational amplifier 331, a sawtooth wave generating module 332, a comparator 333, a first logic module 334, a fifth logic module 335, a sixth logic module 336, and a seventh logic module 337.

The operational amplifier 331 is connected to the output port 34 to obtain a sampling signal of the output voltage Vo, and the sampling signal of the output voltage Vo is compared with a reference voltage Vref to obtain an error signal Vcomp; the sawtooth wave generation module 332 provides a sawtooth wave signal; the comparator 333 is connected to the operational amplifier 331 and the sawtooth wave generating module 332, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the first logic module 334 is connected to the Load and the comparator 333, and generates a first switch control signal Vg1 according to the state signal VL of the Load and the first PWM control signal PWM 1. The fifth logic module 335 is connected to the first logic module 334, and generates a fifth logic signal according to the first switch control signal Vg 1; the sixth logic 336 is connected to the fifth logic 335 and the Load, and generates a second switch control signal Vg2 according to the fifth logic signal and the state signal VL of the Load. The seventh logic block 337 is connected to the Load, and generates a third switch control signal Vg3 according to the state signal VL of the Load.

In this embodiment, the first logic module 334 is an and gate, the fifth logic module 335 is an not gate, the sixth logic module 336 is an and gate, and the seventh logic module 337 is an not gate.

The rest of the charging circuit 30 according to the second embodiment is the same as the first embodiment and therefore will not be described in detail.

Fig. 7 shows a schematic block diagram of a charging circuit according to a third embodiment of the present invention. The charging circuit 40 includes a dc source 41, a power converter 42, a control circuit 43, an output port 44, and a bleed circuit.

Compared to the charging circuit of the second embodiment, the charging circuit 40 according to the third embodiment mainly differs in that the bleeder circuit is connected in parallel with the output capacitor, and the bleeder circuit includes a first resistor R1 and a third transistor Q3, the first resistor R1 and the third transistor Q3 being connected in series across the output capacitor Cout. When the Load is not connected, the bleeder circuit is connected in parallel with the output capacitor to provide a bleeder channel for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

When the Load is removed from the output port 44, the first transistor Q1 and the second transistor Q2 are turned off to cut off the pre-stage voltage, and simultaneously, the third transistor Q3 is turned on, so that the charges on the output capacitor Cout sequentially flow through the first resistor R1 and the third transistor Q3 to form a bleeding loop, and the output voltage Vo is lowered to a preset value.

Specifically, when the output port 44 is not connected to the Load, the first switch control signal Vg1 controls the first transistor Q1 to be in an off state, the second switch control signal Vg2 controls the second transistor Q2 to be in an off state, so that the power converter 42 is disconnected from the dc source 41, the third switch control signal Vg3 controls the third transistor Q3 to be in an on state, and the charges on the output capacitor Cout sequentially flow through the first resistor R1 and the third transistor Q3 to form a bleeding loop, so as to reduce the output voltage Vo to a preset value.

The rest of the charging circuit 40 according to the third embodiment is the same as the second embodiment, and thus, will not be described in detail.

Fig. 8 shows a schematic block diagram of a charging circuit according to a fourth embodiment of the present invention. The charging circuit 50 includes a dc source 51, a power converter 52, a control circuit 53, an output port 54, and a bleed circuit.

Compared with the charging circuit of the first embodiment, the charging circuit 50 according to the fourth embodiment mainly differs in that the bleeder circuit includes a first inductor L1 and a second resistor R2, and the charge on the output capacitor Cout sequentially flows through the first inductor L1 and the second resistor R2 to form a bleeder circuit. The power converter 52 includes a first transistor Q1, a second transistor Q2, a first inductor L1, and an output capacitor Cout.

The first transistor Q1 and the first inductor L are connected in series between the first end of the dc source 51 and the first end of the output port 54, and the output capacitor Cout is connected between the first end and the second end of the output port 54; the second transistor Q2 is connected between a first node a between the first transistor Q1 and the first inductor L1 and the second end of the output port 54; the second resistor R2 is connected between the first node a and the control terminal of the first transistor Q1. A control terminal of the first transistor Q1 and a control terminal of the second transistor Q2 are connected to the control circuit 53, respectively.

The switch control signals include a first switch control signal Vg1 and a second switch control signal Vg 2. Specifically, the control end of the first transistor Q1 is connected to the control circuit 53, and receives a first switch control signal Vg 1; the control terminal of the second transistor Q2 is connected to the control circuit 53 and receives a second switch control signal Vg 2.

The output port 54 is connected to the power converter 52, and the output port 54 charges the Load when the Load is connected thereto, and discharges the output voltage Vo to a predetermined value when the Load is not connected thereto. When no Load is connected, the bleeding circuit multiplexes the power converter 52 to provide a bleed channel for the output capacitor Cout, thereby discharging the charge on the output capacitor Cout.

When the Load is connected to the output port 54, the phases of the first switch control signal Vg1 and the second switch control signal Vg2 are opposite, and the first transistor Q1 and the second transistor Q2 are controlled to be alternately turned on and off, respectively, so as to maintain the stability of the output voltage Vo, that is, the power converter 52 generates a stable output voltage Vo to charge the Load. Specifically, when the output port 54 is connected with a Load, the first transistor Q1 is turned on, the second transistor Q2 is turned off, the current flows through the first transistor Q1, the first inductor L1 and the Load via the first end of the dc source 51, and finally flows to the ground, so as to form a power supply loop, when the second transistor Q2 is turned on, the first transistor Q1 is turned off, the current in the first inductor L1 cannot change suddenly, and the current in the first inductor L1 flows through the Load and the second transistor Q2, and then returns to the first inductor L1, so as to form a free-wheeling loop.

When the output port 54 is not connected to a load, the first switch control signal Vg1 controls the first transistor Q1 to be in an off state, and the second switch control signal Vg2 controls the second transistor Q2 to be in an off state, so that the power converter 52 is disconnected from the dc source 51, and the output voltage Vo of the power converter 52 is reduced to a preset value. Specifically, when the Load is removed from the output port 54, the first transistor Q1 and the second transistor Q2 are turned off to cut off the pre-stage voltage, and the charges on the output capacitor Cout sequentially flow through the first inductor L1 and the second resistor R2 to form a bleeding loop, so that the output voltage Vo drops to the preset value.

Fig. 9 shows a schematic block diagram of a control circuit in a charging circuit according to a fourth embodiment of the present invention. As shown in FIG. 9, the control circuit 43 includes an operational amplifier 531, a sawtooth wave generation module 532, a comparator 533, a first logic block 534, a fifth logic block 535, and a sixth logic block 536.

The operational amplifier 531 is connected to the output port 54 to obtain a sampling signal of the output voltage Vo, and the sampling signal of the output voltage Vo is compared with a reference voltage Vref to obtain an error signal Vcomp; the sawtooth wave generation module 532 provides a sawtooth wave signal; the comparator 533 is connected to the operational amplifier 531 and the sawtooth wave generating module 532, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the first logic block 534 is connected to the Load and the comparator 533, and generates a first switch control signal Vg1 according to the state signal VL of the Load and the first PWM control signal PWM 1. The fifth logic block 535 is connected to the first logic block 534, and generates a fifth logic signal according to the first switch control signal Vg 1; the sixth logic block 536 is connected to the fifth logic block 535 and the Load, and generates a second switch control signal Vg2 according to the fifth logic signal and the state signal VL of the Load.

In this embodiment, the first logic block 534 is an and gate, the fifth logic block 535 is an not gate, and the sixth logic block 536 is an and gate.

The rest of the charging circuit 50 according to the fourth embodiment is the same as the first embodiment, and therefore, will not be described in detail.

Fig. 10 shows a schematic block diagram of a charging circuit according to a fifth embodiment of the present invention. The charging circuit 60 includes a dc source 61, a power converter 62, a control circuit 63, an output port 64, and a bleed circuit.

Compared to the charging circuit of the first embodiment, the charging circuit 60 according to the fifth embodiment is mainly different in that the bleeder circuit comprises a sixth transistor Q6, a second inductor L2, a fourth transistor Q4 and a first capacitor C1; the charges on the output capacitor Cout sequentially flow through the sixth transistor Q6, the second inductor L2, the fourth transistor Q4 and the first capacitor C1 to form a bleeding loop. Or, the bleeder circuit includes a sixth transistor Q6, a second inductor L2, and a fifth transistor Q5, and the charges on the output capacitor Cout sequentially flow through the sixth transistor Q6, the second inductor L2, and the fifth transistor Q5 to form a bleeder circuit. Or, the bleeder circuit comprises a sixth transistor Q6 and a seventh transistor Q7, and the charges on the output capacitor Cout sequentially flow through the sixth transistor Q6 and the seventh transistor Q7 to form a bleeder circuit. The power converter 62 includes fourth to seventh transistors (Q4-Q7), a second inductor L2, and an output capacitor Cout. In this embodiment, the power converter is a buck-boost circuit.

Wherein the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first terminal and the second terminal of the direct current source 61; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first terminal and the second terminal of the output port 64; a second inductor L2 is connected between a second node B between the fourth transistor Q4 and the fifth transistor Q5 and a third node C between the sixth transistor Q6 and the seventh transistor Q7; the output capacitor Cout is connected between the first terminal and the second terminal of the output port 64. A control terminal of the fourth transistor Q4, a control terminal of the fifth transistor Q5, a control terminal of the sixth transistor Q6, and a control terminal of the seventh transistor Q7 are connected to the control circuit 63, respectively.

The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, and a seventh switch control signal Vg 7. The control end of the fourth transistor Q4 is connected with the control circuit 63, and receives a fourth switch control signal Vg 4; the control end of the fifth transistor Q5 is connected to the control circuit 63 and receives a fifth switch control signal Vg 5; the control end of the sixth transistor Q6 is connected to the control circuit 63, and receives a sixth switch control signal Vg 6; the control terminal of the seventh transistor Q7 is connected to the control circuit 63 and receives a seventh switch control signal Vg 7.

The output port 64 is connected to the power converter 62, and the output port 64 charges a Load when the Load is connected to the output port 64, and specifically, when the Load is connected to the output port 64, the fourth to seventh transistors (Q4-Q7) cause the power converter 62 to operate in a buck mode, a boost mode, and a buck-boost mode under the control of the control circuit 63. Specifically, when the power converter 62 operates in the buck mode, the fourth switch control signal Vg4 and the fifth switch control signal Vg5 control the fourth transistor Q4 and the fifth transistor Q5 to be alternately turned on, respectively, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in a turned-on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in a turned-off state. When the power converter 62 operates in the boost mode, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in a conducting state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in a turn-off state, and the sixth switch control signal Vg6 and the seventh switch control signal Vg7 respectively control the sixth transistor Q6 and the seventh transistor Q7 to be alternately conducted. When the power converter 62 works in the buck-boost mode, the fourth control signal Vg4, the fifth control signal Vg5, the sixth control signal Vg6 and the seventh control signal Vg7 respectively control the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 to be alternately turned on.

Discharging when the Load is not connected reduces the output voltage Vo to a preset value. When no Load is connected, the bleeding circuit multiplexes power converter 62 to provide a bleed path for output capacitor Cout, thereby discharging the charge on output capacitor Cout.

Specifically, when the output port 64 is not connected with a Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in a synchronous rectification or off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be alternately turned on and off, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state. When the fifth transistor Q5 is turned on, the charges on the output capacitor Cout sequentially flow through the sixth transistor Q6, the second inductor L2 and the fifth transistor Q5 to form a bleeding loop; when the fifth transistor Q5 is turned off, the charges on the output capacitor Cout sequentially flow through the sixth transistor Q6, the second inductor L2, the fourth transistor Q4 and the first capacitor C1 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value. When the fourth transistor Q4 is turned off, the fourth transistor Q4 freewheels in reverse through its body diode.

In a preferred embodiment, when the output port 64 is not connected with a Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to operate in a constant current region, and the fifth switch control signal Vg5 controls the fifth transistor Q5 to operate in the constant current region; the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state or to operate in a variable resistance region or to operate in a constant current region or to be in an on state. The charge on the output capacitor Cout sequentially flows through the sixth transistor Q6, the second inductor L2 and the fifth transistor Q5 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

In a preferred embodiment, when the output port 64 is not connected to a Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to operate in a constant current region, the fifth switch control signal Vg5 controls the fifth transistor Q5 to operate in an off state, a variable resistance region, a constant current region or an on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to operate in the constant current region. The charge on the output capacitor Cout sequentially flows through the sixth transistor Q6 and the seventh transistor Q7 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

In a preferred embodiment, when the output port 64 is not connected to a Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an on state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in an on state, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state or to operate in a variable resistance region. The charge on the output capacitor Cout sequentially flows through the sixth transistor Q6, the second inductor L2 and the fifth transistor Q5 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

In a preferred embodiment, when the output port 64 is not connected to a Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an on state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in an on state or an off state or to be operated in a variable resistance region, and the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an on state. The charge on the output capacitor Cout sequentially flows through the sixth transistor Q6 and the seventh transistor Q7 to form a bleeding loop, so that the output voltage Vo is reduced to a preset value.

Fig. 11 shows a schematic block diagram of a control circuit in a charging circuit according to a fifth embodiment of the present invention. As shown in FIG. 11, the control circuit 63 includes an operational amplifier 631, a sawtooth wave generation module 632, a comparator 633, a first logic module 634, a PWM generation module 635, a second logic module 636, a third logic module 637, a fourth logic module 638, and a seventh logic module 639.

Wherein, the operational amplifier 631 is connected to the output port 64 to obtain a sampling signal of the output voltage Vo, and the sampling signal of the output voltage Vo is compared with a reference voltage Vref to generate an error signal Vcomp; the sawtooth wave generation module 632 provides a sawtooth wave signal; the comparator 633 is connected to the operational amplifier 631 and the sawtooth wave generation module 632, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the seventh logic module 639 is connected to the Load, and generates a fifth switch control signal Vg5 according to the state signal VL of the Load. The first logic block 634 is connected to the Load and the comparator 633, and generates a seventh switch control signal Vg7 according to the state signal VL of the Load and the first PWM control signal PWM 1. The PWM generation module 635 provides a second PWM control signal PWM 2; the second logic block 636 is connected to the Load, and generates a first logic signal according to the state signal VL of the Load; the third logic block 637 is connected to the second logic block 636 and the PWM generation block 635 to generate a second logic signal PWM2 according to the first and second logic signals; the fourth logic block 638 is connected to the first logic block 634 and the third logic block 637, and generates a sixth switch control signal Vg6 according to the first switch control signal Vg1 and the second logic signal. The fourth switch control signal Vg4 is consistent with the state signal VL of the Load.

In this embodiment, the first logic block 634 is an and gate, the second logic block 636 is an not gate, the third logic block 637 is an and gate, the fourth logic block 638 is a nor gate, and the seventh logic block 639 is an not gate.

The rest of the charging circuit 60 according to the fifth embodiment is the same as the first embodiment, and thus, will not be described in detail.

Fig. 12 shows a schematic block diagram of a charging circuit according to a sixth embodiment of the present invention. The charging circuit 70 includes a dc source 71, a power converter 72, a control circuit 73, an output port 74, and a bleed circuit.

Compared to the charging circuit of the fifth embodiment, the charging circuit 70 according to the fifth embodiment is mainly different in that the bleeder circuit comprises a sixth transistor Q6, a second inductor L2, a third resistor R3 and an eighth transistor Q8, wherein the sixth transistor Q6, the second inductor L2, the third resistor R3 and the eighth transistor Q8 are connected in series between the first end and the second end of the output port; the charge on the output capacitor sequentially flows through the sixth transistor Q6, the second inductor L2, the third resistor R3 and the eighth transistor Q8 to form a bleeder circuit. The power converter 72 includes fourth to seventh transistors (Q4-Q7), a second inductor L2, and an output capacitor Cout.

Wherein the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first terminal and the second terminal of the direct current source 71; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first terminal and the second terminal of the output port 74; a second inductor L2 is connected between a second node B between the fourth transistor Q4 and the fifth transistor Q5 and a third node C between the sixth transistor Q6 and the seventh transistor Q7; the output capacitor Cout is connected between a first terminal and a second terminal of the output port 74. The third resistor R3 and the eighth transistor Q8 are connected in series between the second node B and the second terminal of the output port 74. A control terminal of the fourth transistor Q4, a control terminal of the fifth transistor Q5, a control terminal of the sixth transistor Q6, a control terminal of the seventh transistor Q7, and a control terminal of the eighth transistor Q8 are connected to the control circuit 73, respectively.

The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, a seventh switch control signal Vg7, and an eighth switch control signal Vg 8. The control end of the fourth transistor Q4 is connected to the control circuit 73, and receives a fourth switch control signal Vg 4; the control end of the fifth transistor Q5 is connected to the control circuit 73 and receives a fifth switch control signal Vg 5; the control end of the sixth transistor Q6 is connected to the control circuit 73, and receives a sixth switch control signal Vg 6; a control end of the seventh transistor Q7 is connected to the control circuit 73, and receives a seventh switch control signal Vg 7; the control terminal of the eighth transistor Q8 is connected to the control circuit 73 and receives an eighth switch control signal Vg 8.

The output port 74 is connected to the power converter 72, and the output port 74 charges the Load when the Load is connected thereto, and discharges the output voltage Vo to a preset value when the Load is not connected thereto. Specifically, when no Load is connected, the bleeding circuit multiplexes the power converter 72 to provide a bleed path for the output capacitor Cout, thereby discharging the charge on the output capacitor Cout.

When the Load is connected to the output port 74, the operation states of the four transistors Q4-Q7 of the power converter 72 are the same as those of the fifth embodiment, and thus the description thereof is omitted. The eighth transistor Q8 is in an off state under the control of the control circuit 73.

When the Load is removed from the output port 74, under the control of the control circuit 73, the fourth transistor Q4, the fifth transistor Q5 and the seventh transistor Q7 are turned off, the sixth transistor Q6 and the eighth transistor Q8 are turned on, and the output capacitor Cout, the sixth transistor Q6, the third resistor R3 and the eighth transistor Q8 form a bleeding loop to release the charge on the output capacitor Cout, so that the output voltage Vo drops to the preset value.

Specifically, when the output port 74 is not connected to the Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an on state, the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state, and the eighth switch control signal Vg8 controls the eighth transistor Q8 to be in an on state.

Fig. 13 shows a schematic block diagram of a control circuit in a charging circuit according to a sixth embodiment of the present invention. As shown in fig. 13, the control circuit 73 includes an operational amplifier 731, a sawtooth wave generating module 732, a comparator 733, a first logic module 734, a fifth logic module 735, a sixth logic module 736, a seventh logic module 737, and a low level generating module 738.

Wherein, the operational amplifier 731 is connected to the output port 74 to obtain a sampling signal of the output voltage Vo, and comparing the sampling signal of the output voltage Vo with a reference voltage Vref generates an error signal Vcomp; the sawtooth wave generation module 732 provides a sawtooth wave signal; the comparator 733 is connected to the operational amplifier 731 and the sawtooth wave generation module 732, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the first logic 734 is connected to the Load and the comparator 733, and generates a seventh switch control signal Vg7 according to the state signal VL of the Load and the first PWM control signal PWM 1. The fifth logic module 735 is connected to the first logic module 734, and generates a fifth logic signal according to the seventh switch control signal Vg 7; the sixth logic block 736 is connected to the fifth logic block 735 and the Load, and generates a sixth switch control signal Vg6 according to the fifth logic signal and the state signal VL of the Load. The seventh logic 737 is coupled to the Load, and generates an eighth switch control signal Vg8 according to the state signal VL of the Load. The fourth switch control signal Vg4 is consistent with the state signal VL of the Load. The low level generation module 738 generates a fifth switch control signal Vg5, which is always low level Vg 5.

In this embodiment, the first logic block 734 is an and gate, the fifth logic block 735 is an not gate, the sixth logic block 736 is an and gate, and the seventh logic block 737 is an not gate.

The rest of the charging circuit 70 according to the sixth embodiment is the same as the fifth embodiment, and thus, detailed description thereof is omitted.

Fig. 14 shows a schematic block diagram of a charging circuit according to a seventh embodiment of the present invention. The charging circuit 80 includes a dc source 81, a power converter 82, a control circuit 83, an output port 84, and a bleed circuit.

Compared to the charging circuit of the sixth embodiment, the charging circuit 80 according to the seventh embodiment is mainly different in that the bleeder circuit of the output capacitor Cout includes a third resistor R3 and an eighth transistor Q8, and the third resistor R3 and the eighth transistor Q8 are connected in series across the output capacitor Cout. When the Load is not connected, the bleeder circuit is connected in parallel with the output capacitor Cout to provide a bleeder channel for the output capacitor Cout, thereby releasing the charge on the output capacitor Cout.

When the Load is removed from the output port 84, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are turned off to cut off the previous stage voltage, and at the same time, the eighth transistor Q8 is turned on, and the charges on the output capacitor Cout sequentially flow through the third resistor R3 and the eighth transistor Q8 to form a bleeder circuit, so that the output voltage Vo drops to the preset value.

Specifically, when the output port 84 is not connected with the Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an off state, the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state, so that the power converter 82 is disconnected from the dc source 81, the eighth switch control signal Vg8 controls the eighth transistor Q8 to be in an on state, and charges on the output capacitor Cout sequentially flow through the third resistor R3 and the eighth transistor Q8 to form a bleeding loop, so as to reduce the output voltage Vo to a preset value.

The rest of the charging circuit 80 according to the seventh embodiment is the same as the sixth embodiment, and thus, will not be described in detail.

Fig. 15 shows a schematic block diagram of a charging circuit according to an eighth embodiment of the present invention. The charging circuit 90 includes a dc source 91, a power converter 92, a control circuit 93, an output port 94, and a bleed circuit.

Compared to the charging circuit of the fifth embodiment, the charging circuit 90 according to the seventh embodiment is mainly different in that the bleeder circuit comprises a sixth transistor Q6, a second inductor L2 and a fourth resistor R4, wherein the sixth transistor Q6, the second inductor L2 and the fourth resistor R4 are connected in series between the first end of the output port and the control circuit; the charge on the output capacitor sequentially flows through the sixth transistor Q6, the second inductor L2 and the fourth resistor R4 to form a bleeding loop. The power converter 92 includes fourth to seventh transistors (Q4-Q7), a second inductor L2, and an output capacitor Cout.

Wherein the fourth transistor Q4 and the fifth transistor Q5 are connected in series between the first terminal and the second terminal of the direct current source 51; the sixth transistor Q6 and the seventh transistor Q7 are connected in series between the first terminal and the second terminal of the output port 94; a second inductor L2 is connected between a second node B between the fourth transistor Q4 and the fifth transistor Q5 and a third node C between the sixth transistor Q6 and the seventh transistor Q7; the output capacitor Cout is connected between a first terminal and a second terminal of the output port 94. The fourth resistor R4 is connected between the control terminal of the fourth transistor Q4 and the second node B. A control terminal of the fourth transistor Q4, a control terminal of the fifth transistor Q5, a control terminal of the sixth transistor Q6, and a control terminal of the seventh transistor Q7 are connected to the control circuit 93, respectively.

The switch control signals include a fourth switch control signal Vg4, a fifth switch control signal Vg5, a sixth switch control signal Vg6, and a seventh switch control signal Vg 7. The control end of the fourth transistor Q4 is connected to the control circuit 93, and receives a fourth switch control signal Vg 4; a control end of the fifth transistor Q5 is connected to the control circuit 93, and receives a fifth switch control signal Vg 5; a control end of the sixth transistor Q6 is connected to the control circuit 93, and receives a sixth switch control signal Vg 6; a control terminal of the seventh transistor Q7 is connected to the control circuit 93 and receives a seventh switch control signal Vg 7.

The output port 94 is connected to the power converter 92, and the output port 94 charges the Load when the Load is connected thereto, and discharges the output voltage Vo to a predetermined value when the Load is not connected thereto. Specifically, when no Load is connected, the bleed circuit multiplexes power converter 92 to provide a bleed path for output capacitor Cou, thereby discharging the charge on output capacitor Cout.

When the Load is connected to the output port 94, the operation states of the four transistors Q4-Q7 of the power converter 92 are the same as those of the fifth embodiment, and will not be described again. When the Load is removed from the output port 94, under the control of the control circuit 93, the fourth transistor Q4, the fifth transistor Q5 and the seventh transistor Q7 are turned off, the sixth transistor Q6 is turned on, the output capacitor Cout, the sixth transistor Q6, the second inductor L2 and the fourth resistor R4 form a bleeding loop, and the charge on the output capacitor Cout is released, so that the output voltage Vo drops to the preset value.

When the output port 94 is not connected with the Load, the fourth switch control signal Vg4 controls the fourth transistor Q4 to be in an off state, the fifth switch control signal Vg5 controls the fifth transistor Q5 to be in an off state, the sixth switch control signal Vg6 controls the sixth transistor Q6 to be in an on state, the seventh switch control signal Vg7 controls the seventh transistor Q7 to be in an off state, the charge on the output capacitor Cout is released through the fourth resistor R4, and the output voltage Vo is reduced to a preset value.

Fig. 16 shows a schematic block diagram of a control circuit in a charging circuit according to an eighth embodiment of the present invention. As shown in fig. 16, an operational amplifier 931, a sawtooth wave generating module 932, a comparator 933, a first logic 934, a fifth logic 935, a sixth logic 936, and a low level generating module 938.

Wherein, the operational amplifier 931 is connected to the output port 94 to obtain a sampling signal of the output voltage Vo, and comparing the sampling signal of the output voltage Vo with a reference voltage Vref generates an error signal Vcomp; the sawtooth wave generation module 932 provides a sawtooth wave signal; the comparator 933 is connected to the operational amplifier 931 and the sawtooth wave generation module 932, and generates a first PWM control signal PWM1 according to the error signal Vcomp and the sawtooth wave signal; the first logic 934 is connected to the Load and the comparator 933, and generates a seventh switch control signal Vg7 according to the state signal VL of the Load and the first PWM control signal PWM 1. The fifth logic module 935 is connected to the first logic module 934, and generates a fifth logic signal according to the seventh switch control signal Vg 7; the sixth logic block 936 is connected to the fifth logic block 935 and the Load, and generates a sixth switch control signal Vg6 according to the fifth logic signal and the state signal VL of the Load. The fourth switch control signal Vg4 is consistent with the state signal VL of the Load. The low level generation module 938 generates a fifth switch control signal Vg5, which is always low level Vg 5.

In this embodiment, the first logic block 934 is an and gate, the fifth logic block 935 is an not gate, and the sixth logic block 936 is an and gate.

The rest of the charging circuit 90 according to the seventh embodiment is the same as the fifth embodiment, and thus, detailed description thereof is omitted.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A charging circuit, comprising:

a DC source providing a DC supply voltage;

at least one power converter connected to the DC source for converting the DC supply voltage to an output voltage;

at least one output port, which is respectively connected with the power converter and charges the load;

the control circuit is used for generating a switch control signal of the power converter according to a state signal of a load and the output voltage so as to adjust the output voltage, wherein the state signal of the load represents whether the output port is connected with the load or not;

wherein the power converter comprises an output capacitor connected between a first end and a second end of an output port;

the charging circuit further comprises a bleeder circuit, and the bleeder circuit provides a bleeder channel for the output capacitor.

2. The charging circuit of claim 1, wherein the bleeding circuit provides a bleed path for the output capacitor when no load is connected to the output port, and the switch control signal controls the corresponding power converter and the bleeding circuit to reduce the output voltage across the output capacitor to a predetermined value.

3. The charging circuit of claim 1, wherein the switch control signal controls the respective power converter to produce a stable output voltage when a load is connected to the output port.

4. The charging circuit of claim 1, wherein the bleeding circuit of the output capacitance multiplexes the power converter.

5. The charging circuit of claim 1, wherein the power converter is a BUCK circuit.

6. The charging circuit of claim 5, wherein the bleeding circuit comprises a first inductance, a first transistor, and a first capacitance,

the first transistor and the first inductor are connected to a first end of the direct current source and a first end of the output port;

the first capacitor is connected between the first end and the second end of the direct current source;

the charges on the output capacitor sequentially flow through the first inductor, the first transistor and the first capacitor to form a bleeder circuit.

7. The charging circuit of claim 5, wherein the bleeding circuit comprises a first inductance and a second transistor,

wherein the first inductor and the second transistor are connected in series between a first end and a second end of the output port;

the charge on the output capacitor flows through the first inductor and the second transistor in sequence to form a bleeder circuit.

8. The charging circuit of claim 6 or 7, wherein the power converter further comprises a first transistor, a second transistor, and a first inductor,

the second transistor is connected between a first node between the first transistor and the first inductor and a second end of the output port;

the control end of the first transistor is connected with the control circuit and receives a first switch control signal;

the control end of the second transistor is connected with the control circuit and receives a second switch control signal.

9. The charging circuit of claim 8, wherein when the output port is connected to a load, the first and second switch control signals are in opposite phases and control the first and second transistors to alternately turn on and off, respectively.

10. The charging circuit of claim 8, wherein the first switch control signal controls the first transistor to be in a synchronous rectification or off state and the second switch control signal controls the second transistor to be in an alternating on and off state when the output port is not connected to a load.

11. The charging circuit of claim 8, wherein the first transistor is controlled to be in an off state by the first switch control signal and the second transistor is controlled to operate in a constant current region by the second switch control signal when the output port is not connected with a load.

12. The charging circuit of claim 8, wherein the first switch control signal controls the first transistor to be in an off state and the second switch control signal controls the second transistor to be in an on state when the output port is not connected to a load.

13. The charging circuit of claim 5, wherein the bleeding circuit comprises a first inductor, a first resistor, and a third transistor,

the first inductor, the first resistor and the third transistor are connected in series between the first end and the second end of the output port;

the charge on the output capacitor sequentially flows through the first inductor, the first resistor and the third transistor to form a bleeder circuit.

14. The charging circuit of claim 13, wherein the power converter further comprises a first transistor, a second transistor, a first inductor,

the first resistor and the third transistor are connected in series between a first node between the first transistor and the first inductor and a second end of the output port;

the control end of the second transistor is connected with the control circuit and receives a second switch control signal;

the control end of the third transistor is connected with the control circuit and receives a third switch control signal.

15. The charging circuit of claim 14, wherein when the output port is connected to a load, the first and second switch control signals are in opposite phases to control the first and second transistors to alternately turn on and off, respectively, and the third switch control signal controls the third transistor to turn off.

16. The charging circuit of claim 14, wherein the first switch control signal controls the first transistor to be in an off state, the second switch control signal controls the second transistor to be in an off state, and the third switch control signal controls the third transistor to be in an on state when the output port is not connected to a load.

17. The charging circuit of claim 5, wherein the bleeding circuit comprises a first inductance and a second resistance,

the first inductor and the second resistor are connected between the first end of the output port and the control circuit in series;

the charges on the output capacitor sequentially flow through the first inductor and the second resistor to form a bleeder circuit.

18. The charging circuit of claim 17, wherein the power converter further comprises a first transistor, a second transistor, a first inductor,

the second resistor is connected between a first node between the first transistor and the first inductor and the control end of the first transistor;

19. The charging circuit of claim 18, wherein the first switch control signal controls the first transistor to be in an off state and the second switch control signal controls the second transistor to be in an off state when the output port is not connected to a load.

20. The charging circuit of claim 1, wherein the power converter is a buck-boost circuit.

21. The charging circuit of claim 20, wherein the bleeding circuit comprises a sixth transistor, a second inductor, a fourth transistor, and a first capacitor,

the fourth transistor, the second inductor and the sixth transistor are connected in series between the first end of the direct current source and the first end of the output port;

the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor, the fourth transistor and the first capacitor to form a bleeder circuit.

22. The charging circuit of claim 20, wherein the bleeding circuit comprises a sixth transistor, a second inductance, and a fifth transistor,

the fifth transistor, the second inductor and the sixth transistor are connected in series between the second end of the direct current source and the first end of the output port;

and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor and the fifth transistor to form a bleeder circuit.

23. The charging circuit of claim 20, wherein the bleed circuit comprises sixth and seventh transistors,

wherein the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port;

and the charge on the output capacitor sequentially flows through the sixth transistor and the seventh transistor to form a bleeder circuit.

24. The charging circuit of any of claims 21-23, wherein the power converter further comprises fourth through seventh transistors and a second inductor,

wherein the fourth transistor and the fifth transistor are connected in series between a first terminal and a second terminal of a direct current source;

the sixth transistor and the seventh transistor are connected in series between the first terminal and the second terminal of the output port;

a second inductor is connected between a second node between the fourth transistor and the fifth transistor and a third node between the sixth transistor and the seventh transistor;

the output capacitor is connected between the first end and the second end of the output port;

the control end of the fourth transistor is connected with the control circuit and receives a fourth switch control signal;

the control end of the fifth transistor is connected with the control circuit and receives a fifth switch control signal;

the control end of the sixth transistor is connected with the control circuit and receives a sixth switch control signal;

and the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal.

25. The charging circuit of claim 24, wherein when the load is connected to the output port, the fourth switch control signal and the fifth switch control signal respectively control the fourth transistor and the fifth transistor to be alternately turned on, the sixth switch control signal controls the sixth transistor to be in a turned-on state, and the seventh switch control signal controls the seventh transistor to be in a turned-off state.

26. The charging circuit of claim 24, wherein when the load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in a conducting state, the fifth switch control signal controls the fifth transistor to be in an off state, and the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately conducting.

27. The charging circuit of claim 24, wherein the fourth, fifth, sixth and seventh control signals control the fourth, fifth, sixth and seventh transistors to alternately turn on, respectively, when the load is connected to the output port.

28. The charging circuit of claim 24, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in a synchronous rectification or off state, the fifth switch control signal controls the fifth transistor to be alternately turned on and off, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an off state.

29. The charging circuit of claim 24, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to operate in a constant current region, the sixth switch control signal controls the sixth transistor to operate in the constant current region, and the seventh switch control signal controls the seventh transistor to be in an off state, or to operate in a variable resistance region, or to operate in a constant current region, or to be in an on state.

30. The charging circuit of claim 24, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state or to operate in a variable resistance region or to operate in a constant current region or to operate in an on state, the sixth switch control signal controls the sixth transistor to operate in a constant current region, and the seventh switch control signal controls the seventh transistor to operate in the constant current region.

31. The charging circuit of claim 24, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an on state, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an off state or to operate in a variable resistance region.

32. The charging circuit of claim 24, wherein the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state or to operate in a variable resistance region, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an on state when the output port is not connected to a load.

33. The charging circuit of claim 24, wherein the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an on state, the sixth switch control signal controls the sixth transistor to be in an on state, and the seventh switch control signal controls the seventh transistor to be in an on state when the output port is not connected to a load.

34. The charging circuit of claim 20, wherein the bleeding circuit comprises a sixth transistor, a second inductor, a third resistor, and an eighth transistor,

the sixth transistor, the second inductor, the third resistor and the eighth transistor are connected in series between the first end and the second end of the output port;

and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor, the third resistor and the eighth transistor to form a bleeder circuit.

35. The charging circuit of claim 34 wherein the power converter further comprises fourth through seventh transistors and a second inductor,

the third resistor and the eighth transistor are connected in series between a second node between the fourth transistor and the fifth transistor and a second end of the output port;

the control end of the seventh transistor is connected with the control circuit and receives a seventh switch control signal;

and the control end of the eighth transistor is connected with the control circuit and receives an eighth switch control signal.

36. The charging circuit of claim 35, wherein when the output port is connected to a load, the fourth and fifth switch control signals control the fourth and fifth transistors to be alternately turned on, respectively, the sixth switch control signal controls the sixth transistor to be in an on state, the seventh switch control signal controls the seventh transistor to be in an off state, and the eighth switch control signal controls the eighth transistor to be in an off state.

37. The charging circuit of claim 35, wherein when the output port is connected to a load, the fourth switch control signal controls the fourth transistor to be in an on state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately turned on, and the eighth switch control signal controls the eighth transistor to be in an off state.

38. The charging circuit of claim 35, wherein the fourth, fifth, sixth and seventh control signals control the fourth, fifth, sixth and seventh transistors to be alternately turned on, respectively, and the eighth switch control signal controls the eighth transistor to be in an off state when the load is connected to the output port.

39. The charging circuit of claim 35, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an off state, the fifth switch control signal controls the fifth transistor to be in an off state, the sixth switch control signal controls the sixth transistor to be in an on state, the seventh switch control signal controls the seventh transistor to be in an off state, and the eighth switch control signal controls the eighth transistor to be in an on state.

40. The charging circuit of claim 20, wherein the bleeding circuit comprises a sixth transistor, a second inductance, and a fourth resistance,

the sixth transistor, the second inductor and the fourth resistor are connected in series between the first end of the output port and the control circuit;

and the charges on the output capacitor sequentially flow through the sixth transistor, the second inductor and the fourth resistor to form a bleeder circuit.

41. The charging circuit of claim 40, wherein the power converter further comprises fourth through seventh transistors and a second inductor,

the fourth resistor is connected between the second node and the control circuit;

42. The charging circuit of claim 41, wherein when the load is connected to the output port, the fourth switch control signal and the fifth switch control signal respectively control the fourth transistor and the fifth transistor to be alternately turned on, the sixth switch control signal controls the sixth transistor to be in a turned-on state, and the seventh switch control signal controls the seventh transistor to be in a turned-off state.

43. The charging circuit of claim 41, wherein when the load is connected to the output port, the fourth switch control signal controls the fourth transistor to be in a conducting state, the fifth switch control signal controls the fifth transistor to be in an off state, and the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately conducting.

44. The charging circuit of claim 41, wherein the fourth, fifth, sixth and seventh control signals control the fourth, fifth, sixth and seventh transistors to alternately turn on, respectively, when the load is connected to the output port.

45. The charging circuit of claim 41, wherein the fourth switch control signal controls the fourth transistor to be in an OFF state, the fifth switch control signal controls the fifth transistor to be in an OFF state, the sixth switch control signal controls the sixth transistor to be in an ON state, and the seventh switch control signal controls the seventh transistor to be in an OFF state when the output port is not connected to a load.

46. The charging circuit of claim 2, wherein the bleed circuit is connected in parallel with the output capacitance.

47. The charging circuit of claim 5, wherein the bleeding circuit comprises a first resistor and a third transistor,

the first resistor and the third transistor are connected in series between a first end and a second end of the output port;

the charge on the output capacitor sequentially flows through the first resistor and the third transistor to form a bleeder circuit.

48. The charging circuit of claim 47, wherein the power converter further comprises a first transistor, a second transistor, a first inductance;

the first resistor and the third transistor are connected in series between two ends of the output capacitor;

49. The charging circuit of claim 48, wherein when the output port is connected to a load, the first and second switch control signals are in opposite phases and control the first and second transistors to alternately turn on and off, respectively, and the third switch control signal controls the third transistor to turn off.

50. The charging circuit of claim 48, wherein the first switch control signal controls the first transistor to be in an OFF state, the second switch control signal controls the second transistor to be in an OFF state, and the third switch control signal controls the third transistor to be in an ON state when the output port is not connected to a load.

51. The charging circuit of claim 20, wherein the bleeding circuit comprises a third resistor and an eighth transistor, and the charge on the output capacitor sequentially flows through the third resistor and the eighth transistor to form a bleeding circuit.

52. The charging circuit of claim 51, wherein the power converter further comprises fourth through eighth transistors and a second inductor,

the third resistor and the eighth transistor are connected between two ends of the output capacitor in series;

53. A charging circuit as claimed in claim 52, wherein when a load is connected to the output port, the fourth and fifth switch control signals control the fourth and fifth transistors to be alternately turned on, respectively, the sixth switch control signal controls the sixth transistor to be in an on state, the seventh switch control signal controls the seventh transistor to be in an off state, and the eighth switch control signal controls the eighth transistor to be in an off state.

54. A charging circuit as claimed in claim 52, wherein when the output port is connected to a load, the fourth switch control signal controls the fourth transistor to be in an ON state, the fifth switch control signal controls the fifth transistor to be in an OFF state, the sixth switch control signal and the seventh switch control signal respectively control the sixth transistor and the seventh transistor to be alternately turned on, and the eighth switch control signal controls the eighth transistor to be in an OFF state.

55. The charging circuit of claim 52, wherein the fourth, fifth, sixth and seventh control signals control the fourth, fifth, sixth and seventh transistors to alternately turn on, respectively, when the load is connected to the output port, and the eighth switch control signal controls the eighth transistor to be in an off state.

56. The charging circuit of claim 52, wherein when the output port is not connected to a load, the fourth switch control signal controls the fourth transistor to be in an OFF state, the fifth switch control signal controls the fifth transistor to be in an OFF state, the sixth switch control signal controls the sixth transistor to be in an ON state, the seventh switch control signal controls the seventh transistor to be in an OFF state, and the eighth switch control signal controls the eighth transistor to be in an ON state.