CN111983859A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN111983859A CN111983859A CN202010788965.7A CN202010788965A CN111983859A CN 111983859 A CN111983859 A CN 111983859A CN 202010788965 A CN202010788965 A CN 202010788965A CN 111983859 A CN111983859 A CN 111983859A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an array substrate and a preparation method thereof, wherein the array substrate comprises a substrate and a plurality of functional layers, wherein at least two layers of conductive wires are arranged in the functional layers, and each layer of conductive wire is provided with a wire break area and wire routing areas positioned on two sides of the wire break area; at least one bridging line bridging the routing areas on both sides of each broken line area. The invention has the technical effect of greatly improving the success rate of repairing the conductive routing.
Description
Technical Field
The invention relates to the field of display, in particular to an array substrate and a preparation method thereof.
Background
With the continuous development of liquid crystal display technology, high requirements are put forward on the production efficiency of liquid crystal. The liquid crystal display panel comprises an array substrate and a color filter substrate, wherein a large number of conducting wires such as data wires and scanning wires are arranged on the array substrate.
In the process of manufacturing the array substrate, due to the influence of various factors, there may be a case that the data line or the scan line has a disconnection defect, and the conductive line cannot be conducted, so that the function of transmitting signals cannot be realized.
In the prior art, in order to repair a disconnection defect on a wire, a film is coated on the disconnection defect of the wire by using a disconnection repairing machine, and a repair wire is formed at the disconnection defect to conduct the wire.
However, after the repair line is formed by the line breaking repair machine, since the molecules on the surface of the repair line are not sequentially arranged, and after the repair line is formed by coating, cracks exist on the surface of the repair line, the surface of the repair line is uneven. Both of the above two situations can cause the impedance on the surface of the patch cord to increase, which leads to the increase of the resistance of the patch cord, and further leads to the reduction of the conductivity of the repaired wire, and affects the signal transmission capability of the wire.
Disclosure of Invention
The invention aims to solve the technical problem of low repairing efficiency in the existing array substrate repairing process.
In order to achieve the above object, the present invention provides an array substrate, including: a substrate; the functional layers are arranged on the substrate and provided with at least two layers of conductive wires, and the at least two layers of conductive wires are provided with a wire breaking area and wire routing areas positioned on two sides of the wire breaking area; at least one bridging line bridging the routing areas on both sides of each broken line area.
Further, the conductive trace includes: routing a grid; the source drain routing is arranged above the grid routing; the source drain electrode wiring is provided with a first broken line area and first wiring areas positioned on two sides of the first broken line area; the grid routing is provided with a second broken line area and second routing areas positioned on two sides of the second broken line area; the first bridge connectors are bridged with the first routing areas on two sides of the first broken line area, and the second bridge connectors are bridged with the second routing areas on two sides of the second broken line area.
Further, the first bridging line is silver.
Further, the second bridge connection line is made of tungsten.
In order to achieve the above object, the present invention further provides a method for manufacturing an array substrate, including the steps of: providing a substrate; preparing a functional layer on the upper surface of the substrate, wherein the functional layer comprises at least two layers of conductive wires; the at least two layers of conductive wires are provided with a wire break area and wire routing areas positioned on two sides of the wire break area; repairing the broken line area to form bridging lines arranged in the routing areas on the two sides of the broken line area; the repairing of the broken line area comprises the following steps: performing first repair on a first broken line region of the source drain routing line to form a first bridging line; and performing second repair on the second broken line region of the gate routing to form a second bridging line.
Further, the first repairing the first disconnection area of the source/drain routing includes: spraying a liquid material on the first wiring areas on two sides of the first wire breakage area in an ink-jet printing mode, wherein the liquid material contains metal silver to form a metal film layer; and curing the metal film layer, and plating metal silver on two sides of the first wire-breaking area of the gate layer to form a first bridging line.
Further, the second repairing the second wire-break area of the gate trace comprises: and two through holes are formed above the second wiring area of the grid wiring and are respectively positioned on the first wiring areas at two sides of the first broken line area of the grid wiring.
Further, repairing the second broken line region of the gate trace for the second time further includes: depositing a metal material at the through hole, wherein the metal material is tungsten hexacarbonyl; and decomposing the tungsten hexacarbonyl to obtain metal tungsten to form a second bridging line.
Further, decomposing the tungsten hexacarbonyl comprises: decomposing the tungsten hexacarbonyl by adopting laser light or thermal decomposition.
Furthermore, the resistance value between the first bridging line and the source drain electrode routing line is 20-40 ohms.
The method has the technical effects that the broken source and drain wires are repaired by adopting the metal silver, so that the repairing efficiency of the source and drain wires is improved, and the repairing efficiency of the array substrate is further improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic view of an array substrate according to an embodiment of the invention;
FIG. 2 is a cross-sectional view of the array substrate after a first repair according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of the array substrate after a second repair according to an embodiment of the invention;
fig. 4 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Some of the components are identified as follows:
1. routing the source and drain electrodes; 2. routing a grid; 3. a silver foil layer;
10. a substrate; 20. an insulating layer;
11. a first wire break region; 12. a first bridge connection line;
21. a second wire break region; 22. a through hole; 23. a second bridge line.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Specifically, referring to fig. 1 to 3, an embodiment of the invention provides an array substrate, which includes a substrate 10, a functional layer, and an insulating layer 20. The functional layer is provided with at least two layers of conductive wires and at least one bridging wire, and the at least two layers of conductive wires are provided with a wire breakage area and wire routing areas positioned on two sides of the wire breakage area; the bridge connection line is bridged on the wiring areas on two sides of each broken line area.
The functional layer is arranged on the upper surface of the substrate 10, the conductive traces comprise source drain traces 1 and grid traces 2, the grid traces 2 are arranged on the upper surface of the substrate 10, the insulating layer 20 is arranged on the upper surface of the grid traces 2, and the source drain traces 1 are arranged on the upper surface of the insulating layer 20.
Source-drain utmost point is walked line 1 and is had first broken string district 11 and locate the first district of walking of first broken string district 11 both sides, the line of first walking the line district is normal line, need not to repair, and the side of first broken string district 11 is equipped with first bridging line 12, and the both ends of first bridging line 12 are connected electrically respectively to first broken string district 11 both sides first district of walking, make form the electricity between first district of walking and the first bridging line 12 and be connected, walk around first broken string district 11, guarantee that source-drain utmost point walks that the signal of telecommunication of line 1 is complete.
The first bridging line 12 is made of a metal material, in this embodiment, the first bridging line 12 is made of metal silver, a silver foil layer 3 (see fig. 2) is further coated on the upper surface of the first bridging line 12, the silver foil layer 3 is used to ensure the thickness of the first bridging line 12, since silver has good fluidity, the silver foil layer 3 prevents the first bridging line from spreading to other routing areas, and otherwise, a short circuit occurs.
The success rate of repairing the first bridge connector 12 is 95% to 99%, and in this embodiment, the success rate of repairing the first bridge connector 12 is preferably 98%. The resistance between the first bridging line 12 and the first routing area is 20-40 ohms, in this embodiment, the resistance between the first bridging line 12 and the first routing area is preferably 30 ohms, the lower the resistance between the bridging line and the routing area is, the better the low resistance is, the low resistance does not affect the charging and discharging time of the TFT.
The grid wire 2 is provided with a second wire-breaking area 21 and second wire-routing areas arranged on two sides of the second wire-breaking area 21, the wires in the second wire-routing areas are normal wires and do not need to be repaired, a second bridging wire 23 is arranged on the side edge of the second wire-breaking area 21, two through holes 22 penetrate through the insulating layer film above the second wire-routing area, and the through holes 22 are arranged at one end, close to the second wire-breaking area 21, of the second wire-routing area. Two ends of the second bridging line 23 are electrically connected to the second routing regions on two sides of the second wire breakage region 21 from the through hole 22, so that the second routing regions are electrically connected with the second bridging line 23, and the second routing regions 21 are bypassed, thereby ensuring complete electrical signal transmission of the gate wire 2.
The second bridging line 23 is made of a metal material, in this embodiment, the second bridging line 23 is made of metal tungsten, and the success rate of repairing the second bridging line 23 is 93% to 97%, and in this embodiment, it is preferably 95%. The resistance between the second bridging line 23 and the second routing area is 300-800 ohms.
The final success rate of repairing the array substrate is 90% -95%, and in the embodiment, the final success rate of repairing the array substrate is preferably 93%, so that the success rate of repairing is greatly improved.
The array substrate has the technical effects that the broken line region of the source drain wiring is repaired by the metal silver, the broken line region of the grid wiring is repaired by the metal tungsten, and the repairing success rate of the broken line region is greatly improved.
As shown in fig. 4, the present embodiment further provides a method for manufacturing an array substrate, including steps S1 to S3.
S1 provides a base plate that functions as a substrate.
S2, preparing a functional layer on the upper surface of the substrate, wherein the functional layer comprises at least two layers of conductive wires, and the at least two layers of conductive wires are provided with a wire break area and wire routing areas positioned on two sides of the wire break area.
The conductive wires comprise grid wires and source and drain wires, the source and drain wires comprise a first broken wire area and first wire areas positioned on two sides of the first broken wire area, the first wire areas can transmit normal electric signals, but the first broken wire areas cannot transmit the electric signals.
The grid wiring comprises a second broken line area and second wiring areas positioned on two sides of the second broken line area, the second wiring areas can transmit normal electric signals, but the second broken line areas cannot transmit the electric signals.
Therefore, the first disconnection region of the source-drain trace and the second disconnection region of the gate trace need to be repaired, so that the normal transmission of the electrical signals can be performed.
S3, repairing the broken line area to form bridging lines bridging the routing areas on the two sides of the broken line area. The method specifically comprises the following steps:
and repairing the first broken line region of the source drain electrode routing line for the first time to form a first bridging line. Specifically, a liquid material is sprayed on the first wiring areas on two sides of the first wire break area in an ink-jet printing mode, wherein the liquid material contains metal silver to form a metal film layer; and solidifying the dropped liquid to form a first bridging line, wherein two ends of the first bridging line are electrically connected to the first routing areas on two sides of the first broken line area respectively, and because the metal silver has good conductive performance, electric signals can be transmitted from the first routing areas and the first bridging line.
Besides metal silver, the liquid material also comprises an adhesive, so that the liquid has certain fluidity after dropping on the substrate, but cannot spread to other wiring areas to cause the technical problem of short circuit.
The success rate of repairing the first bridge connector is 95% to 99%, and in this embodiment, the success rate of repairing the first bridge connector is preferably 98%. The resistance between the first bridging line and the first wiring area is 20-40 ohms, in the embodiment, the resistance between the first bridging line and the first wiring area is preferably 30 ohms, the whiter the metal silver is, the better the color is, the clean and impurity-free are, the backlight is realized, the light transmission is avoided, the lower the resistance between the bridging line and the wiring area is, the better the low resistance is, and the low resistance does not influence the charging and discharging time of the TFT.
And repairing a second broken line area of the grid routing for the second time to form a second bridging line, and specifically, forming two through holes at the film layer above the second routing area at two sides of the second broken line area, wherein the through holes are respectively positioned at two sides of the second broken line area.
Depositing a metal material on the substrate by adopting a chemical vapor deposition method, wherein the metal material is tungsten hexacarbonyl, and decomposing the tungsten hexacarbonyl by adopting a laser photolysis or thermal decomposition mode to obtain metal tungsten so as to form a second bridging line.
The principle equation of decomposition is: w (CO)6→ W + (CO) x, decomposition conditions are: and (3) performing thermal decomposition by using 300-400 nm laser or at the temperature of 60-80 ℃ to obtain the metal tungsten. In this embodiment, the decomposition is preferably performed by a laser at 335 nm or at 70 ℃.
The success rate of repairing the second bridge connector is 93-97%, and in this embodiment, the success rate is preferably 95%. The resistance between the second bridging line and the second routing area is 300-800 ohms.
After comprehensive repair, the final success rate of array substrate repair is 90% -95%, and in this embodiment, the final success rate of array substrate repair is preferably 93%, which greatly improves the success rate of repair.
The capital method of the array substrate has the technical effects that the broken line region of the source drain wiring is repaired by the metal silver, and the broken line region of the grid wiring is repaired by the metal tungsten, so that the repair success rate of the broken line region is greatly improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the method for manufacturing the same provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the description of the embodiments is only used to help understanding the technical solutions and the core ideas of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An array substrate, comprising:
a substrate; and
the functional layers are arranged on the substrate, at least two layers of conductive wires are arranged in the functional layers, and each layer of conductive wire is provided with a wire breaking area and wire routing areas positioned on two sides of the wire breaking area;
at least one bridging line bridging the routing areas on both sides of each broken line area.
2. The array substrate of claim 1, wherein the conductive trace comprises:
routing a grid;
the source drain routing is arranged above the grid routing;
the source drain electrode wiring is provided with a first broken line area and first wiring areas positioned on two sides of the first broken line area;
the grid routing is provided with a second broken line area and second routing areas positioned on two sides of the second broken line area;
the first bridge connectors are bridged with the first routing areas on two sides of the first broken line area, and the second bridge connectors are bridged with the second routing areas on two sides of the second broken line area.
3. The array substrate of claim 1,
the first bridging line is silver.
4. The array substrate of claim 1,
the second bridge connection line is made of tungsten.
5. The preparation method of the array substrate is characterized by comprising the following steps:
providing a substrate;
preparing a functional layer on the upper surface of the substrate, wherein the functional layer comprises at least two layers of conductive wires; the at least two layers of conductive wires are provided with a wire break area and wire routing areas positioned on two sides of the wire break area; and
repairing the broken line area to form bridging lines bridging the routing areas on the two sides of the broken line area;
the repairing of the broken line area comprises the following steps:
performing first repair on a first broken line region of the source drain routing line to form a first bridging line; and
and performing second repair on the second broken line region of the gate routing to form a second bridging line.
6. The method for manufacturing the array substrate according to claim 5, wherein the first repairing of the first broken line region of the source drain trace comprises:
spraying a liquid material on the first wiring areas on two sides of the first wire breakage area in an ink-jet printing mode, wherein the liquid material contains metal silver to form a metal film layer;
and curing the metal film layer, and plating metal silver on the side edge of the first wire-breaking area of the gate layer to form a first bridging line.
7. The method for manufacturing an array substrate according to claim 5, wherein the second repairing the second broken line region of the gate trace comprises:
two through holes are formed above the second wiring area of the grid wiring, and the two through holes are respectively located on the first wiring areas on two sides of the first broken line area of the grid wiring.
8. The method for manufacturing an array substrate according to claim 7, wherein the second repairing the second broken line region of the gate trace further comprises:
depositing a metal material at the through hole, wherein the metal material is tungsten hexacarbonyl;
and decomposing the tungsten hexacarbonyl to obtain metal tungsten to form a second bridging line.
9. The method of manufacturing an array substrate of claim 7, wherein decomposing the tungsten hexacarbonyl comprises:
decomposing the tungsten hexacarbonyl by adopting laser light or thermal decomposition.
10. The method of manufacturing an array substrate of claim 5,
the resistance value between the first bridging line and the source drain electrode routing line is 20-40 ohms.
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| CN202010788965.7A CN111983859A (en) | 2020-08-07 | 2020-08-07 | Array substrate and preparation method thereof |
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| CN202010788965.7A CN111983859A (en) | 2020-08-07 | 2020-08-07 | Array substrate and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022227291A1 (en) * | 2021-04-28 | 2022-11-03 | Tcl华星光电技术有限公司 | Display panel and manufacturing method therefor, and display apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395462A (en) * | 2002-06-06 | 2003-02-05 | 华中科技大学 | Electric circuit board production and its repairing method |
| US20080108229A1 (en) * | 2006-10-26 | 2008-05-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing Method of Semiconductor Device |
| CN104597640A (en) * | 2015-02-12 | 2015-05-06 | 深圳市华星光电技术有限公司 | Array substrate and broken line repairing method thereof |
| CN110267452A (en) * | 2019-06-03 | 2019-09-20 | 深圳市华星光电技术有限公司 | A kind of broken wire repair method and device |
-
2020
- 2020-08-07 CN CN202010788965.7A patent/CN111983859A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395462A (en) * | 2002-06-06 | 2003-02-05 | 华中科技大学 | Electric circuit board production and its repairing method |
| US20080108229A1 (en) * | 2006-10-26 | 2008-05-08 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing Method of Semiconductor Device |
| CN104597640A (en) * | 2015-02-12 | 2015-05-06 | 深圳市华星光电技术有限公司 | Array substrate and broken line repairing method thereof |
| CN110267452A (en) * | 2019-06-03 | 2019-09-20 | 深圳市华星光电技术有限公司 | A kind of broken wire repair method and device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022227291A1 (en) * | 2021-04-28 | 2022-11-03 | Tcl华星光电技术有限公司 | Display panel and manufacturing method therefor, and display apparatus |
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Application publication date: 20201124 |