CN111967132A - FET device electrical characteristic modeling method, system and storage medium - Google Patents

Abstract

The invention discloses an electrical characteristic modeling method, system and storage medium of an FET device, which are applied to semiconductor simulation technology. The method includes: acquiring fixed parameters of the FET device; acquiring target electrical index parameters of the FET device; configuring and initialize the variable parameters of the FET device; build a physical model according to the fixed parameters and variable parameters of the FET device; select a simulated physical model to simulate the electrical performance of the physical model to obtain simulated electrical index parameters; The index parameter and the simulated electrical index parameter modify the value of the variable parameter until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter satisfies a preset condition; The electrical performance simulation result of the physical model formed by the modified variable parameters and the fixed parameters is used to obtain the electrical characteristic model of the FET device. The present invention can improve the modeling efficiency.

Description

Method, system and storage medium for modeling electrical characteristics of FET devices

technical field

The invention relates to semiconductor simulation technology, in particular to a method, system and storage medium for modeling the electrical characteristics of a FET device.

Background technique

In order to continue to achieve Moore's Law and achieve higher transistor performance and circuit densities, advanced CMOS technology has focused on scaling device geometries for decades. In order to solve the short channel effect problem of traditional planar transistors at 20nm, the traditional planar semiconductor field effect transistor structure is transformed into a FinFET (Fin Field-Effect Transistor, Chinese name is fin field effect transistor) structure. Fin-type field effect transistors have excellent gate control capabilities and good compatibility with CMOS processes, and have become the most commonly used core devices in deep nanoscale process sizes.

However, in the past when the device was studied, the electrical characteristic model of the device was established by measuring after the device was fabricated, which was relatively inefficient.

SUMMARY OF THE INVENTION

In order to solve at least one of the above technical problems, the purpose of the present invention is to provide a method, system and storage medium for modeling the electrical characteristics of a FET device, so as to improve the modeling efficiency.

In the first aspect, the embodiments of the present invention provide:

A method for modeling electrical characteristics of a FET device, comprising the following steps:

obtaining fixed parameters of the FET device;

obtaining the target electrical index parameters of the FET device;

configuring and initializing variable parameters of the FET device;

constructing a physical model according to the fixed parameters and variable parameters of the FET device;

Selecting a simulation physical model to simulate the electrical performance of the physical model to obtain simulated electrical index parameters;

Modify the value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter, until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter satisfies preset conditions;

According to the electrical performance simulation result of the physical model formed by the modified variable parameters and the fixed parameters, an electrical characteristic model of the FET device is obtained.

Further, the FET device is a FinFET device with a manufacturing process of 14 nm, and the fixed parameters include gate length, Fin height, Fin width, equivalent gate oxide thickness, gate spacing, source/drain region doping concentration, bulk silicon at least one of doping concentration, channel doping concentration or source-drain resistance.

Further, the electrical performance simulation adopts Sentaurus TCAD device simulation software, the gate of the FET device uses the metal material TiN, and the gate oxide layer of the FET device uses the material HfO ₂ .

Further, the target electrical index parameter includes at least one of saturation current and electrical characteristic transfer curve.

Further, the simulated physical model includes quantum correction model, Fermi model, silicon band contraction model, carrier recombination model, electric field saturation migration model, Philips migration model, ThinLayer migration model, high-k scattering model or Lombardi model.

Further, the carrier transport equation is adopted as the shift-diffusion equation DriftDiffusion when conducting the electrical performance simulation.

Further, the variable parameter includes at least one of source-drain vertical diffusion depth, source-drain lateral diffusion width, metal work function or fixed charge concentration.

Further, the electrical characteristic model includes at least one of a drain induced barrier reduction effect, a subthreshold swing, a threshold voltage, a saturation current and an electrical characteristic transfer curve in a linear case and a saturation case.

In the second aspect, the embodiments of the present invention provide:

A system for modeling electrical characteristics of a FET device, comprising:

memory for storing programs;

A processor for loading the program to execute the method.

In a third aspect, the embodiments of the present invention provide:

A storage medium storing a program, the method described when the program is executed by a processor.

The beneficial effects of the embodiments of the present invention are: the present invention is based on the simulation technology, by adjusting some variable parameters of the FET device, so that some electrical index parameters of the FET device are close to the target electrical index parameters, and then the variable parameters of the FET device are determined, and based on the basis of The electrical performance simulation result of the physical model constructed with fixed parameters and variable parameters obtains the electrical characteristic model of the FET device.

Description of drawings

1 is a flowchart of a method for modeling electrical characteristics of a FET device according to an embodiment of the present invention;

2 is a flowchart of a method for modeling electrical characteristics of a FinFET device according to an embodiment of the present invention;

3 is a schematic diagram of a physical model of a FinFET device provided according to an embodiment of the present invention;

4 is a comparison diagram of an electrical characteristic transfer curve between a physical model of a FinFET device and an electrical index provided according to an embodiment of the present invention

FIG. 5 is a schematic diagram of electrical parameters of a physical model of a FinFET device provided according to an embodiment of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

Referring to FIG. 1 , the present embodiment discloses a method for modeling electrical characteristics of a FET device, including the following steps:

Step 110: Acquire the fixed parameters of the FET device.

In general, fixed parameters are surface-measurable or relatively fixed parameters such as size. For example, in some embodiments, the FET device is a FinFET device with a process of 14 nm, and the fixed parameters include gate length, Fin (fin) height, Fin width, equivalent gate oxide thickness, gate spacing, source /Drain region doping concentration, bulk silicon doping concentration, channel doping concentration or at least one of source-drain resistance.

Step 120: Acquire target electrical index parameters of the FET device.

Generally, in this step, some electrical index parameters that have a significant impact on the FET device are selected. For example, in some embodiments, the target electrical index parameter includes at least one of saturation current or electrical characteristic transfer curve.

Step 130: Configure and initialize variable parameters of the FET device.

In this embodiment, the variable parameters are generally parameters that are difficult to measure or some non-dimensional parameters. For example, in some embodiments, the variable parameter includes at least one of source/drain vertical diffusion depth, source/drain lateral diffusion width, metal work function, or fixed charge concentration.

Step 140: Build a physical model according to the fixed parameters and variable parameters of the FET device.

In this step, the physical model can be constructed by using Sentaurus TCAD (Technology Computer Aided Design, referring to a semiconductor process simulation and device simulation tool) device simulation software.

Step 150: Select a simulated physical model to perform electrical performance simulation on the physical model to obtain simulated electrical index parameters. In this step, the TCAD tool is used to simulate the FinFET structure. In order to deeply explore the physical characteristics of the device, it is necessary to add an appropriate physical model. According to the physical characteristics of the advanced FinFET device, determine its simulation physical model, including quantum correction model, Fermi model, Silicon band contraction model, carrier recombination model, electric field saturation migration model, Philips migration model, ThinLayer migration model, high-k scattering model, Lombardi model. On the basis of this model, the electrical characteristics of the device are simulated, and the carrier transport equation used is the shift-diffusion equation DriftDiffusion.

Step 160: Modify the value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter, until the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter is equal to The absolute value satisfies the preset condition.

In this step, the value of the variable parameter can be changed according to a preset rule or in a random manner, until the absolute value of the difference between the simulated electrical index parameter and the target electrical index parameter is smaller than the preset value. For example, for a curve, the average value of the absolute values of the numerical differences at the corresponding positions may be required to be smaller than a preset value.

Step 170: Obtain an electrical characteristic model of the FET device according to the electrical performance simulation result of the physical model formed by the modified variable parameters and the fixed parameters.

The electrical property model finally obtained in this step includes various electrical properties. In some embodiments, the electrical characteristic model includes at least one of a drain induced barrier lowering effect, a subthreshold swing, a threshold voltage, a saturation current, and an electrical characteristic transfer curve in a linear case and a saturation case.

According to the above embodiments, it can be determined that the present invention has high efficiency, and saves manpower and material resources compared with the solution of manufacturing devices and then testing them.

Referring to FIG. 2 to FIG. 5 , the present embodiment discloses a method for modeling electrical characteristics of an advanced FinFET device with a size of 14 nm. The method includes the following processing steps:

Step 1: Determine the key parameters of 14nm size advanced FinFET devices, i.e. fixed parameters;

Step 2: Use TCAD device simulation to establish a physical model of an advanced FinFET device with a size of 14 nm according to the size parameters;

Step 3: Determine the target electrical specifications for 14nm size advanced FinFET devices;

Step 4: Based on TCAD, determine the simulation physical model of the simulated electrical characteristics;

Step 5: Fitting the established 14nm size advanced FinFET device physical model with the target electrical index;

Step 6: Extract other relevant parameters of the model, and establish a complete 14nm size advanced FinFET device model;

In step 1, the key dimension parameters of the 14nm size advanced FinFET device are determined through the empirical data of the prior art, wherein the gate length is 20nm, the Fin height is 42nm, the Fin width is 8nm, the equivalent gate oxide thickness is 0.5nm, The gate spacing is 70nm, the source/drain doping concentration is 1×10 ^-21 cm ^-3 , the bulk silicon doping concentration is 1×10 ^-18 cm ^-3 , and the channel doping concentration is 1×10 ^-15 cm ^-3 , The source-drain resistance is 1×10 ^-9 Ωcm ² .

In step 2, according to the key parameters of the 14nm size advanced FinFET device, the computer aided tool Sentaurus TCAD is used to perform device modeling and simulation of the semiconductor device, as shown in Figure 3 for the device model diagram. The device as a whole is mainly composed of a silicon dioxide substrate 306, the source and drain protrusions form a fin type, and a spacer region is formed between the source and drain regions and the channel region. A drain electrode 301 and a source electrode 303 are formed above the source and drain in contact with metal tungsten, and a gate electrode 302 is formed above the channel region in contact with a high-K metal gate TiN. A gate oxide layer 305 is placed between the gate and the channel region, and its material uses a thin layer of high-K material HfO ₂ combined with a thin layer of SiO ₂ . A Si ₃ N ₄ layer 304 is placed in the spaced region between the source-drain electrode and the gate electrode to isolate the mutual interference of the two electrodes. Among them, high K means that the dielectric material has a high dielectric constant, so that a good field effect is generated between the gate and the channel (between the source and the drain) and the leakage current density is reduced.

In step 3, the electrical index is determined by the empirical data of the prior art. When V _d is 0.05V, the saturation current Isat is _0.237mA /μM, and when V _d is 0.7V, the saturation current Isat is _1.04mA /μM μm. The DIBL of the N-type FinFET is ~60mV/V, and the electrical characteristic transfer curve.

In step 4, the FinFET structure is simulated using a TCAD tool, and an appropriate physical model needs to be added to delve into the physical properties of the device. Entering deep nanoscale semiconductor devices, the wave nature of electrons and holes cannot be ignored, and quantum correction models need to be added. The Philips model is used to describe the effect of temperature on the mobility and the scattering relationship between electron holes. The Lombardi model can be used to describe the mobility changes caused by high dielectric constants and the effects of phonon scattering.

According to the physical characteristics of advanced FinFET devices, determine their simulation physical models, including quantum correction model, Fermi model, silicon band contraction model, carrier recombination model, electric field saturation migration model, Philips migration model, ThinLayer migration model, high-k Scattering model, Lombardi model. On the basis of this model, the electrical characteristics of the device are simulated, and the carrier transport equation used is the shift-diffusion equation DriftDiffusion.

In step 5, the physical model is calibrated using _Sentautus TCAD software according to the existing saturation current Isat and electrical characteristic transfer curve. In FinFET devices, the channel region and bulk silicon region are doped uniformly, and the source and drain regions are doped with Gaussian doping. The transfer curve can be adjusted by changing the doping depth and diffusion width of the source and drain regions, and the downward diffusion depth is set to 30 nm. In the software, the work function of the gate TiN material is set to 4.66. According to the existing experience and fitting data, changing the work function to 4.4 can better fit. A fixed charge is injected between the channel and the gate oxide, and the fixed charge concentration is changed to fine-tune the threshold voltage and linear drive current. In device simulation with computer aided tools, all of its drain currents are normalized by the effective channel width, W _eff , which is W _eff = 2H _fin + W _fin .

The electrical characteristic transfer curves simulated by the computer aided tool Sentautus TCAD were compared with the electrical characteristic transfer curves of electrical indicators. As shown in Fig. 4, taking the logarithm of the ordinate drain current, it can be seen that the simulated curve roughly fits the electrical index curve. By measuring the electrical characteristics of the simulated curve, when V _d is 0.05V, the saturation current Isat is _0.217mA /μm, and the relative error with the electrical index is 8.44%. When V _d is 0.7V, the saturation current Isat is _1.08mA /μm, and the relative error with the electrical index is 3.82%. Both relative errors are less than 10%, indicating that the simulation curve is accurate.

In step 6, other parameters of the fitted simulation physical model are extracted and a complete 14nm size advanced FinFET device model is constructed, wherein the value of V _dd of the physical model is 0.7V. As shown in Figure 5, when V _d is 0.05V, the leakage current I _off is 2.59 ^-9 A/μm, the saturation current _Isat is 2.17 ^-4 A/μm, the subthreshold swing SS is 70.986 V/dec, and the threshold The voltage V _th is 0.195V. When V _d is 0.7V, the leakage current I _off is _4.27e ^-9 A/μm, the saturation current Isat is 1.08e ^-3 A/μm, the subthreshold swing SS is 67.139V/dec, and the threshold voltage V _th is 0.173V. The DIBL of the device model is 43.0769mV/V.

In this embodiment, based on the advanced prior art experience, the present invention simulates an advanced FinFET device with a size of 14 nm by means of a TCAD simulation tool, determines the physical characteristic model in the electrical characteristic simulation according to the physical characteristics of the FinFET, and determines the fitting electrical index. Adjust the model parameters to fit the data, and combine other characteristic parameters of device simulation to build a complete 14nm size advanced FinFET device model. The technical effect of the invention is that the performance of a new generation of advanced FinFET devices with a size of 14 nm can be accurately reflected. Through the modeling of the physical device of the FinFET device, the relative error between the simulation results and the electrical indicators is less than 10%, and the performance of the new generation of advanced FinFET devices with a size of 14 nm can be accurately reflected. It can analyze the characteristics of a new generation of semiconductor devices through physical modeling, and provide a research basis for the research and development analysis and optimization of advanced semiconductor devices.

This embodiment discloses a system for modeling electrical characteristics of a FET device, including:

memory for storing programs;

A processor for loading the program to execute the method.

This embodiment discloses a storage medium, which stores a program, and the method is described when the program is executed by a processor.

The step numbers in the above-mentioned method embodiments are set only for the convenience of description, and the order between the steps is not limited, and the execution order of each step in the embodiments can be performed according to the understanding of those skilled in the art Adaptive adjustment.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without departing from the spirit of the present invention, These equivalent modifications or substitutions are all included within the scope defined by the claims of the present application.

Claims (10)

1. an electrical characteristic modeling method of FET device, is characterized in that, comprises the following steps: obtaining fixed parameters of the FET device; obtaining the target electrical index parameters of the FET device; configuring and initializing variable parameters of the FET device; constructing a physical model according to the fixed parameters and variable parameters of the FET device; Selecting a simulation physical model to simulate the electrical performance of the physical model to obtain simulated electrical index parameters; Modify the value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter, until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter satisfies preset conditions; According to the electrical performance simulation result of the physical model formed by the modified variable parameters and the fixed parameters, an electrical characteristic model of the FET device is obtained. 2. The method for modeling electrical characteristics of a FET device according to claim 1, wherein the FET device is a FinFET device with a manufacturing process of 14 nm, and the fixed parameters include gate length, Fin height, Fin width, etc. at least one of effective gate oxide thickness, gate spacing, source/drain region doping concentration, bulk silicon doping concentration, channel doping concentration or source-drain resistance. 3. The method for modeling electrical characteristics of a FET device according to claim 1, wherein the electrical performance simulation adopts Sentaurus TCAD device simulation software, the gate of the FET device uses a metal TiN material, and the FET device uses a metal TiN material. The gate oxide layer uses HfO ₂ material. 4 . The method for modeling electrical characteristics of a FET device according to claim 1 , wherein the target electrical index parameter comprises at least one of a saturation current or an electrical characteristic transfer curve. 5 . 5 . The method for modeling electrical characteristics of a FET device according to claim 1 , wherein the simulated physical model includes a quantum correction model, a Fermi model, a silicon energy band contraction model, a carrier recombination model, and an electric field saturation model. 6 . Migration Model, Philips Migration Model, ThinLayer Migration Model, High-k Scattering Model or Lombardi Model. 6 . The method for modeling the electrical characteristics of a FET device according to claim 1 , wherein the carrier transport equation is adopted as the shift-diffusion equation DriftDiffusion during the electrical performance simulation. 7 . 7 . The method for modeling electrical characteristics of a FET device according to claim 1 , wherein the variable parameters include at least one of source-drain vertical diffusion depth, source-drain lateral diffusion width, metal work function or fixed charge concentration. 8 . . 8 . The method for modeling electrical characteristics of a FET device according to claim 1 , wherein the electrical characteristic model includes leakage-induced barrier reduction effect, subthreshold swing, threshold voltage, At least one of a saturation current and an electrical characteristic transfer curve. 9. A system for modeling electrical characteristics of FET devices, comprising: memory for storing programs; A processor for loading the program to execute the method according to any one of claims 1-8. 10. A storage medium storing a program, wherein when the program is executed by a processor, the method according to any one of claims 1-8 is implemented.

Images