CN111967132A - FET device electrical characteristic modeling method, system and storage medium - Google Patents
FET device electrical characteristic modeling method, system and storage medium Download PDFInfo
- Publication number
- CN111967132A CN111967132A CN202010651063.9A CN202010651063A CN111967132A CN 111967132 A CN111967132 A CN 111967132A CN 202010651063 A CN202010651063 A CN 202010651063A CN 111967132 A CN111967132 A CN 111967132A
- Authority
- CN
- China
- Prior art keywords
- electrical
- model
- fet device
- simulation
- parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000003860 storage Methods 0.000 title claims abstract description 8
- 238000004088 simulation Methods 0.000 claims abstract description 38
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000012546 transfer Methods 0.000 claims description 11
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 238000012937 correction Methods 0.000 claims description 5
- 230000006870 function Effects 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000008602 contraction Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005215 recombination Methods 0.000 claims description 3
- 230000006798 recombination Effects 0.000 claims description 3
- 229920006395 saturated elastomer Polymers 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000013508 migration Methods 0.000 description 9
- 230000005012 migration Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an electrical characteristic modeling method, a system and a storage medium of an FET device, which are applied to a semiconductor simulation technology, wherein the method comprises the following steps: acquiring fixed parameters of the FET device; acquiring a target electrical index parameter of the FET device; configuring and initializing variable parameters of the FET device; constructing a physical model according to the fixed parameters and the variable parameters of the FET device; selecting a simulation physical model to perform electrical performance simulation on the physical model to obtain simulation electrical index parameters; modifying the numerical value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter meets a preset condition; and obtaining an electrical characteristic model of the FET device according to an electrical performance simulation result of a physical model formed by the modified variable parameters and the fixed parameters. The invention can improve the modeling efficiency.
Description
Technical Field
The invention relates to a semiconductor simulation technology, in particular to a method and a system for modeling the electrical characteristics of an FET device and a storage medium.
Background
Advanced CMOS technology has been focused on scaling of device geometries for decades in order to continue to implement moore's law, achieving higher transistor performance and circuit density. In order to solve the problem of short channel Effect at 20nm of the conventional planar Transistor, the conventional planar semiconductor Field Effect Transistor (FinFET) structure is shifted to a FinFET (Fin-Field-Effect Transistor) structure. FinFET has excellent gate control capability and good compatibility with CMOS process, and is the most common core device in deep nanoscale process dimensions.
However, in the past, when a device is researched, an electrical characteristic model of the device is established by a mode of measuring after the device is manufactured, and the mode is relatively inefficient.
Disclosure of Invention
To solve at least one of the above-mentioned technical problems, the present invention is directed to: a method, system and storage medium for modeling electrical characteristics of FET devices to improve modeling efficiency are provided.
In a first aspect, an embodiment of the present invention provides:
a method of modeling electrical characteristics of a FET device, comprising the steps of:
acquiring fixed parameters of the FET device;
acquiring a target electrical index parameter of the FET device;
configuring and initializing variable parameters of the FET device;
constructing a physical model according to the fixed parameters and the variable parameters of the FET device;
selecting a simulation physical model to perform electrical performance simulation on the physical model to obtain simulation electrical index parameters;
modifying the numerical value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter meets a preset condition;
and obtaining an electrical characteristic model of the FET device according to an electrical performance simulation result of a physical model formed by the modified variable parameters and the fixed parameters.
Further, the FET device is a FinFET device with a process of 14nm, and the fixed parameters comprise at least one of gate length, Fin height, Fin width, equivalent gate oxide thickness, gate interval, source/drain region doping concentration, bulk silicon doping concentration, channel doping concentration or source/drain resistance.
Furthermore, the simulation software of the electrical performance adopts Sentaurus TCAD device simulation software, the gate of the FET device uses metal material TiN, and the gate oxide layer of the FET device uses material HfO2。
Further, the target electrical index parameter includes at least one of a saturation current, an electrical characteristic transfer curve.
Further, the simulation physical model comprises a quantum correction model, a Fermi model, a silicon energy band contraction model, a carrier combination model, an electric field saturation migration model, a Philips migration model, a ThinLayer migration model, a high-k scattering model or a Lombardi model.
Further, a carrier transport equation is adopted as a drift-diffusion equation DriftDiffusion when electrical property simulation is carried out.
Further, the variable parameter includes at least one of a source-drain vertical diffusion depth, a source-drain lateral diffusion width, a metal work function, or a fixed charge concentration.
Further, the electrical characteristic model includes at least one of a drain induced barrier lowering effect in a linear case and a saturation case, a sub-threshold swing, a threshold voltage, a saturation current, and an electrical characteristic transfer curve.
In a second aspect, an embodiment of the present invention provides:
a FET device electrical characteristic modeling system, comprising:
a memory for storing a program;
a processor for loading the program to perform the method.
In a third aspect, an embodiment of the present invention provides:
a storage medium storing a program, which when executed by a processor, performs the method.
The embodiment of the invention has the beneficial effects that: based on the simulation technology, partial variable parameters of the FET device are adjusted to enable partial electrical index parameters of the FET device to be close to target electrical index parameters, so that variable parameters of the FET device are determined, and an electrical property simulation result of a physical model constructed according to the fixed parameters and the variable parameters is used for obtaining an electrical property model of the FET device.
Drawings
FIG. 1 is a flow chart of a method for modeling electrical characteristics of a FET device according to an embodiment of the present invention;
fig. 2 is a flow chart of a method for modeling electrical characteristics of a FinFET device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a physical model of a FinFET device provided in accordance with an embodiment of the invention;
FIG. 4 is a graph comparing an electrical characteristic transfer curve of a physical model and an electrical index of a FinFET device provided in accordance with an embodiment of the invention
Fig. 5 is a schematic diagram of electrical parameters of a physical model of a FinFET device provided in accordance with an embodiment of the invention.
Detailed Description
The invention is further described with reference to the drawings and the specific examples.
Referring to fig. 1, the present embodiment discloses a method for modeling electrical characteristics of an FET device, including the steps of:
and step 110, acquiring fixed parameters of the FET device.
Typically, the fixed parameter is a measurable or relatively fixed parameter of a surface such as a dimension. For example, in some embodiments, the FET device is a 14nm process FinFET device, and the fixed parameters include at least one of gate length, Fin height, Fin width, equivalent gate oxide thickness, gate spacing, source/drain doping concentration, bulk silicon doping concentration, channel doping concentration, or source-drain resistance.
And step 120, acquiring a target electrical index parameter of the FET device.
Typically, some electrical characteristic parameter that has a significant effect on the FET device will be selected at this step, for example, in some embodiments, the target electrical characteristic parameter includes at least one of a saturation current or an electrical characteristic transfer curve.
In this embodiment, the variable parameter is typically a poorly measurable parameter or some non-dimensional parameter. For example, in some embodiments, the variable parameter comprises at least one of a source/drain vertical diffusion depth, a source/drain lateral diffusion width, a metal work function, or a fixed charge concentration.
In this step, a physical model may be constructed by using Sentaurus TCAD (Technology Computer aid Design, which refers to a semiconductor process simulation and device simulation tool) device simulation software.
And 150, selecting a simulation physical model to perform electrical performance simulation on the physical model to obtain a simulation electrical index parameter. In the step, a TCAD tool is adopted to simulate the FinFET structure, appropriate physical models are required to be added to deeply explore the physical characteristics of the device, and simulated physical models of the FinFET device are determined according to the physical characteristics of the advanced FinFET device, wherein the simulated physical models comprise a quantum correction model, a Fermi model, a silicon energy band contraction model, a carrier recombination model, an electric field saturation migration model, a Philips migration model, a thinLayer migration model, a high-k scattering model and a Lombardi model. And (3) performing device electrical characteristic simulation on the basis of the model, wherein the used carrier transport equation is a drift-diffusion equation DriftDiffusion.
And 160, modifying the numerical value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter meets a preset condition.
In this step, the value of the variable parameter may be changed according to a preset rule or in a random manner until the absolute value of the difference between the simulated electrical index parameter and the target electrical index parameter is smaller than a preset value. For example, for a curve, it may be required that the average of the absolute values of the numerical differences of the corresponding positions is smaller than a preset value.
And 170, obtaining an electrical characteristic model of the FET device according to an electrical performance simulation result of a physical model formed by the modified variable parameters and the fixed parameters.
The electrical characteristic model finally obtained in this step includes various electrical characteristics. In some embodiments, the electrical characteristic model includes at least one of a drain induced barrier lowering effect in a linear case and a saturation case, a sub-threshold swing, a threshold voltage, a saturation current, and an electrical characteristic transfer curve.
According to the embodiment, the method is high in efficiency, and labor and materials are saved compared with a scheme of manufacturing a device and then testing.
Referring to fig. 2-5, the present embodiment discloses a method for modeling electrical characteristics of a 14 nm-sized advanced FinFET device, the method comprising the following processing steps:
step 1: determining key parameters, namely fixed parameters, of the advanced FinFET device with the size of 14 nm;
step 2: establishing a physical model of the 14nm advanced FinFET device by using TCAD device simulation according to the size parameter;
and step 3: determining a target electrical index of the advanced FinFET device with the size of 14 nm;
and 4, step 4: determining a simulation physical model simulating electrical characteristics based on the TCAD;
step 6: extracting other relevant parameters of the model, and establishing a complete 14nm advanced FinFET device model;
in step 1, the key dimension parameters of the 14nm advanced FinFET device are determined by empirical data in the prior art, where the gate length is 20nm, the Fin height is 42nm, the Fin width is 8nm, the equivalent gate oxide thickness is 0.5nm, the gate spacing is 70nm, and the source/drain doping concentration is 1 × 10-21cm-3Doping concentration of bulk silicon is 1 x 10-18cm-3Channel doping concentrationDegree of 1 × 10-15cm-31 x 10 source-drain resistance-9Ωcm2。
In step 2, according to the key parameters of the 14nm advanced FinFET device, a computer aided tool Sentaurus TCAD is used to perform device modeling simulation on the semiconductor device, as shown in fig. 3, which is a device model diagram. The whole device is mainly composed of a silicon dioxide substrate 306, the source and drain protrusions form a fin shape, and a spacing region is arranged between the source and drain regions and the channel region. And a drain electrode 301 and a source electrode 303 are formed on the source and the drain in contact with the metal tungsten, and a gate electrode 302 is formed on the channel region in contact with the high-K metal gate TiN. A gate oxide layer 305 is arranged between the gate and the channel region, and the material of the gate oxide layer is high-K material HfO2Thin layer and SiO2The thin layers are combined. Placing Si in the spacing region between the source/drain electrode and the gate electrode3N4Layer 304 is provided to isolate the electrodes from interfering with each other. The high K is a dielectric material having a high dielectric constant, so that a good field effect is generated between a gate and a channel (between a source and a drain) and the leakage current density is reduced.
In step 3, the electrical index is determined from empirical data of the prior art, when V isdAt 0.05V, saturation current Isat0.237 mA/. mu.M, when VdAt 0.7V, saturation current IsatIt was 1.04 mA/. mu.m. DIBL for N-type FinFET is 60mV/V, and the electrical characteristic transfer curve.
In step 4, a TCAD tool is used to simulate a FinFET structure, and an appropriate physical model is added to deeply explore the physical characteristics of the device. Into deep nanometer sized semiconductor devices, the electron and hole mobility properties are not negligible and quantum correction models need to be added. The Philips model is used to describe the relationship between mobility affected by temperature and scattering between electron holes. The Lombardi model can be used for describing the influence of mobility change, phonon scattering and the like caused by high dielectric constant.
According to the physical characteristics of the advanced FinFET device, determining a simulation physical model of the FinFET device, wherein the simulation physical model comprises a quantum correction model, a Fermi model, a silicon energy band contraction model, a carrier recombination model, an electric field saturation migration model, a Philips migration model, a ThinLayer migration model, a high-k scattering model and a Lombardi model. And (3) performing device electrical characteristic simulation on the basis of the model, wherein the used carrier transport equation is a drift-diffusion equation DriftDiffusion.
In step 5, according to the existing saturation current IsatThe physical model was calibrated using sentausus TCAD software. In the FinFET device, the channel region and the bulk silicon region are doped uniformly, and the source and drain regions are doped Gaussian. The transfer curve can be adjusted by changing the doping depth and diffusion width of the source and drain regions, wherein the downward diffusion depth is set to be 30 nm. In software, the work function of the gate TiN material is set to 4.66, and according to the existing experience and fitting data, the work function is changed to 4.4, so that better fitting can be achieved. Fixed charges are injected between the channel and the gate oxide layer, and the fixed charge concentration of the fixed charges is changed to fine tune the threshold voltage and the linear driving current. When the device is simulated by a computer aided tool, all drain current is controlled by the effective channel width WeffNormalization of, W ofeff＝2Hfin+Wfin。
The electrical characteristic transfer curve simulated by the computer aided tool sentausus TCAD is compared with the electrical characteristic transfer curve of the electrical index. As shown in fig. 4, the drain current is logarithmically processed on the ordinate, and it can be seen that the simulated curve is approximately fitted to the electrical index curve. Obtained by measuring the electrical characteristics of an analog curve, when VdAt 0.05V, saturation current Isat0.217 mA/mum, and the relative error with the electrical index is 8.44%. When V isdAt 0.7V, saturation current Isat1.08 mA/mum, and the relative error with the electrical index is 3.82%. Both relative errors are less than 10%, which indicates that the fitting of the simulation curve is accurate.
In step 6, extracting other parameters of the fitted simulated physical model to construct a complete 14nm advanced FinFET device model, wherein V of the physical modelddIs 0.7V. When V is shown in FIG. 5dAt 0.05V, leakage current IoffIs 2.59-9A/μm, saturation current IsatIs 2.17-4A/mum, sub-threshold swing SS 70.986V/dec, threshold voltage VthAnd 0.195V. When V isdLeakage current I of 0.7VoffIs 4.27e-9A/μm, saturation current IsatIs 1.08e-3A/mum, sub-threshold swing SS 67.139V/dec, threshold voltage VthIt was 0.173V. DIBL of the device model was 43.0769 mV/V.
In this embodiment, based on advanced prior art experience, the 14nm advanced FinFET device is simulated by using a TCAD simulation tool, a physical characteristic model in electrical characteristic simulation is determined according to physical characteristics of the FinFET device, after fitting electrical indexes are determined, model parameter fitting data is adjusted, and a complete 14nm advanced FinFET device model is established by combining other characteristic parameters of device simulation. The method has the technical effects that the performance of the 14nm advanced FinFET device of the new generation can be accurately reflected, the relative error between a simulation result and an electrical index is less than 10% through the physical device modeling of the FinFET device, the performance of the 14nm advanced FinFET device of the new generation can be accurately reflected, the characteristic analysis can be carried out on the semiconductor device of the new generation through the physical modeling, and a research basis is provided for the research, development, analysis and optimization of the advanced semiconductor device.
The embodiment discloses a FET device electrical characteristic modeling system, including:
a memory for storing a program;
a processor for loading the program to perform the method.
The present embodiment discloses a storage medium storing a program which, when executed by a processor, performs the method described herein.
The step numbers in the above method embodiments are set for convenience of illustration only, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of modeling electrical characteristics of an FET device, comprising the steps of:
acquiring fixed parameters of the FET device;
acquiring a target electrical index parameter of the FET device;
configuring and initializing variable parameters of the FET device;
constructing a physical model according to the fixed parameters and the variable parameters of the FET device;
selecting a simulation physical model to perform electrical performance simulation on the physical model to obtain simulation electrical index parameters;
modifying the numerical value of the variable parameter according to the target electrical index parameter and the simulated electrical index parameter until the absolute value of the difference between the simulated electrical index parameter of the physical model corresponding to the modified variable parameter and the target electrical index parameter meets a preset condition;
and obtaining an electrical characteristic model of the FET device according to an electrical performance simulation result of a physical model formed by the modified variable parameters and the fixed parameters.
2. The method of claim 1, wherein the FET device is a FinFET device with a 14nm process, and the fixed parameters include at least one of gate length, Fin height, Fin width, equivalent gate oxide thickness, gate spacing, source/drain doping concentration, bulk silicon doping concentration, channel doping concentration, or source-drain resistance.
3. The method of claim 1, wherein the simulation of the electrical properties is performed by using Sentaurus TCAD device simulation software, the gate of the FET device is made of TiN, and the gate oxide layer of the FET device is made of HfO2A material.
4. The method of modeling electrical characteristics of a FET device of claim 1 wherein the target electrical index parameter comprises at least one of a saturation current or an electrical characteristic transfer curve.
5. The method of modeling electrical characteristics of a FET device according to claim 1, wherein the simulated physical model comprises a quantum correction model, a fermi model, a silicon band contraction model, a carrier recombination model, an electric field saturation mobility model, a Philips mobility model, a ThinLayer mobility model, a high-k scattering model, or a Lombardi model.
6. A method of modelling the electrical characteristics of a FET device as claimed in claim 1 wherein the carrier transport equation used in the simulation of the electrical properties is the drift-diffusion equation DriftDiffusion.
7. The method of claim 1 wherein the variable parameter comprises at least one of source-drain vertical diffusion depth, source-drain lateral diffusion width, metal work function, or fixed charge concentration.
8. The method of claim 1, wherein the electrical characteristic model comprises at least one of a leakage induced barrier lowering effect in linear and saturated cases, a sub-threshold swing, a threshold voltage, a saturation current, and an electrical characteristic transfer curve.
9. A FET device electrical characteristic modeling system, comprising:
a memory for storing a program;
a processor for loading the program to perform the method of any one of claims 1 to 8.
10. A storage medium storing a program, characterized in that the program, when executed by a processor, implements the method according to any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010651063.9A CN111967132B (en) | 2020-07-08 | 2020-07-08 | FET device electrical characteristic modeling method, system and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010651063.9A CN111967132B (en) | 2020-07-08 | 2020-07-08 | FET device electrical characteristic modeling method, system and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111967132A true CN111967132A (en) | 2020-11-20 |
| CN111967132B CN111967132B (en) | 2024-10-18 |
Family
ID=73361431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010651063.9A Active CN111967132B (en) | 2020-07-08 | 2020-07-08 | FET device electrical characteristic modeling method, system and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111967132B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN102184879A (en) * | 2011-05-03 | 2011-09-14 | 中国科学院上海微系统与信息技术研究所 | TCAD simulation calibration method of SOI field effect transistor |
| CN102637215A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Modeling method of semiconductor device |
| CN104881520A (en) * | 2015-05-04 | 2015-09-02 | 复旦大学 | Tri-gate Fin FET (fin field effect transistor) potential and sub-threshold oscillation amplitude extracting method |
-
2020
- 2020-07-08 CN CN202010651063.9A patent/CN111967132B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN102637215A (en) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | Modeling method of semiconductor device |
| CN102184879A (en) * | 2011-05-03 | 2011-09-14 | 中国科学院上海微系统与信息技术研究所 | TCAD simulation calibration method of SOI field effect transistor |
| CN104881520A (en) * | 2015-05-04 | 2015-09-02 | 复旦大学 | Tri-gate Fin FET (fin field effect transistor) potential and sub-threshold oscillation amplitude extracting method |
Non-Patent Citations (2)
| Title |
|---|
| 孙俊雅: "14纳米节点FinFET器件自热效应及其建模研究", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》, no. 9, 15 September 2019 (2019-09-15), pages 3 * |
| 张燕: "三栅FinFET电学特性仿真分析与研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》, no. 2013, 15 December 2013 (2013-12-15), pages 3 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111967132B (en) | 2024-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Roy et al. | Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs | |
| CN102668079B (en) | Be configured for silicon-on-insulator (SOI) structure and the method for the harmonic wave of minimizing | |
| Asenov et al. | Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques | |
| KR20080010305A (en) | Simulation apparatus and simulation method used to design characteristics and circuits of semiconductor device, and semiconductor device fabrication method | |
| Oh et al. | Impact of etch angles on cell characteristics in 3D NAND flash memory | |
| Li et al. | Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors | |
| Stanojević et al. | Nano device simulator—a practical subband-BTE solver for path-finding and DTCO | |
| Gaidhane et al. | Compact modeling of surface potential, drain current and terminal charges in negative capacitance nanosheet FET including quasi-ballistic transport | |
| Chaudhuri et al. | 3D vs. 2D device simulation of FinFET logic gates under PVT variations | |
| CN111967132B (en) | FET device electrical characteristic modeling method, system and storage medium | |
| US9852956B2 (en) | Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices | |
| Jansson et al. | Intrinsic performance of InAs nanowire capacitors | |
| Kim et al. | Investigation and SPICE compact model of spacer region for static characteristics of 3-D NAND flash memories | |
| CN115081180A (en) | Gate tunneling current simulation method under total dose effect | |
| Miura-Mattausch et al. | MOSFET modeling gets physical | |
| Tan et al. | Random dopant fluctuation in gate-all-around nanowire FET | |
| Vandemaele et al. | The properties, effect and extraction of localized defect profiles from degraded FET characteristics | |
| Tamilarasi et al. | Machine Learning Assisted Device Modeling: A Survey | |
| Chandorkar et al. | Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method | |
| Spinelli et al. | Random dopant fluctuation and random telegraph noise in nanowire and macaroni MOSFETs | |
| Kondo et al. | A FinFET design based on three-dimensional process and device simulations | |
| Kim et al. | Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention | |
| Tang et al. | Two-dimensional self-consistent simulation of a triangular P-channel SOI nano-flash memory device | |
| Paul | Design and Performance Investigation of SiGe Heterojunction Based Vertical Dual Pocket Biosensor Design Based on Charge Plasma TFET | |
| Duane et al. | Novel capacitance coupling coefficient measurement methodology for floating gate nonvolatile memory devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |