CN111965660B - Time-of-flight sensor, ranging system and electronic device - Google Patents
Time-of-flight sensor, ranging system and electronic device Download PDFInfo
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- CN111965660B CN111965660B CN202011153204.0A CN202011153204A CN111965660B CN 111965660 B CN111965660 B CN 111965660B CN 202011153204 A CN202011153204 A CN 202011153204A CN 111965660 B CN111965660 B CN 111965660B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
- G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
Abstract
The application discloses time of flight sensor and relevant chip, electron device and ranging system, the time of flight sensor includes: a clock signal generating circuit for generating a first clock signal and a second clock signal; the transmission circuit is used for generating a third clock signal according to the first clock signal, and the third clock signal is output to the light-emitting module; a replica transfer circuit for emulating the transfer circuit and generating a fourth clock signal according to the second clock signal; a delay locked loop for generating a fifth clock signal according to one of a plurality of sixth clock signals and the fourth clock signal; a clock tree for generating the plurality of sixth clock signals according to the fifth clock signal; the pixel array is provided with a plurality of rows of pixel columns, wherein the reflected light pulses are sampled by the pixel columns according to the sixth clock signals respectively so as to generate sampling results; and the depth judgment unit is used for obtaining depth information according to the sampling result.
Description
Technical Field
The present disclosure relates to sensors, and particularly to a time-of-flight sensor, a distance measuring system and an electronic device.
Background
CMOS image sensors have been mass produced and applied. Conventional image sensors can generate two-dimensional (2D) images and videos, and recently, image sensors and systems that can generate three-dimensional (3D) images have received much attention, and these three-dimensional image sensors can be applied to face recognition, Augmented Reality (AR)/Virtual Reality (VR), unmanned aerial vehicles, and the like.
One of the existing three-dimensional image sensor implementations is a time of flight (TOF) based distance measurement technology, in which in order to increase accuracy, it is necessary to ensure that a phase relationship between an emission time point of a light pulse and a sampling time point of a reflected light pulse is synchronized or fixed at a preset value, otherwise, the accuracy is reduced, and therefore how to achieve the above purpose becomes an important work item in the field.
Disclosure of Invention
One of the objectives of the present application is to provide a time-of-flight sensor, a distance measuring system, and an electronic device, which can ensure that the phase relationship between the emission time point of the optical pulse and the sampling time point of the reflected optical pulse is fixed at a predetermined value, so as to solve the above problems.
An embodiment of the present application discloses a time-of-flight sensor for controlling a light-emitting module to intermittently emit light pulses, the light pulses being reflected by a target to generate reflected light pulses, the time-of-flight sensor comprising: a clock signal generating circuit for generating a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency and a predetermined phase difference therebetween; the transmission circuit is used for generating a third clock signal according to the first clock signal, and the third clock signal is output to the light-emitting module so that the light-emitting module intermittently emits the light pulse; a replica transfer circuit for emulating the transfer circuit and generating a fourth clock signal according to the second clock signal such that a phase difference between the fourth clock signal and the third clock signal and the predetermined phase difference can be maintained the same during temperature, bias, or process variations; a delay locked loop coupled to the replica transfer circuit and one of the plurality of sixth clock signals to generate a fifth clock signal, such that a phase difference between the one of the plurality of sixth clock signals and the fourth clock signal is maintained at zero; a clock tree for generating the sixth clock signals according to the fifth clock signal, wherein phases of the sixth clock signals are the same as each other; and the pixel array is provided with a plurality of pixel rows, and the plurality of pixel rows respectively sample the reflected light pulse according to the plurality of sixth clock signals so as to generate a sampling result.
An embodiment of the present application discloses a time-of-flight ranging system, the time-of-flight ranging system includes: the above-described time-of-flight sensor; and the light emitting module includes: a light source control path for generating a light source control signal according to the third clock signal; and a light source for intermittently emitting the light pulses in accordance with the light source control signal.
An embodiment of the present application discloses a time-of-flight ranging system, the time-of-flight ranging system includes: the above-described time-of-flight sensor; and the light emitting module includes: a light source control path for generating a light source control signal according to the third clock signal to replicate the light source control path, coupled between the replication transmitting circuit and the delay locked loop, the replicated light source control path being used for emulating the light source control path and generating a seventh clock signal according to the fourth clock signal to the delay locked loop of the time of flight sensor, such that a phase difference between the light source control signal and the seventh clock signal and a predetermined phase difference can be maintained the same during temperature, bias voltage, or process variation; and a light source for intermittently emitting the light pulses in accordance with the light source control signal.
An embodiment of the present application discloses an electronic device, including foretell distance measuring system: and a processor coupled to the ranging system.
The time-of-flight sensor, the distance measuring system and the electronic device can ensure that the phase relation between the emission time point of the light pulse and the sampling time point of the reflected light pulse is fixed at a preset value so as to maintain the accuracy of the obtained depth information.
Drawings
FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight ranging system of the present application.
Fig. 2 is a schematic diagram of a first embodiment of the delay locked loop of fig. 1.
Fig. 3 is a schematic diagram of a second embodiment of the delay locked loop of fig. 1.
Fig. 4 is a schematic view of an embodiment of the light emitting module in fig. 1.
FIG. 5 is a schematic diagram of a second embodiment of a time-of-flight ranging system of the present application.
Fig. 6 is a schematic view of an embodiment of the light emitting module in fig. 5.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein to facilitate describing a relationship between one element or feature relative to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
The existing three-dimensional image sensor has three main implementation modes: stereoscopic binocular, structured light and time of flight (ToF). Generally, in the time-of-flight implementation, a light pulse is emitted, and then the time-of-flight sensor is used to sample the reflected light pulse to calculate the time of the photon flying between the target object and the time-of-flight sensor, thereby obtaining the depth information of the target object.
However, the time of flight achieved by a time of flight sensor is often affected by the physical characteristics of the electronic components in the time of flight sensor. For example, when the temperature, voltage or manufacturing process of the operating environment in which the time-of-flight sensor is located changes, the physical characteristics of the electronic components of the time-of-flight sensor may be changed, so that the phase relationship between the emission time point of the light pulse and the sampling time point of the reflected light pulse cannot be fixed at a preset value, and the accuracy of the obtained depth information is degraded. Conversely, if the phase relationship between the emission time point of the optical pulse and the sampling time point of the reflected optical pulse is not affected by temperature, voltage, or manufacturing process, the accuracy of the time-of-flight sensor can be improved, as described in detail below.
FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight ranging system 100 of the present application. The time-of-flight ranging system 100 comprises a time-of-flight sensor 102 and a light-emitting module 120, which are used to detect the distance between the target 124 and the ranging system 100, and it should be noted that the distance between the target 124 and the ranging system 100 should be less than or equal to the maximum measurement distance of the ranging system 100. In this embodiment, the time-of-flight sensor 102 is disposed on a first chip, for example, the first chip may be a sensor chip, or the time-of-flight sensor 102 belongs to a part of the first chip; the light emitting module 120 is disposed on the second chip, and the first chip and the second chip can be disposed in an electronic device, for example, any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, or a tablet computer.
Specifically, the time-of-flight sensor 102 controls the light-emitting module 120 to emit the light pulses 122 at a predetermined frequency, intensity, and the like, and in the present embodiment, the time-of-flight sensor 102 controls the light-emitting module 120 to intermittently emit the light pulses 122. Light pulse 122 is reflected by object 124 to produce reflected light pulse 126. The time-of-flight sensor 102 senses and samples the reflected light pulse 126 to produce a sampling result pout that can be used to calculate the distance between the target object 124 and the ranging system 100, while depth information of the target object 124 can be obtained by calculating the distance of different portions of the target object 124.
The time-of-flight sensor 102 includes a clock signal generation circuit 104, a transfer circuit 106, a replica transfer circuit 108, a delay locked loop 110, a clock tree 112, and a pixel array 114. Wherein the clock signal generating circuit 104 is used for generating a first clock signal clk1 and a second clock signal clk2, wherein the frequencies of the first clock signal clk1 and the second clock signal clk2 are the same, and the first clock signal clk1 and the second clock signal clk2 have a predetermined phase difference φ 1. For example, the clock signal generating circuit 104 may generate the first clock signal clk1 and the second clock signal clk2 according to a reference clock (not shown), wherein the reference clock source may be a crystal oscillator external to the chip where the time-of-flight sensor is located. In addition, it should be noted that the value of the predetermined phase difference φ 1 can be set according to a time-of-flight algorithm in a manner not discussed in the present application, and thus the value of the predetermined phase difference φ 1 is not limited in the present application, i.e., the predetermined phase difference φ 1 can be greater than zero, less than zero, or equal to zero.
As can be seen from fig. 1, the first clock signal clk1 controls the light emitting module 120 to emit the light pulse 122 through a path; the second clock signal clk2 controls the timing of the pixel array 114 sampling the reflected light pulse 126 via another path, and the purpose of the present application is to keep the difference between the point in time when the light emitting module 120 emits the light pulse 122 and the point in time when the pixel array 114 samples the reflected light pulse 126 at the predetermined phase difference φ 1 as much as possible, and is not affected by temperature, voltage or manufacturing process.
The transmitting circuit 106 is used for generating a third clock signal clk3 according to the first clock signal clk1, and the third clock signal clk3 is output to the light emitting module 120, so that the light emitting module 120 intermittently emits the light pulses 122. Generally, the second chip on which the light emitting module 120 is located and the second chip on which the time of flight sensor 102 is located are different chips, and the frequency of the first clock signal clk1 may be in the order of several hundred MHz, so the transmitting circuit 106 needs to process the first clock signal clk1 in order to transmit the first clock signal clk1 out of the chip on which the time of flight sensor 102 is located, for example, the transmitting circuit 106 is a Low-Voltage Differential Signaling (LVDS) circuit, which converts the first clock signal clk 25 into a small-amplitude Differential signal 1, so as to reduce noise and save power consumption. However, the present application is not limited thereto, and the transmitting circuit 106 may use other methods, for example, the third clock signal clk3 may be a non-differential signal.
In summary, no matter how the transmitting circuit 106 is used, it is impossible to cause no delay to the first clock signal clk1, that is, it is difficult to ensure that the phase between the first clock signal clk1 and the second clock signal clk2 does not change after the first clock signal clk1 passes through the transmitting circuit 106, so that the time point of controlling the light emitting module 120 to emit the light pulse 122 becomes uncontrollable. The solution of the present application is to add a replica transmission circuit 108 to simulate the transmission circuit 106 in the path from the second clock signal clk2 to the pixel array 114, where the replica transmission circuit 108 generates the fourth clock signal clk4 according to the second clock signal clk2, and since the design of the replica transmission circuit 108 and the design of the transmission circuit 106 are substantially the same, the delays caused by the first clock signal clk1 and the third clock signal clk3 are substantially the same. Further, since the replica transfer circuit 108 and the transfer circuit 106 are located in the same chip, the influence of temperature, voltage, or manufacturing process on the replica transfer circuit 108 and the transfer circuit 106 is substantially the same, in other words, a change in temperature, voltage, or manufacturing process causes the replica transfer circuit 108 and the transfer circuit 106 to change synchronously, so that the phase difference between the fourth clock signal clk4 and the third clock signal clk3 can be maintained at the predetermined phase difference Φ 1 when the temperature, bias, or process changes. In some embodiments, the layout of the transfer circuit 106 is directly adjacent to the layout of the replica transfer circuit 108, making the effects of temperature, voltage, or manufacturing process on the transfer circuit 106 and the replica transfer circuit 108 more nearly uniform.
In the present embodiment, the layout of the replica transfer circuit 108 and the layout of the transfer circuit 106 are identical. However, the present application is not limited thereto, and in some embodiments, the layout of the replica transfer circuit 108 and the layout of the transfer circuit 106 are not exactly the same, for example, the layout of the replica transfer circuit 108 and the layout of the transfer circuit 106 are arranged in pairs, or other special designs are used as long as the delay caused by the transfer circuit 106 to the first clock signal clk1 and the delay caused by the replica transfer circuit 108 to the third clock signal clk3 are approximately the same, which is within the scope of the present application.
Since the fourth clock signal clk4 needs to be distributed to the pixel columns of the pixel array 114, generally, the number of the pixel columns of the pixel array 114 is large, so that in order to provide sufficient driving force, the clock tree 12 is needed to generate the sixth clock signals clk6 with sufficient driving force to the pixel columns of the pixel array 114, and the phase relationship between the sixth clock signals clk6 is kept fixed. The delay locked loop 110 is to ensure that the phase difference between the plurality of sixth clock signals clk6 and the fourth clock signal clk4 output by the clock tree 12 is kept to zero during temperature, bias or process variation, so as to ensure that the phase difference between the plurality of sixth clock signals clk6 and the third clock signal clk3 output by the clock tree 12 is kept at the predetermined phase difference Φ 1. Specifically, the phases of the plurality of sixth clock signals clk6 output by the clock tree 12 are all consistent, and the delay locked loop 110 generates the fifth clock signal clk5 according to one of the plurality of sixth clock signals clk6 and the fourth clock signal clk 4.
The clock tree 112 includes a plurality of paths, each of the plurality of paths includes a start terminal and an end terminal, the plurality of start terminals are in common and are used for receiving the fifth clock signal clk5, the plurality of end terminals are respectively coupled to the plurality of rows of pixel rows of the pixel array 114, the fifth clock signal clk5 is converted into a plurality of sixth clock signals clk6 to the plurality of rows of pixel rows from the source through the plurality of paths, the plurality of paths respectively have a plurality of buffers thereon to increase the driving force, and the signal transmission distance from the start terminal to the end terminal and the arrangement of the buffers of each of the plurality of paths are designed, for example, the plurality of paths have the same length and the same number of buffers, so that the phase difference between the plurality of sixth clock signals clk6 can be kept to zero during temperature, bias voltage or process variation.
It should be noted that the delay of each transmission line among the clock signal generating circuit 104, the transmission circuit 106, the replica transmission circuit 108, the delay locked loop 110, the clock tree 112 and the pixel array 114 in fig. 1 is relatively small compared to the compensation brought by the replica transmission circuit 108, the delay locked loop 110 and the clock tree 112, and therefore the delay of each transmission line is omitted and will not be discussed here.
Fig. 2 is a schematic diagram of a first embodiment of the delay locked loop 110 of fig. 1. The delay locked loop 110 includes a phase detector 202, a charge pump 204, a filter 206, and a voltage controlled delay line 208. The phase detector 202 receives any one of the sixth clock signal clk6 and the fourth clock signal clk4, and is used to generate phase difference information se1 between the sixth clock signal and the fourth clock signal clk 4. in the embodiment of fig. 2, the phase detector 202 is implemented using an analog circuit. The charge pump 204 is used for generating voltage information sc1 to charge or discharge the filter 206 in response to the phase difference information se1, and the filter 206 performs filtering processing on the voltage information sc1 to generate the voltage-controlled delay line control signal sf 1. In the embodiment of fig. 2, the filter 206 is implemented using analog circuitry.
The voltage controlled delay line 208 is used to pass the fourth clock signal clk4 through the voltage controlled delay line 208 to generate the fifth clock signal clk5, and the voltage controlled delay line 208 causes a variable phase difference between the fifth clock signal clk5 and the fourth clock signal clk4, and the variable phase difference is controlled by the voltage controlled delay line control signal sf 1. In the embodiment of fig. 2, the voltage controlled delay line 208 is implemented using analog circuitry. That is, the voltage controlled delay line is controlled by the control signal sf1 such that the fourth clock signal clk4 input to the voltage controlled delay line generates a corresponding phase difference to output the fifth clock signal clk 5.
Fig. 3 is a diagram of a second embodiment of the delay locked loop 110 of fig. 1. The delay locked loop 110 includes a phase detector 302, an accumulator 304, a filter 306, and a digital delay line 308. Similar to the delay locked loop 110 of fig. 3 and the delay locked loop 110 of fig. 2, the difference is that the delay locked loop 110 of fig. 3 is implemented using digital circuitry. The phase detector 302 is used to generate phase difference information se2 between one of the sixth clock signals clk6 and the fourth clock signal clk4, and in the embodiment of fig. 3, the phase detector 202 is implemented using an analog circuit. The accumulator 304 is used for generating accumulated phase information sc2 to the filter 306 according to the accumulated phase difference information se2, so that the filter 306 performs filtering processing on the voltage information sc2 to generate the digital delay line control signal sf 2. In the embodiment of fig. 3, filter 306 is implemented using digital circuitry.
The digital delay line 308 is used to pass the fourth clock signal clk4 through the digital delay line 308 to generate the fifth clock signal clk5, and the digital delay line 208 causes a variable phase difference between the fifth clock signal clk5 and the fourth clock signal clk4, and the variable phase difference is controlled by the digital delay line control signal sf 2.
The pixel array 114 has a plurality of pixel columns, which respectively sample the reflected light pulses 126 according to a plurality of sixth clock signals clk6 to generate a sampling result pout. In some embodiments, the time-of-flight sensor 102 may include a depth determination unit 116, and the depth determination unit 116 is used to obtain the depth information of the target object 124 according to the sampling result pout. In some other embodiments, the depth determination unit 116 may be unnecessary, for example, the sampling result pout generated by the pixel array 114 is sent to a processor outside the chip where the time-of-flight sensor 102 is located to calculate the depth information of the target object 124.
In some embodiments, to ensure that the time interval between the time point when the third clock signal clk3 arrives at the light emitting module 120 and the time point when the light pulse 122 is actually emitted changes with temperature, bias voltage, or process variations, the light emitting module 120 of fig. 4 may be used. Fig. 4 is a schematic diagram of an embodiment of the light emitting module 120 in fig. 1. After the third clock signal clk3 reaches the light emitting module 120, the light source control path 402 generates a light source control signal sl, and the light source 404 intermittently emits the light pulses 122 according to the light source control signal sl. The light source 404 may be, but is not limited to, a Laser Diode (LD), a Light Emitting Diode (LED), or other light source that can generate the light pulse 122. The light source control path 402 is designed to make the phase difference between the light source control signal sl and the third clock signal clk3 independent of temperature, bias voltage or process.
However, the embodiment of fig. 1 is not limited to the light emitting module 120 of fig. 4. However, using a typical light module may contribute a slight error such that the difference between the point in time that the light module 120 emits the light pulse 122 and the point in time that the pixel array 114 samples the reflected light pulse 126 is not exactly equal to the predetermined phase difference φ 1. Therefore, the present application also proposes the embodiment of fig. 5 to provide another approach besides using the light emitting module 120 of fig. 4.
FIG. 5 is a diagram of a second embodiment of a time-of-flight ranging system 500 of the present application. The difference between the time-of-flight ranging system 500 in fig. 5 and the time-of-flight ranging system 100 in fig. 1 is that the fourth clock signal clk4 in fig. 1 is directly sent to the delay locked loop 110, but the fourth clock signal clk4 in fig. 5 is sent to the off-chip light emitting module 520 of the time-of-flight sensor 502 before being fed back to the delay locked loop 110. The purpose of the simulation is to simulate the light source control path 602 of the light emitting module 520 in the path of the second clock signal clk2 to match the path of the first clock signal clk 1.
Fig. 6 is a schematic view of an embodiment of the light emitting module 520 in fig. 5. In the present application, in the path from the second clock signal clk2 to the pixel array 114, a replica light source control path 604 is additionally added to the light emitting module 520 to simulate the light source control path 602, and the replica light source control path 604 generates the seventh clock signal clk7 according to the fourth clock signal clk4, since the design of the replica light source control path 604 and the design of the light source control path 602 are substantially the same, the delay caused by the third clock signal clk3 and the delay caused by the fourth clock signal clk4 are substantially the same. Furthermore, since the duplicate light source control path 604 and the light source control path 602 are located in the same chip, the temperature, voltage or manufacturing process will have substantially the same effect on the duplicate light source control path 604 and the light source control path 602, in other words, a temperature, voltage or manufacturing process change will cause the duplicate light source control path 604 and the light source control path 602 to change synchronously, so that the phase difference between the light source control signal sl and the seventh clock signal clk7 can be maintained at the predetermined phase difference φ 1 when the temperature, bias voltage or process changes. The seventh clock signal clk7 and fed back to the delay locked loop 110 of the delay locked loop 110.
In the present embodiment, the layout of the duplicate light source control path 604 is identical to the layout of the light source control path 602. However, the present application is not limited thereto, and in some embodiments, the layout of the light source control path 604 and the layout of the light source control path 602 are duplicated, for example, the layout of the light source control path 604 and the layout of the light source control path 602 are arranged in a pair, or by other special designs, as long as the delay caused by the light source control path 602 to the third clock signal clk3 and the delay caused by the light source control path 604 to the fourth clock signal clk4 can be made approximately the same, which is within the scope of the present application.
The foregoing description has set forth briefly the features of certain embodiments of the present application so that those skilled in the art may more fully appreciate the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should understand that they can still make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (14)
1. A time-of-flight sensor for controlling a light emitting module to intermittently emit light pulses that are reflected by a target to produce reflected light pulses, the time-of-flight sensor comprising:
a clock signal generating circuit for generating a first clock signal and a second clock signal, wherein the first clock signal and the second clock signal have the same frequency and a predetermined phase difference therebetween;
the transmission circuit is used for generating a third clock signal according to the first clock signal, and the third clock signal is output to the light-emitting module so that the light-emitting module intermittently emits the light pulse;
a replica transmission circuit for emulating the transmission circuit and generating a fourth clock signal according to the second clock signal such that a phase difference between the fourth clock signal and the third clock signal is maintained to be the same as the predetermined phase difference;
a delay locked loop coupled to the replica transfer circuit and one of the plurality of sixth clock signals to generate a fifth clock signal, such that a phase difference between the one of the plurality of sixth clock signals and the fourth clock signal is maintained at zero;
a clock tree for generating the sixth clock signals according to the fifth clock signal, wherein phases of the sixth clock signals are the same as each other; and the pixel array is provided with a plurality of pixel rows, and the plurality of pixel rows respectively sample the reflected light pulse according to the plurality of sixth clock signals so as to generate a sampling result.
2. The time-of-flight sensor of claim 1, wherein the clock tree comprises a plurality of paths, each of the plurality of paths comprises a start end and an end, the start ends of the plurality of paths are concurrent and configured to receive the fifth clock signal, the end ends of the plurality of paths are coupled to the plurality of rows of pixels, respectively, such that the fifth clock signal is converted into a plurality of sixth clock signals to the plurality of rows of pixels via the plurality of paths, and signal propagation distances from the start end to the end of each of the plurality of paths are matched to each other, such that a phase difference between the plurality of sixth clock signals can be kept to zero during temperature, bias voltage, or process variation.
3. The time-of-flight sensor of claim 1, wherein the time-of-flight sensor is disposed on a first chip and the layout of the transmit circuit is adjacent to the layout of the replica transmit circuit.
4. The time of flight sensor of claim 1, wherein the delay locked loop generates the fifth clock signal as a function of the fourth clock signal and one of the plurality of sixth clock signals.
5. The time-of-flight sensor of claim 4, wherein the delay locked loop comprises:
a phase detector to generate phase difference information between one of the sixth clock signals and the fourth clock signal;
the charge pump is used for generating voltage information to the filter according to the phase difference information;
the filter is used for filtering the voltage information to generate a voltage-controlled delay line control signal; and
the voltage-controlled delay line is used for enabling the fourth clock signal to pass through the voltage-controlled delay line to generate the fifth clock signal, and the voltage-controlled delay line causes the fifth clock signal and the fourth clock signal to have variable phase difference, and the variable phase difference is controlled by the voltage-controlled delay line control signal.
6. The time-of-flight sensor of claim 4, wherein the delay locked loop comprises:
a phase detector to generate phase difference information between one of the sixth clock signals and the fourth clock signal;
an accumulator for accumulating the phase difference information to generate accumulated phase information to a filter;
the filter is used for filtering the accumulated phase information to generate a digital delay line control signal; and
a digital delay line for passing the fourth clock signal through the digital delay line to generate the fifth clock signal, and the digital delay line causes a variable phase difference between the fifth clock signal and the fourth clock signal, and the variable phase difference is controlled by the digital delay line control signal.
7. The time-of-flight sensor of claim 1, further comprising:
and the depth judgment unit is used for obtaining depth information according to the sampling result.
8. A time-of-flight ranging system, comprising:
a time-of-flight sensor as claimed in any one of claims 1 to 7; and
the light emitting module includes:
a light source control path for generating a light source control signal according to the third clock signal; and
a light source for intermittently emitting the light pulses in accordance with the light source control signal.
9. The ranging system of claim 8, wherein a phase difference between the third clock signal and the light source control signal is zero.
10. A time-of-flight ranging system, comprising:
a time-of-flight sensor as claimed in any one of claims 1 to 3 and 7; and
the light emitting module includes:
a light source control path for generating a light source control signal according to the third clock signal; a replica light source control path coupled between the replica transmitting circuit and the delay locked loop, the replica light source control path being configured to emulate the light source control path and generate a seventh clock signal to the delay locked loop of the time of flight sensor according to the fourth clock signal, such that a phase difference between the light source control signal and the seventh clock signal and a predetermined phase difference can be maintained the same during temperature, bias voltage or process variation; and
a light source for intermittently emitting the light pulses in accordance with the light source control signal.
11. The range finding system of claim 10 wherein the light emitting module is disposed on a second chip and the layout of the light source control paths is adjacent to the layout of the duplicate light source control paths.
12. The ranging system of claim 10, wherein the delay locked loop comprises:
a phase detector for generating phase difference information between one of the sixth clock signals and the seventh clock signal;
the charge pump is used for generating voltage information to the filter according to the phase difference information;
the filter is used for filtering the voltage information to generate a voltage-controlled delay line control signal; and
a voltage controlled delay line for passing the seventh clock signal through the voltage controlled delay line to generate the fifth clock signal, wherein the voltage controlled delay line causes a variable phase difference between the fifth clock signal and the seventh clock signal, and the variable phase difference is controlled by the voltage controlled delay line control signal.
13. The ranging system of claim 10, wherein the delay locked loop comprises:
a phase detector for generating phase difference information between one of the sixth clock signals and the seventh clock signal;
an accumulator for accumulating the phase difference information to generate accumulated phase information to a filter; the filter is used for filtering the accumulated phase information to generate a digital delay line control signal; and
a digital delay line for passing the seventh clock signal through the digital delay line to generate the fifth clock signal, and the digital delay line causes a variable phase difference between the fifth clock signal and the seventh clock signal, and the variable phase difference is controlled by the digital delay line control signal.
14. An electronic device, comprising:
a ranging system as claimed in any of claims 8 to 13; and
a processor coupled to the ranging system.
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