CN111953313A

CN111953313A - Fully unified PUF (physical unclonable function) and TRNG (TRNG) hardware security primitive circuit based on FPGAs (field programmable gate arrays)

Info

Publication number: CN111953313A
Application number: CN202010832092.5A
Authority: CN
Inventors: 梁华国; 王燕捷; 王鑫宇; 鲁迎春; 蒋翠云; 易茂祥; 黄正峰
Original assignee: Hefei University of Technology
Current assignee: Hefei University of Technology
Priority date: 2020-08-18
Filing date: 2020-08-18
Publication date: 2020-11-17
Anticipated expiration: 2040-08-18
Also published as: CN111953313B

Abstract

The invention discloses a fully unified PUF (physical unclonable function) and TRNG (true Ring trap network) hardware security primitive circuit based on FPGAs (field programmable Gate arrays), which comprises an entropy source circuit, a data selector, an entropy source collector and a deviation post-processing circuit, wherein the entropy source circuit comprises a first bit line, a second bit line and a first bit line; the entropy source circuit is composed of a dual-input NAND gate enabling signal unit and two single-input inverters; the offset post-processing circuit comprises n first-order offset post-processors, and any one first-order offset post-processor comprises three D triggers, a two-input AND gate, an inverter and two XOR gates. The invention can collect discarded entropy sources in the PUF and provide dynamic entropy for TRNG operation, thereby simultaneously designing two security primitives of TRNG and PUF on the edge equipment of the Internet of things, reducing the waste of entropy source circuits and improving the robustness of the equipment.

Description

Fully unified PUF (physical unclonable function) and TRNG (TRNG) hardware security primitive circuit based on FPGAs (field programmable gate arrays)

Technical Field

The invention belongs to the field of chip authentication and IP protection, and particularly relates to a fully unified PUF (physical unclonable function) and TRNG (true Ring trap network) hardware security primitive circuit based on FPGAs (field programmable gate arrays).

Background

With the continuous and deep development of social informatization, the information security problem is more and more emphasized by people. Keys that are considered to be permanently stored and unknown to an attacker are the core of traditional cryptography, however, many existing techniques can break traditional keys, making them insufficient to secure the hardware. To effectively address this security issue, PUFs and TRNGs have come into existence, which are the underlying security primitives that support the basis of trust in a mutually authenticated public key infrastructure for digital signature, certificate generation, and privacy protection. The PUF utilizes process deviation among chips during manufacturing to generate a key with enough safety, so that the uniqueness of the key among the chips can be ensured, and the stability of the key can be ensured under the environment of voltage/temperature fluctuation. Instead, the TRNG utilizes an entropy source such as white gaussian noise to generate a device-independent time-varying bit stream that can serve as a random number, initialization vector, and padding values in the security protocol. Therefore, TRNGs and PUFs, as emerging revolutionary hardware security primitives, can more effectively address security issues.

With the development of the internet of things, the data security problem in the authentication process of the internet of things equipment is also widely concerned, and Privacy Protection Mutual Authentication (PPMA) is an encryption authentication scheme aiming at the security of the internet of things equipment, and can remarkably reduce the possibility of secret leakage while repeatedly using challenge-response pairs. In the scheme, firstly, a server generates an R1 random number, and a secret key PUF1 is encrypted by utilizing R1 and then sent to an Internet of things chip; the chip of the Internet of things decrypts the information sent by the PUF1 according to the response generated by the chip of the Internet of things, generates a random number R2 through the TRNG of the chip of the Internet of things after obtaining the R1, re-encrypts the response of the PUF1 by using the R2 and the R1 and returns the information to the server; the server decrypts again with the key PUF1, can solve R1 and R2, and verifies the device by comparing whether the transmitted and received R1 are the same.

The protocol requires that two security primitives, namely TRNG and PUF, must be simultaneously provided on an edge device of the Internet of things, and PUF and TRNG designed at present are independent structures using a single entropy source. The PUF/TRNG needs to be subjected to independent design optimization and post-manufacturing calibration to generate a good result, and the action not only wastes a large amount of entropy source circuits, but also causes the circuit effect to be different along with environmental change; a greater challenge is also that if the PPMA protocol of the internet of things is used, it requires multiple overhead for device authentication.

Disclosure of Invention

The invention aims to solve the defects of the prior art, and provides a full-unified PUF and TRNG hardware security primitive circuit based on FPGAs, so that discarded entropy sources can be collected in the PUF, dynamic entropy is provided for TRNG operation, two security primitives of TRNG and PUF can be simultaneously designed on an Internet of things edge device, waste of the entropy source circuit is reduced, and the robustness of the device is improved.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention relates to a full-uniform PUF (physical unclonable function) and TRNG (true Ring trap network) hardware security primitive circuit based on FPGAs (field programmable Gate arrays), which is characterized by comprising n rows and m columns of entropy source circuits, n data selectors, n entropy source collectors and a deviation post-processing circuit;

any ith entropy source circuit is formed by a double-input NAND gate enabling signal unit and two single-input inverters, and i belongs to [1, nxm ];

the dual-input NAND gate enable signal unit comprises an enable input end EN, a data input end NAND and an output end NOUT;

any one single-input inverter comprises an input end ROIN and an output end ROUT;

the output end ROUT1_ i of the 1 st inverter in any ith entropy source circuit is connected with the input end ROIN2_ i of the 2 nd inverter; taking the input end ROUT2_ i of the 2 nd inverter as the output end of the ith entropy source circuit;

the output end ROUT2_ i of the 2 nd inverter is connected with the data input end NAND _ i of the NAND gate;

any jth data selector MUX _ j has m data inputs,

A data selection terminal and a data output terminal;

the m data input ends of any jth data selector are respectively connected with the output ends of the m entropy source circuits of the jth row; j ∈ [1, n ];

the kth data input terminal is according to

Input value of data selection terminal

Selecting the output end of the kth entropy source circuit and connecting the output end of the kth entropy source circuit to the jth input end of the entropy source collector; k is an element of [1, m ]]；

The offset post-processing circuit comprises n first-order offset post-processors, and any jth first-order offset post-processor comprises three D triggers, a two-input AND gate, an inverter and two XOR gates;

the input end btn of a first flip-flop FF0_ j of any jth first-order deviation post-processor is connected with the output end of a jth entropy source collector;

one input end S0 of a first exclusive-OR gate of the jth first-order deviation post-processor is connected with the output end of the jth entropy source collector, and the other input end is connected with the output end S1 of a first flip-flop FF0_ j;

one input end S2 of a two-input AND gate of the jth first-order deviation post-processor is connected with the output end of the first exclusive-OR gate, and the other input end is connected with the output end S1 of the FF0_ j;

the input terminal of a second flip-flop FF1_ j of the jth first-order-offset post-processor is connected with the output terminal of a second exclusive-OR gate; one input terminal S4 of the second xor gate is connected to the output terminal of the second flip-flop FF1_ j, and the other input terminal is connected to the output terminal S3 of the two-input and gate; the output terminal of the second flip-flop FF1_ j outputs a true random number TRNG;

the input end of the inverter of the jth first-order deviation post-processor is connected with the output end S3 of the two-input AND gate; the output end of the inverter is connected with the enabling end CE of the third flip-flop FF2_ j;

the input end of a third flip-flop FF2_ j of the jth first-order deviation post-processor is connected with the output end S1 of the first flip-flop FF0_ j; the output of the third flip-flop FF2_ j outputs a physical unclonable function PUF.

The working method of the fully unified PUF and TRNG hardware security primitive circuit is characterized by comprising the following steps of:

step 1, initializing enabling ends EN of all entropy source circuits to be 0, and enabling clock frequencies of n entropy source collectors and a deviation post-processing circuit to be f; defining the current clock period number as k;

step 2, enabling terminals EN of all entropy source circuits to be 1, and enabling the entropy source circuits to oscillate;

step 3, initializing k to 1;

step 4, judging whether the input value k of the data selection end of the jth data selector MUX _ j is less than or equal to m or not in the kth clock cycle; if yes, executing step 5-step 7; otherwise, executing step 8;

step 5, under the k clock period, the n data selectors select the output of the n entropy source circuits of the k column;

step 6, the entropy source collector samples n outputs of the kth column of the n data selectors and takes the n outputs as n sampling results of the kth clock period;

step 7, the deviation post-processing circuit extracts n sampling results of the kth clock cycle through a data bus, compares the n sampling results with n sampling results of k-1 clock cycles, if the corresponding jth sampling results are the same, the inverter provides an enable signal for a third flip-flop FF2_ j, and the third flip-flop FF2_ j outputs the jth sampling result as the jth bit of the physical unclonable function PUF; if the corresponding jth sampling result is different, the two input AND gates of the jth first-order deviation post-processor provide an enable signal for a second flip-flop FF1_ j, and the second flip-flop FF1_ j outputs the jth sampling result as a true random number TRN;

step 8, assigning k +1 to k, judging whether k is greater than m, and if so, executing step 3; otherwise, returning to the step 4.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention designs a fully unified PUF and TRNG hardware security primitive circuit based on FPGAs by reusing PUF entropy sources, and realizes the purpose of collecting discarded entropy sources in PUF to provide dynamic entropy for TRNG operation.

2. Although the FPGA design is used, the structure of the invention does not contain the unique structure of the FPGA circuit, and the design structures of all parts are mutually independent, so that the design scheme has universality and is also suitable for digital circuits except the FPGA.

3. Compared with the traditional independent design, the invention simultaneously realizes two different hardware security primitive circuits of PUF and TRNG by using the same entropy source circuit, thereby saving a large amount of area overhead

4. The deviation post-processing circuit can separate delay variation caused by random deviations such as process deviation, electromagnetic thermal noise and the like, solve the problem of statistical deviation in the random number extraction process, and reduce the error rate in the device key generation process, thereby ensuring the quality of PUF and TRNG.

Drawings

FIG. 1 is a diagram of a fully unified PUF and TRNG offset post-processing circuit of the present invention;

FIG. 2 is a diagram of an entropy source circuit of the present invention;

FIG. 3 is a diagram of the offset post-processing architecture of the present invention.

Detailed Description

In this embodiment, a Field Programmable Gate Array (FPGAs) -based fully unified Physical Unclonable Function (PUF) and True Random Number Generator (TRNG) hardware security primitive circuit is shown in fig. 1, and includes: n rows and m columns of entropy source circuits, n data selectors, n entropy source collectors and a deviation post-processing circuit; the composition of the structure and the corresponding connection are given in fig. 1.

As shown in fig. 2, any ith entropy source circuit is composed of a two-input nand gate enable signal unit and two single-input inverters, i belongs to [1, n × m ];

the output end ROUT1_ i of the 1 st inverter in any ith entropy source circuit is connected with the input end ROIN2_ i of the 2 nd inverter; the input end ROUT2_ i of the 2 nd inverter is used as the output end of the ith entropy source circuit;

any jth data selector MUX _ j has m data inputs,

A data selection terminal and a data output terminal;

the kth data input terminal is according to

Input value of data selection terminal

The offset post-processing circuit is shown in fig. 3, and comprises n first-order offset post-processors, wherein any jth first-order offset post-processor comprises three D flip-flops, a two-input and gate, an inverter and two exclusive or gates;

In this embodiment, a working method of a fully unified PUF and TRNG hardware security primitive circuit based on FPGAs is performed according to the following steps:

step 1, initializing enabling ends EN of all entropy source circuits to be 0, and enabling clock frequencies of n entropy source collectors and a deviation post-processing circuit to be f; defining the current clock period number as k; the enabling signal in the initialization step can be provided by a pulse or step signal generated by a microblaze soft core, a chipscope IP core or a clock and the like; and the clock frequency ranges from 50-400 Mhz.

Step 2, enabling ends EN of all entropy source circuits to be 1, and enabling the entropy source circuits to oscillate;

step 3, initializing k to 1;

step 7, the deviation post-processing circuit extracts n sampling results of the kth clock cycle through the data bus and compares the n sampling results with n sampling results of k-1 clock cycles, if the corresponding jth sampling results are the same, the inverter provides an enable signal for a third flip-flop FF2_ j, and the third flip-flop FF2_ j outputs the jth sampling result as the jth bit of the physical unclonable function PUF; if the corresponding jth sampling result is different, the two-input AND gate of the jth first-order deviation post-processor provides an enable signal for a second flip-flop FF1_ j, and the second flip-flop FF1_ j outputs the jth sampling result as a true random number TRN;

The method also comprises a randomness testing step after the steps:

the method comprises the steps of adopting an NIST test suite to carry out randomness test on random bit data generated by a structure, wherein the test comprises 15 items, the NIST test suite calculates a probability density curve of corresponding chi-square distribution for the random bit data aiming at each test item, the probability density curve is obtained by calculating the integral of the random bit data to infinity through solving statistics, the integral result P-value is used as a test result to be compared with a significant level alpha, if the integral result P-value is larger than alpha, the random bit data is considered to have randomness, and a typical alpha value interval is within [0.001, 0.01], wherein all results of TRN generated in the method have true randomness through the NIST test.

In order to further illustrate the positive effect of the scheme of the invention, the adopted Xilinx Virtex-6 series FPGA platform designs and realizes the provided hardware security primitive circuit, and the designed PUF has the bit error rate of 6.7 percent and has better uniqueness and stability.

Claims

1. A full-uniform PUF and TRNG hardware security primitive circuit based on FPGAs is characterized by comprising n rows and m columns of entropy source circuits, n data selectors, n entropy source collectors and a deviation post-processing circuit;

any jth data selector MUX _ j has m data inputs,

A data selection terminal and a data output terminal;

the kth data input terminal is according to

Input value of data selection terminal

2. The method of claim 1, wherein the steps of operating the fully unified PUF and TRNG hardware security primitive circuit are as follows:

step 3, initializing k to 1;