CN111951858B - Nor Flash programming method, modeling method and storage and calculation integrated chip - Google Patents
Nor Flash programming method, modeling method and storage and calculation integrated chip Download PDFInfo
- Publication number
- CN111951858B CN111951858B CN201910407917.6A CN201910407917A CN111951858B CN 111951858 B CN111951858 B CN 111951858B CN 201910407917 A CN201910407917 A CN 201910407917A CN 111951858 B CN111951858 B CN 111951858B
- Authority
- CN
- China
- Prior art keywords
- current
- flash memory
- memory unit
- voltage
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 93
- 238000003860 storage Methods 0.000 title claims abstract description 39
- 238000004364 calculation method Methods 0.000 title claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 30
- 238000012360 testing method Methods 0.000 claims description 39
- 230000001276 controlling effect Effects 0.000 description 21
- 238000004590 computer program Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000012545 processing Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007781 pre-processing Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 101100067427 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FUS3 gene Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
- G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Abstract
The invention provides a Nor Flash programming method, a modeling method and a storage and calculation integrated chip, wherein the Nor Flash programming method comprises the following steps: judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not; if yes, judging whether the current is larger than the target current or not; if the current is larger than the target current, obtaining a write-in voltage according to the current, the target current and a write-in voltage model, and controlling a programming circuit to apply the write-in voltage to the flash memory unit; if the current is smaller than the target current, obtaining an erase voltage according to the current, the target current and an erase voltage model, and controlling a programming circuit to apply the erase voltage to the flash memory unit, namely: the write voltage or the erase voltage is directly obtained by utilizing the write voltage model or the erase voltage model, and the repeated iteration process of updating and checking is omitted.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a Nor Flash programming method, a modeling method and a storage and calculation integrated chip based on Nor Flash.
Background
When the Nor Flash is used as a memory (only used for storing data), the data stored in each unit is generally 1-4 bits, so that the maximum number of states of each unit is 2-16, the programming method is relatively simple, and an update-and-verify (update-and-verify) iterative mode is adopted for programming to ensure that the final state is consistent with the target state, and the specific process is as follows: assuming that the initial state is a full deletion state (i.e. no electrons exist in the floating gate), reading the current after each writing (injecting electrons), if the current reading current is larger than the target current, continuing to write (injecting electrons), and then checking the relation between the reading current and the target current; on the contrary, if the current read current is smaller than the target current, the erasing operation (deleting electrons) is executed, and then the relation between the read current and the target current is checked; the above process is repeated until the sensing current is equal to the target current or the difference between the sensing current and the target current is less than the preset threshold.
In recent years, in order to solve the bottleneck of the traditional von neumann computing architecture, a Nor Flash-based memory Computing (CIM) chip has attracted much attention, and the basic idea is to directly perform logic computation by using a memory, thereby reducing the data transmission amount and transmission distance between the memory and a processor, reducing power consumption, and improving performance.
The existing programming method adopting an update-and-verify (update-and-verify) iterative manner is acceptable for a Nor Flash memory because the number of states of the memory is limited, but is not acceptable for a Nor Flash-based storage integrated chip because the weight data stored in the Nor Flash-based storage integrated chip usually requires 6-10 bits, even 12 bits, which means that the number of states of each unit is 64-1024, even 4048, and if the existing programming method is adopted for programming, the number of required target currents is large due to the large number of states of each unit, so that the number of update-verify iterations is increased greatly, further the complexity, time delay and power consumption overhead of programming are increased, and the actual requirements cannot be met.
Disclosure of Invention
In view of this, the present invention provides a Nor Flash programming method and apparatus, a modeling method, a Nor Flash based storage integrated chip, and a computer readable storage medium, which solve the problem that the existing programming method cannot meet the requirement of the Nor Flash based storage integrated chip, resulting in increased programming complexity, time delay, and power consumption overhead.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a Nor Flash programming method is provided, including:
controlling the reading circuit to read the current of a flash memory unit;
judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not;
if yes, judging whether the current is larger than the target current;
if the current is larger than the target current, obtaining a write-in voltage according to the current, the target current and a write-in voltage model, and controlling a programming circuit to apply the write-in voltage to the flash memory unit;
if the current is less than the target current, obtaining an erase voltage according to the current, the target current and an erase voltage model, and controlling a programming circuit to apply the erase voltage to the flash memory unit;
and if the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value, ending the Flash programming process.
Further, still include:
a target current of a flash memory cell, the write voltage model and the erase voltage model are obtained.
Further, still include:
acquiring erasure test data of the flash memory unit;
and carrying out polynomial fitting average on the erasing test data to obtain the erasing voltage model.
Further, still include:
acquiring write-in test data of a flash memory unit;
and carrying out polynomial fitting average on the write test data to obtain the write voltage model.
Further, still include:
the write voltage model is calibrated, and/or the erase voltage model is calibrated.
Further, calibrating the write voltage model includes:
obtaining a write voltage according to a current of a flash memory cell, a first target reference current and the write voltage model, and controlling a programming circuit to apply the write voltage to the flash memory cell;
controlling the reading circuit to read the current of the flash memory unit after the writing voltage is applied;
obtaining the offset value of the first target reference current and the current of the flash memory unit after the write-in voltage is applied;
calibrating the write-in voltage model according to the deviation value to obtain a calibrated write-in voltage model of the Flash memory unit, wherein the calibrated write-in voltage model is used in a Flash programming flow;
the difference between the current and the first target reference current is greater than a preset threshold, and the first target reference current is greater than zero and less than the current.
Further, calibrating the erase voltage model includes:
obtaining an erase voltage according to a current of a flash memory cell, a second target reference current and the erase voltage model, and controlling a programming circuit to apply the erase voltage to the flash memory cell;
controlling the reading circuit to read the current of the flash memory unit after the erasing voltage is applied;
obtaining the offset value of the second target reference current and the current of the flash memory unit after the erasing voltage is applied;
calibrating the erasing voltage model according to the deviation value to obtain a calibrated erasing voltage model of the Flash memory unit, wherein the calibrated erasing voltage model is used in a Flash programming flow;
the difference between the second target reference current and the current is greater than a preset threshold, and the second target reference current is less than the maximum outputtable current of the flash memory unit and greater than the current.
In a second aspect, a modeling method for Nor Flash programming is provided, including:
acquiring erasing test data and writing test data of a flash memory unit;
carrying out polynomial fitting averaging on the erasing test data to obtain the erasing voltage model;
and carrying out polynomial fitting average on the write test data to obtain the write voltage model.
In a third aspect, a Nor Flash programming device is provided, including:
the current reading control module controls the reading circuit to read the current of a flash memory unit;
the first judging module is used for judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not;
a second judging module, for judging whether the current is larger than the target current when the absolute value of the difference between the target current and the current of the flash memory unit is larger than a preset threshold;
a programming module for obtaining a write voltage according to the current, the target current and a write voltage model when the current is greater than the target current, and controlling a programming circuit to apply the write voltage to the flash memory cell;
an erase module for obtaining an erase voltage according to the current, the target current and an erase voltage model when the current is less than the target current, and controlling a programming circuit to apply the erase voltage to the flash memory cell;
and the programming ending module is used for ending the Flash programming process when the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value.
In a fourth aspect, a Nor Flash based storage and calculation integrated chip is provided, which includes: the controller realizes the steps of the Nor Flash programming method when programming control is carried out.
In a fifth aspect, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a controller, implements:
controlling the reading circuit to read the current of a flash memory unit;
judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not;
if yes, judging whether the current is larger than the target current;
if the current is larger than the target current, inputting the current and the target current into a write voltage model to obtain a write voltage, and controlling a programming circuit to apply the write voltage to the flash memory unit;
if the current is less than the target current, inputting the current and the target current into an erasing voltage model to obtain an erasing voltage, and controlling a programming circuit to apply the erasing voltage to the flash memory unit;
and if the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value, ending the Flash programming process.
The invention provides a Nor Flash programming method and device, a modeling method, a storage and calculation integrated chip based on Nor Flash and a computer readable storage medium, wherein the method comprises the following steps: controlling the reading circuit to read the current of a flash memory unit; judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not; if yes, judging whether the current is larger than the target current; if the current is larger than the target current, obtaining a write-in voltage according to the current, the target current and a write-in voltage model, and controlling a programming circuit to apply the write-in voltage to the flash memory unit; if the current is less than the target current, obtaining an erase voltage according to the current, the target current and an erase voltage model, and controlling a programming circuit to apply the erase voltage to the flash memory unit; if the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value, ending the Flash programming process, namely: the write voltage model or the erase voltage model is used for directly acquiring the write voltage or the erase voltage, so that the repeated iteration process of updating and checking is omitted, the problem that the existing programming method cannot meet the requirement of a Nor Flash-based storage integrated chip is solved, the iteration times of updating and checking are reduced, the programming complexity, time delay and power consumption overhead are further reduced, and the actual requirement is met.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. In the drawings:
FIG. 1 is a circuit diagram of a Nor Flash-based computing integrated chip according to an embodiment of the present invention;
FIG. 2 is a first flowchart illustrating a Nor Flash programming method according to an embodiment of the present invention;
FIG. 3 is a second flowchart illustrating a Nor Flash programming method according to an embodiment of the present invention;
FIG. 4 is a third flowchart illustrating a Nor Flash programming method in an embodiment of the present invention;
FIG. 5 is a fourth flowchart illustrating a modeling method for Nor Flash programming according to an embodiment of the present invention;
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
It should be noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the above-described drawings, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
The existing programming method adopting an update-verify (update-and-verify) iteration mode is not acceptable for a Nor Flash-based storage integrated chip, because the weight data stored in the Nor Flash-based storage integrated chip is generally required to be 6-10 bits, even 12 bits, which means that the number of states of each unit is 64-1024, even 4048, if the existing programming method is adopted for programming, the number of states of each unit is large, and the number of required target currents is large, so that the number of update-verify iterations is increased greatly, the complexity, the time delay and the power consumption expense of programming are increased, and the actual requirements cannot be met.
In order to solve the technical problems in the prior art, embodiments of the present invention provide a Nor Flash programming method, which can directly obtain a write voltage or an erase voltage by using a write voltage model or an erase voltage model, thereby omitting an update-check iteration process, solving the problem that the existing programming method cannot meet the requirement of a Nor Flash-based storage integrated chip, reducing the update-check iteration times, further reducing the programming complexity, time delay and power consumption overhead, and meeting the actual requirement.
It is worth to be noted that, according to the current-current characteristic of the floating gate transistor, the magnitude of the write voltage or the erase voltage applied to the flash memory cell is not linear with the decrease or increase of the read current, after the applicant has conducted a lot of research and test analysis, the applicant finds that, for the same type of flash memory cell, an initial read current state is given, and after a write voltage or an erase voltage is applied, the final read current and the write voltage or the erase voltage are changed in a certain rule, based on the above significant finding, the applicant improves the existing update-verification iteration mode, and directly obtains the required write voltage or the erase voltage by adopting a write voltage model or an erase voltage model according to the current read current and the target read current, through practical verification, the number of update-verification iterations is greatly reduced, and the target state can be obtained only by one-time processing under ideal conditions, the programming complexity, the time delay and the power consumption overhead are greatly reduced, and the actual requirements are met.
FIG. 1 is a circuit diagram of a NorFlash-based computing integrated chip in an embodiment of the present invention. As shown in fig. 1, the NorFlash-based computing integrated chip includes: an input register 1 for registering data to be processed, a DAC2 for converting the data to be processed registered by the input register 1 into analog data, a flash memory cell array 3 for performing calculation (such as matrix multiplication) on the analog data in a calculation mode or storing the data in a storage mode, an analog processing module 4 for preprocessing the calculation result of the flash memory cell array 3, an ADC5 for converting the processing result of the analog processing module 4 into digital data, an output register for registering and outputting the digital data, a programming circuit 7 for programming the flash memory cell array 3, a reading circuit 9 for reading the data (also referred to as weights) stored by each flash memory cell in the flash memory cell array, and a controller 8 for controlling the operation of the programming circuit 7 and the reading circuit 9.
In an optional embodiment, the NorFlash-based computing integrated chip may further include: a row-column decoder. The row-column decoder is connected to the flash memory cell array 3 and the controller 8, and is configured to perform row-column decoding on the flash memory cell array 3 under the control of the controller 8.
The flash memory cell array 3 is composed of a plurality of flash memory cells with adjustable threshold voltages. The threshold voltage of the flash memory units is adjustable, namely the transconductance of each flash memory unit is adjustable, which is equivalent to that each flash memory unit stores variable simulation weight data, a plurality of flash memory units in the flash memory unit array form a simulation data array, each data in the array can be freely adjusted, according to ohm's law and kirchhoff's law, the output current of each flash memory unit is equal to the input simulation data multiplied by the simulation weight data, the output currents of the plurality of flash memory units are equal to the sum of the output currents of each flash memory unit, and then various calculations are directly realized in the flash memory unit array.
The flash memory cell can be implemented by a floating gate transistor.
The input register 1 is connected with an input interface of the integrated storage chip, the input interface is connected with an external element, such as an external microprocessor, and receives data sent by the external microprocessor, and the output register 6 is connected with an output interface of the integrated storage chip.
The programming circuit 7 is connected to the source, the gate and/or the substrate of each flash memory cell in the flash memory cell array, and is used for regulating and controlling the threshold voltage of the flash memory cell. The programming circuit 7 may include: a voltage generating circuit for generating a write voltage or an erase voltage, and a voltage control circuit for applying the write voltage to a selected flash memory cell.
Specifically, the programming circuit applies a high voltage (i.e., a write voltage) to the source of the flash memory cell using a hot electron injection effect to accelerate channel electrons to a high speed to increase the threshold voltage of the flash memory cell, thereby achieving writing.
The programming circuit uses tunneling effect to apply a high voltage (i.e., an erase voltage) to the gate or substrate of the flash memory cell, thereby reducing the threshold voltage of the flash memory cell and enabling erase.
The controller 8 can control the working mode of the flash memory cell array 3, including a calculation mode and a storage mode, when in the calculation mode, the controller 8 controls the programming circuit 7 to program the flash memory cell array, namely, the threshold voltage of each flash memory cell is adjusted, the data to be processed is input into the flash memory cell array 3 after being registered and subjected to digital-to-analog conversion to realize calculation, when in the storage mode, no data is input through the input register, and the controller controls the programming circuit 7 to program the flash memory cell array according to the data to be stored, namely, the threshold voltage of each flash memory cell is adjusted to realize data storage.
In addition, a controller 8 connects the programming circuit and the reading circuit 9.
The controller 8 is configured to execute the Nor Flash programming method provided by the embodiment of the present invention, referring to fig. 2, the Nor Flash programming method may include the following steps:
step S10: the reading circuit is controlled to read the current of a flash memory unit.
The flash memory cell refers to a flash memory cell to be programmed.
Step S20: and judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value.
The preset threshold value can be any value within 0.01nA to 5nA, such as 1nA or 2 nA.
If yes, go to step S30; if not, go to step S80.
The preset threshold, the address of the flash memory unit and the target current thereof are included in the control data received by the controller.
Step S30: determining whether the current is greater than the target current.
If yes, go to step S40; if not, go to step S60.
Generally, the more electrons in the floating gate, the smaller the read current.
Step S40: and obtaining a write-in voltage according to the current, the target current and a write-in voltage model.
The write voltage model (also referred to as a write voltage function or a write voltage empirical equation) can be obtained by analyzing write test data, and reflects the relationship between the current, the target current and the write voltage.
It is worth mentioning that the process of obtaining the write voltage model from the write test data may be implemented in a controller or in a server (e.g. a smart phone, a tablet electronic device, a portable computer, a desktop computer, a Personal Digital Assistant (PDA), etc.), which may include a compiling software, such as MATLAB. When the computational power of the controller is sufficient, the process of obtaining the write voltage model according to the write test data may be implemented in the controller, and when the computational power of the controller is limited, in order to reduce the chip area and reduce the workload of the controller, the write voltage model may be obtained in the server according to the write test data, and the controller directly obtains the write voltage model already established in the server to perform specific application, see step S1 in fig. 3.
In an alternative embodiment, the current and target currents may be input into the write voltage model to obtain the write voltage.
In another alternative embodiment, in order to increase the speed, a lookup table of the current and target current-write voltage correspondence may be obtained according to the write model, and then, according to the current and target currents, the write voltage may be obtained through the lookup table without temporarily inputting the current and target currents into the model to obtain the write voltage, thereby effectively increasing the speed.
Step S50: the control program circuit applies the write voltage to the flash memory cell and then returns to step S10.
Specifically, the programming circuit generates the write voltage according to a control command of the controller and applies the write voltage to the source of the flash memory unit, the drain of the flash memory unit applies a ground voltage or a low voltage, the write voltage accelerates channel electrons to a high speed, electrons are injected into the flash memory unit by utilizing a hot electron injection effect, the threshold voltage of the flash memory unit is increased, and writing is realized.
Step S60: and inputting the current and the target current into an erasing voltage model to obtain an erasing voltage.
The erase voltage model (also called as an erase voltage function or an erase voltage empirical equation) can be obtained by analyzing erase test data, and reflects the relationship between the current, the target current and the erase voltage.
It is worth mentioning that the process of obtaining the erase voltage model from the erase test data may be implemented in the controller or in a server (e.g. a smart phone, a tablet electronic device, a portable computer, a desktop computer, a Personal Digital Assistant (PDA), etc.). When the calculation power of the controller is sufficient, the process of obtaining the erasing voltage model according to the erasing test data can be realized in the controller, when the calculation power of the controller is limited, in order to reduce the chip area and reduce the workload of the controller, the erasing voltage model can be obtained in the server according to the erasing test data, and the controller directly obtains the erasing voltage model which is established in the server to carry out specific application.
In an alternative embodiment, the current and target currents may be input into the erase voltage model to obtain the erase voltage.
In another optional embodiment, in order to increase the speed, a lookup table of a current and target current-erase voltage correspondence may be obtained according to the erase model, and then, according to the current and target currents, the erase voltage may be obtained through the lookup table without temporarily inputting the current and target currents into the model to obtain the erase voltage, thereby effectively increasing the speed.
Step S70: the control program circuit applies the erase voltage to the flash memory cell and then returns to step S10.
Specifically, the programming circuit generates the erasing voltage according to a control instruction of the controller and applies the erasing voltage to a grid electrode or a substrate of the flash memory unit, and electrons in the flash memory unit are reduced by utilizing a tunneling effect, so that the threshold voltage of the flash memory unit is reduced, and the erasing is realized.
Step S80: and finishing the Flash programming flow.
When the current of the Flash memory unit is equal to the target current or the difference between the current and the target current is within a preset range, the Flash memory unit does not need to be programmed, and at the moment, the Flash programming process is ended.
It will be understood by those skilled in the art that both the write and erase operations are processes of programming a flash memory cell, and that for the purpose of distinguishing between the act of adding electrons or the act of reducing electrons, the write operation is used to denote the act of adding electrons and the erase operation is used to denote the act of reducing electrons.
According to the technical scheme, the Nor Flash programming method provided by the embodiment of the invention can utilize an empirical equation, greatly reduce the repeated iteration process of updating-checking, and solve the problem that the existing programming method cannot meet the requirement of a Nor Flash-based storage integrated chip, thereby reducing the programming complexity, time delay and power consumption overhead and meeting the actual requirement.
In order to further reduce the programming complexity, the time delay, and the power consumption overhead, an embodiment of the present invention further provides a Nor Flash programming method, referring to fig. 4, where the Nor Flash programming method includes the Nor Flash programming method shown in fig. 3, and may further include:
step S2: the write voltage model is calibrated, and/or the erase voltage model is calibrated.
The step of calibrating the write voltage model may specifically include the following steps:
step 1: and controlling a reading circuit to read the current of the flash memory unit to be programmed, and obtaining a writing voltage according to the current, the first target reference current and the writing voltage model.
Step 2: the control program circuit applies the write voltage to the flash memory cell.
And step 3: controlling the reading circuit to read the current of the flash memory unit after the writing voltage is applied;
and 4, step 4: obtaining the offset value of the first target reference current and the current of the flash memory unit after the write voltage is applied.
And 5: calibrating the write-in voltage model according to the offset value to obtain a calibrated write-in voltage model of the flash memory unit, wherein the calibrated write-in voltage model is used in the process of programming the flash memory unit by the method;
wherein, the first target reference current is a randomly selected current value, and the following conditions are satisfied: the difference between the current and the first target reference current is greater than a preset threshold, and the first target reference current is greater than zero and less than the current.
Since the offset value is generally linear, the offset value is added to or subtracted from the model.
In addition, the step of calibrating the erase voltage model may specifically include the following:
step 1': and controlling the reading circuit to read the current of the flash memory unit to be programmed, and obtaining the erasing voltage according to the current, the second target reference current and the erasing voltage model.
Step 2': the control program circuit applies the erase voltage to the flash memory cell.
Step 3': and controlling the reading circuit to read the current of the flash memory unit after the erasing voltage is applied.
Step 4': obtaining the offset value of the second target reference current and the current of the flash memory unit after the erasing voltage is applied;
step 5': calibrating the erasing voltage model according to the deviation value to obtain a calibrated erasing voltage model of the Flash memory unit, wherein the calibrated erasing voltage model is used in a Flash programming flow;
the difference between the second target reference current and the current is greater than a preset threshold, and the second target reference current is less than the maximum outputtable current of the flash memory unit and greater than the current.
Through the technical scheme, the process parameter deviation exists in different flash memory units, so that a certain offset may exist between a write voltage model and an erase voltage model of different flash memory units, when programming a certain flash memory cell by using a write voltage model and an erase voltage model, the write voltage model and the erase voltage model are applied to the flash memory cell for trial programming, calibrating the write voltage model and the erase voltage model according to an offset value between the target current and the actually read current to obtain a write voltage model and an erase voltage model suitable for the flash memory cell, and then, the calibrated write-in voltage model and erase voltage model which are suitable for the Flash memory are used for Flash programming, so that the iteration times of updating-checking can be further reduced, and the programming complexity, time delay and power consumption overhead can be further reduced.
In an optional embodiment, the Nor Flash programming method may further include: the steps of obtaining the erase test data and the write test data of the flash memory cell and obtaining the erase voltage model and the write voltage model, which have been mentioned above, may be implemented in the controller, or may be implemented in the server, and the specific contents included in the steps are shown in fig. 5:
step S100: and acquiring erasing test data and writing test data of the flash memory unit.
The write test data refers to a series of test data obtained in a test performed to obtain write voltages required for different target states through a test based on different states of an actual flash memory cell.
The erase test data is a series of test data obtained in an experiment performed to obtain erase voltages required for different target states through testing based on different states of an actual flash memory cell.
Step S200: and carrying out polynomial fitting average on the erasing test data to obtain the erasing voltage model.
Step S300: and carrying out polynomial fitting average on the write test data to obtain the write voltage model.
The erasing test data and the writing test data are real data obtained by actual tests meeting certain precision requirements.
Of course, the step of modeling may also include: the process of preprocessing the erasing test data and the writing test data of the flash memory unit comprises the process of eliminating the dead data and the abnormal data.
Specifically, for example, the expression of the write voltage model may be:
v＝ax3+bx2+cx+d，
where v denotes a write voltage to be acquired,
a. b, c and d are coefficients obtained when polynomial fitting is carried out.
Similarly, the expression of the erase voltage model may be:
v1＝a1x1 3+b1x1 2+c1x1+d1，
wherein v is1Which represents the erase voltage to be obtained,
a1、b1、c1、d1are coefficients obtained when performing polynomial fitting.
It can be understood by those skilled in the art that the Nor Flash programming method provided in the embodiments of the present invention can also be directly executed on a server, and in the execution process, when it is necessary to read the current of a certain Flash memory cell or apply the obtained write voltage or erase voltage to a certain Flash memory cell, it is only necessary to send a read command to a computer-integrated chip or a nonvolatile memory (e.g., a Flash memory), and to read the address of the Flash memory cell, the program command and the write voltage, and the address of the Flash memory cell to be programmed, the erase command and the erase voltage, and the address of the Flash memory cell to be erased, and then to receive data fed back by the computer-integrated chip or the nonvolatile memory (e.g., the Flash memory).
Based on the same inventive concept, the embodiment of the present application further provides a Flash programming device, which can be used to implement the methods described in the above embodiments, as described in the following embodiments. Because the principle of solving the problems of the Flash programming device is similar to that of the method, the implementation of the Flash programming device can refer to the implementation of the method, and repeated parts are not described again. As used hereinafter, the term "unit" or "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
The Flash programming device comprises: the device comprises a current reading control module, a first judgment module, a second judgment module, a programming module, an erasing module and a programming ending module.
The current reading control module controls the reading circuit to read the current of a flash memory unit.
The first judging module judges whether the absolute value of the difference value of the target current and the current of the flash memory unit is larger than a preset threshold value.
The second judging module judges whether the current is larger than the target current or not when the absolute value of the difference value between the target current and the current of the flash memory unit is larger than a preset threshold value.
When the current is larger than the target current, the programming module obtains a writing voltage according to the current, the target current and a writing voltage model and controls a programming circuit to apply the writing voltage to the flash memory unit.
The erasing module obtains an erasing voltage according to the current, the target current and an erasing voltage model when the current is smaller than the target current, and controls a programming circuit to apply the erasing voltage to the flash memory unit.
And the programming ending module ends the Flash programming process when the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value.
Embodiments of the present invention also provide an electronic device, which may include the NorFlash-based storage integrated chip or the nonvolatile storage memory (e.g., FLASH memory) described above, and in particular, the electronic device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a controller to perform the Nor Flash programming method. The computer program may be downloaded and installed from a network, and/or installed from a removable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (9)
1. A Nor Flash programming method is characterized by comprising the following steps:
controlling the reading circuit to read the current of a flash memory unit;
judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not;
if yes, judging whether the current is larger than the target current or not;
if the current is larger than the target current, obtaining a write-in voltage according to the current, the target current and a write-in voltage model, and controlling a programming circuit to apply the write-in voltage to the flash memory unit;
if the current is smaller than the target current, obtaining an erasing voltage according to the current, the target current and an erasing voltage model, and controlling a programming circuit to apply the erasing voltage to the flash memory unit;
and if the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value, ending the Flash programming process.
2. The Nor Flash programming method of claim 1, further comprising:
and acquiring a target current, the writing voltage model and the erasing voltage model of a flash memory unit.
3. The Nor Flash programming method of claim 1, further comprising:
acquiring erasure test data of the flash memory unit;
and carrying out polynomial fitting average on the erasing test data to obtain the erasing voltage model.
4. The Nor Flash programming method of claim 1, further comprising:
acquiring write-in test data of a flash memory unit;
and carrying out polynomial fitting average on the write-in test data to obtain the write-in voltage model.
5. The Nor Flash programming method of any of claims 1 to 4, further comprising:
the write voltage model is calibrated, and/or the erase voltage model is calibrated.
6. The Nor Flash programming method of claim 5, wherein calibrating the write voltage model comprises:
obtaining a write-in voltage according to the current of a flash memory unit, a first target reference current and the write-in voltage model, and controlling a programming circuit to apply the write-in voltage to the flash memory unit;
controlling the reading circuit to read the current of the flash memory unit after the writing voltage is applied;
obtaining the offset value of the first target reference current and the current of the flash memory unit after the write-in voltage is applied;
calibrating the write-in voltage model according to the deviation value to obtain a calibrated write-in voltage model of the Flash memory unit, wherein the calibrated write-in voltage model is used in a Flash programming flow;
wherein a difference between the present current and the first target reference current is greater than a preset threshold, and the first target reference current is greater than zero and less than the present current.
7. The Nor Flash programming method of claim 5, wherein calibrating the erase voltage model comprises:
obtaining an erasing voltage according to the current of a flash memory unit, the second target reference current and the erasing voltage model, and controlling a programming circuit to apply the erasing voltage to the flash memory unit;
controlling the reading circuit to read the current of the flash memory unit after the erasing voltage is applied;
obtaining the offset value of the second target reference current and the current of the flash memory unit after the erasing voltage is applied;
calibrating the erasing voltage model according to the deviation value to obtain a calibrated erasing voltage model of the Flash memory unit, wherein the calibrated erasing voltage model is used in a Flash programming flow;
the difference between the second target reference current and the current is greater than a preset threshold, and the second target reference current is less than the maximum outputable current of the flash memory unit and greater than the current.
8. A Nor Flash programming device, comprising:
the current reading control module controls the reading circuit to read the current of a flash memory unit;
the first judgment module is used for judging whether the absolute value of the difference value between the target current and the current of the flash memory unit is greater than a preset threshold value or not;
the second judging module is used for judging whether the current is larger than the target current or not when the absolute value of the difference value between the target current of the flash memory unit and the current is larger than a preset threshold value;
the programming module is used for obtaining a writing voltage according to the current, the target current and a writing voltage model when the current is larger than the target current, and controlling a programming circuit to apply the writing voltage to the flash memory unit;
the erasing module is used for obtaining erasing voltage according to the current, the target current and an erasing voltage model when the current is smaller than the target current, and controlling a programming circuit to apply the erasing voltage to the flash memory unit;
and the programming ending module is used for ending the Flash programming process when the absolute value of the difference value between the target current and the current of the Flash memory unit is less than or equal to a preset threshold value.
9. A Nor Flash-based storage and calculation integrated chip is characterized by comprising: the Flash memory comprises a Flash memory cell array, a programming circuit, a reading circuit and a controller, wherein the controller realizes the steps of the Nor Flash programming method according to any one of claims 1 to 7 when in programming control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910407917.6A CN111951858B (en) | 2019-05-16 | 2019-05-16 | Nor Flash programming method, modeling method and storage and calculation integrated chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910407917.6A CN111951858B (en) | 2019-05-16 | 2019-05-16 | Nor Flash programming method, modeling method and storage and calculation integrated chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111951858A CN111951858A (en) | 2020-11-17 |
| CN111951858B true CN111951858B (en) | 2021-09-17 |
Family
ID=73336743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910407917.6A Active CN111951858B (en) | 2019-05-16 | 2019-05-16 | Nor Flash programming method, modeling method and storage and calculation integrated chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111951858B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100806792B1 (en) * | 2006-09-01 | 2008-02-27 | 동부일렉트로닉스 주식회사 | Method for measuring threshold voltage of sonos flash device |
| CN104766629B (en) * | 2014-01-07 | 2018-09-14 | 北京兆易创新科技股份有限公司 | Enhance the method for NAND type FLASH reliabilities |
| CN108847268B (en) * | 2018-06-13 | 2020-10-16 | 上海华力微电子有限公司 | Threshold voltage adjusting method and system of storage unit model |
-
2019
- 2019-05-16 CN CN201910407917.6A patent/CN111951858B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111951858A (en) | 2020-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101242293B1 (en) | Nonvolatile memory control method and semiconductor device | |
| CN106547515B (en) | Method and processing device for performing arithmetic operations | |
| CN109817267B (en) | Deep learning-based flash memory life prediction method and system and computer-readable access medium | |
| CN111950718B (en) | Method for realizing progressive CNN operation by using storage and computation integrated chip | |
| JP6991983B2 (en) | How and systems to train machine learning systems | |
| JP2018537788A5 (en) | ||
| JP6935356B2 (en) | Semiconductor devices, information processing systems, and information processing methods | |
| BR112020024353B1 (en) | METHOD PERFORMED BY DATA PROCESSING APPARATUS, NON-TRAINER COMPUTER STORAGE SYSTEM AND MEDIUM | |
| CN109214193B (en) | Data encryption and machine learning model training method and device and electronic equipment | |
| US20190050721A1 (en) | Pulse-width modulated multiplier | |
| US20190065962A1 (en) | Systems And Methods For Determining Circuit-Level Effects On Classifier Accuracy | |
| US9620227B1 (en) | Characterizing and operating a non-volatile memory device | |
| US20170103154A1 (en) | Circuit design method and simulation method based on process variation caused by aging | |
| US10217515B2 (en) | Programming memory devices | |
| CN113344170A (en) | Neural network weight matrix adjusting method, writing control method and related device | |
| US20190026629A1 (en) | Systems and Methods for Overshoot Compensation | |
| CN106030453A (en) | Methods and apparatus to support dynamic adjustment of graphics processing unit frequency | |
| CN103778970A (en) | Working performance simulation method and device of flash memory | |
| CN111951858B (en) | Nor Flash programming method, modeling method and storage and calculation integrated chip | |
| CN111243654A (en) | Flash memory chip and calibration method and device thereof | |
| US7962317B1 (en) | Analytic linearization for system design | |
| CN112861239A (en) | Method, system, device and storage medium for initially balancing ground stress of numerical model | |
| CN111813339A (en) | Data writing method and device of Flash Nand Flash, electronic equipment and storage medium | |
| US20230305734A1 (en) | Platform for non-volatile memory storage devices simulation | |
| CN105095545A (en) | Work area based device buffering in circuit simulation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 213-175, 2nd Floor, Building 1, No. 180 Kecheng Street, Qiaosi Street, Linping District, Hangzhou City, Zhejiang Province, 311100 Patentee after: Hangzhou Zhicun Computing Technology Co.,Ltd. Country or region after: China Address before: 1707 shining building, 35 Xueyuan Road, Haidian District, Beijing 100083 Patentee before: BEIJING WITINMEM TECHNOLOGY Co.,Ltd. Country or region before: China |
|
| CP03 | Change of name, title or address |