CN111949581B

CN111949581B - Command-based on-chip termination for high speed NAND interfaces

Info

Publication number: CN111949581B
Application number: CN202010806431.2A
Authority: CN
Inventors: 陈沈雄; 范科伟; 周官水
Original assignee: Shenzhen Anjili New Technology Co ltd
Current assignee: Shenzhen Anjilite New Technology Co ltd
Priority date: 2020-08-12
Filing date: 2020-08-12
Publication date: 2022-04-08
Anticipated expiration: 2040-08-12
Also published as: CN111949581A

Abstract

Systems, apparatuses, and methods are provided for a multi-drop, multi-load NAND interface topology in which multiple NAND flash memory devices share a data bus with a NAND controller. A method for controlling on-die termination (ODT) in a nonvolatile memory device may include: a chip enable signal is received from the controller on a chip enable signal line, an on-die termination (ODT) command is received from the controller on a data bus when the chip enable signal is on, the on-die termination command is decoded and a termination Resistor (RTT) setting in the ODT command is applied to a selected nonvolatile memory cell in the nonvolatile memory device, thereby enabling ODT of the selected nonvolatile memory cell.

Description

Command-based on-chip termination for high speed NAND interfaces

Technical Field

The present disclosure relates to NAND flash memory interfaces, and more particularly to a multi-drop, multi-load NAND interface topology in which multiple NAND flash memory devices share a data bus with a NAND controller.

Background

The advent of Solid State Disks (SSDs), which have higher speed and latency performance than traditional hard disks, has pushed the development of modern computing systems to some extent. Unlike hard disks that rely on magnetism to store data, solid state drives use NAND flash memory devices to enable data storage. NAND flash memory devices are a family of integrated circuits manufactured by advanced processes and packaging techniques that allow vertical stacking of multiple layers of memory cells into smaller packages, thereby achieving high storage capacity.

A typical SSD consists of a controller and a plurality of NAND flash memory devices that are placed on and connected through a Printed Circuit Board (PCB) and are of standard size for various consumer or enterprise usage models. The interface between the controller and the NAND flash devices is grouped into channels, with modern controllers typically having 4, 8, or 16 NAND channels. To achieve higher storage capacity, SSDs need to integrate more NAND flash devices into the PCB, resulting in multiple NAND devices sharing a channel. As a result, for the design of high density solid state drives, a multi-load or multi-drop PCB topology is typically employed.

However, the use of multi-load PCB topologies also presents new challenges for high-speed NAND flash interfaces with signal integrity and timing performance degradation. With multiple NAND flash devices on a bus, negative reflections from the capacitive load of one NAND flash device propagate through the PCB transmission line, causing signal attenuation to other NAND flash devices sharing the bus. The more NAND devices installed on the bus, the more severe the reflection problem becomes and the greater the likelihood of degradation of signal integrity. As a result, the speed of the NAND interface must be reduced to accommodate the degradation in signal integrity, resulting in performance degradation. Although the nature of signal reflection and decay in a NAND interface is similar to that of a multi-column DRAM interface, NAND is more severe because the capacitive loading per pin of a high density NAND package is typically several times that of a DRAM package, thus making negative reflections more pronounced.

To address the signal integrity challenges with multi-load PCB topologies, NAND interfaces have introduced on-die termination (ODT) technology that integrates resistive termination into the integrated circuit to help suppress reflections of capacitive loads. While ODT technology has proven effective, it is equally important to enable and set ODT values on each individual NAND flash memory device of a data bus. For example, on a multi-load NAND bus, it is generally more effective to set a low resistance value to ODT for those non-target NAND flash memory devices that do not process commands or perform data transfers.

In the latest open NAND flash interface specification (ONFI) revision 4.1, a non-targeted ODT function is supported by a two-step method, an ODT configuration step and an ODT enable step. However, in the prior art, this non-targeted ODT technology has many drawbacks in terms of controller and system implementation. In addition, the level of support for such non-targeted ODT technology in mainstream NAND flash memory devices and controllers also lags behind. Accordingly, there is a need in the art to develop ODT techniques that are more efficient and easy to implement.

Disclosure of Invention

The disclosed subject matter relates to systems, methods, and apparatus that provide command-based non-targeted ODT techniques for memory systems. Command-based non-targeted ODT techniques may be a way to save power consumption, may simplify configuration, and may enable non-targeted ODT at a system level. In various embodiments, the same command may be used to set the target and non-target ODT configurations. Embodiments according to the present disclosure do not require multiple chip enable signals to be driven simultaneously. It also does not require new complex controller circuit implementations to support various chip enable and ODT configurations for multiple PCB topologies. In some embodiments, the techniques may be implemented at the firmware level without modifying existing controller hardware.

In an exemplary embodiment, a method for controlling on-die termination in a non-volatile memory device is provided. The method can comprise the following steps: receiving a chip enable signal from a controller ON a chip enable signal line, receiving an ON-die termination (ODT) command from the controller ON a data bus when the chip enable signal is ON (ON), decoding the ON-die termination command and applying a termination Resistor (RTT) setting in the ODT command to a selected nonvolatile memory cell in a nonvolatile memory device, enabling the selected nonvolatile memory cell to ODT.

In another exemplary embodiment, a non-volatile storage system is provided. The non-volatile memory system may include a controller and a non-volatile memory device connected to the controller through at least one chip enable signal line and a data bus. The non-volatile memory device may be configured to receive a chip enable signal from a controller on a chip enable signal line, receive an on-die termination (ODT) command from the controller on a data bus when the chip enable signal is on, decode the on-die termination command and apply a termination Resistor (RTT) setting in the ODT command to a selected non-volatile memory cell in the non-volatile memory device to enable ODT for the selected non-volatile memory cell.

Brief description of the drawings

FIG. 1A schematically illustrates a NAND memory system in one embodiment according to the present disclosure.

FIG. 1B schematically shows a NAND memory system in another embodiment according to the present disclosure.

Fig. 2 schematically illustrates a command from a NAND controller to enable and turn off non-target ODT in one embodiment according to the disclosure.

Fig. 3 schematically illustrates an ODT command from a NAND controller for switching a target in one embodiment according to the present disclosure.

Fig. 4 is a flow diagram of a process for controlling non-target on-die termination (ODT) in one embodiment according to the present disclosure.

Detailed Description

Specific embodiments according to the present application will now be described in detail with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals for consistency.

The present disclosure provides systems and methods for configuring non-target ODT for a non-volatile memory device based memory system. As used herein, a non-volatile memory device may be a computer storage device that may retain stored information after being powered off, and may retrieve stored information after being powered back on (off and back on). Non-volatile storage may include floppy disks, hard drives, magnetic disks, optical disks, NAND flash memory, NOR flash memory, Magnetoresistive Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PCRAM), Nano-RAM, and so forth. In the description, NAND flash memory may be used as an example of demonstrating ODT technology. However, other types of non-volatile storage devices may be utilized to implement the techniques in accordance with various embodiments of the present disclosure.

FIG. 1A schematically illustrates an exemplary NAND memory system 100A, according to one embodiment. The NAND memory system 100A can include a NAND controller 102A and a plurality of NAND devices 104A.1 and 104 A.2. The NAND controller 102A may be connected to the NAND devices 104A.1 and 104A.2 via a NAND interface, which may include multiple signal lines. Some signal lines of the NAND interface may not require ODT, such as Chip Enable (CE) 108A.1, CE 108A.2, CE 108A.3, and CE 108 A.4. CE 108A.1 and CE 108A.2 can be connected between NAND controller 102A and a first NAND device 104 A.1. CE 108A.3 and CE 108A.4 can be connected between NAND controller 102A and a second NAND device 104 A.2. Some signal lines of the NAND interface may require ODT, for example, each signal line of a data bus, a differential pair of Strobe (Strobe) signals (DQS _ P/DQS _ N) and a differential pair of Read Enable (Read Enable) signals (RE _ P/RE _ N), and a typical data bus may be 8 bits or 16 bits with 8 signal lines (which may be referred to as DQ0 through DQ7, respectively) or 16 signal lines (which may be referred to as DQ0 through DQ15, respectively). A single signal line 110A may be illustrated as representative of demonstrating ODT techniques. The single signal line 110A may be a data bus line, a data signal line of DQS, RE, or any signal line requiring ODT.

As shown in FIG. 1A, each NAND memory device 104A.1 and 104A.2 can include a plurality of memory cells. For example, the NAND memory device 104A.1 can include two memory cells: 106a.1 and 106a.2, the NAND memory device 104a.2 may include two memory cells: 106a.3 and 106 a.4. NAND controller 102A can use CE 108A.1 to select memory cell 106 A.1. NAND controller 102A may use CE 108a.2 to select memory cell 106 a.2. NAND controller 102A can use CE 108A.3 to select memory cell 106 A.3. NAND controller 102A may use CE 108a.4 to select memory cell 106 a.4.

The signal line 110A may be connected to the NAND controller 102A at one end and connected to a plurality of signal pins in the memory units 106a.1 to 106a.4 in shunt at the other end. That is, the signal line 110A is shared by all of the memory cells 106a.1 to 106 a.4. The signal pin of each memory cell 106a.1 to 106a.4 may be connected to a respective termination resistor: termination Resistor (RTT) 112a.1 in memory cell 106a.1, termination resistor 112a.2 in memory cell 106a.2, termination resistor 112a.3 in memory cell 106a.3, and termination resistor 112a.4 in memory cell 106 a.4. The other end of each termination resistor may be connected to a reference voltage point 114a.1, 114a.2, 114a.3, and 114a.4, respectively. The reference voltage may be the midpoint of the power and ground (e.g., V)_DD/2). In at least one embodiment, each termination resistor 112a.1, 112a.2, 112a.3, and 112a.4 may be a tunable resistor. For example, the resistance of the termination resistor may be programmed and set by the NAND controller 102A. The termination resistor may also be referred to as an on-chip terminator or a resistive terminator. It should be noted thatThe signal pin of each memory cell 106a.1 to 106a.4 may also be connected to an input/output receiver in the respective memory cell, respectively, and in a parallel relationship with the termination resistor.

Each storage unit (e.g., 106A.1, 106A.2, 106A.3, and 106 A.4) can be a Logical Unit (LUN) and assigned an identifier, which can be referred to as a LUN address. A new feature address may be assigned to support ODT as a feature so that ODT settings may be enabled or modified by command. This command may be referred to as an ODT command. In various embodiments, different types of NAND flash memory devices may have the flexibility to assign different feature addresses.

In embodiments consistent with the present disclosure, NAND controller 102A may send ODT commands to the plurality of NAND memory devices 104a.1 and 104a.2 over the NAND interface to enable ODT and/or set the resistance value of ODT. During operation of the NAND memory system 100A, one memory cell may be selected as a target, while other memory cells may be non-target. The target ODT and the non-target ODT may be set using different parameters by the same command. In some embodiments, a command may include a command type field of a command code, may include one address field to identify which memory unit may be selected as the address of the target, one characteristic address that may contain a characteristic address for ODT setting, and a plurality of data fields to carry configuration information for the target and non-target ODT settings.

In at least one embodiment, the command may be a set feature (Setfeature) command, such as a set feature command with a hexadecimal (e.g., D5 h) command code of "D5". NAND memory device 104A.1 can have logic circuit 116A.1 and NAND memory device 104A.2 can have logic circuit 116 A.2. Logic circuits 116a.1 and 116a.2 may be configured to decode a received ODT command and turn on ODT according to the configuration in the command. The resistance values of termination resistors 112A.1, 112A.2, 112A.3, and 112A.4 may be set by logic circuit 116A.1 and logic circuit 116A.2, respectively, according to the settings in the ODT command. The logic circuits 116a.1 and 116a.2 may be implemented in hardware, software, or a combination of hardware and software. For example, the logic circuits 116a.1 and 116a.2 may be implemented by a microprocessor, microcontroller, Field Programmable Gate Array (FPGA), or application specific ic (asic).

FIG. 1B schematically shows an exemplary NAND memory system 100B according to another embodiment. The NAND memory system 100B may include a NAND controller 102B and a plurality of NAND devices 104b.1 and 104 b.2. NAND controller 102B may be connected to NAND devices 104b.1 and 104b.2 via a NAND interface, which may include multiple signal lines, e.g., Chip Enable (CE) 108b.1 and CE 108 b.2. CE 108B.1 can be connected between NAND controller 102B and first NAND device 104 A.1. CE 108b.2 may be connected between NAND controller 102B and a second NAND device 104 b.2. A single signal line 110B may be illustrated as demonstrating a representation of a signal line that may require ODT. The single signal line 110B may be a data bus line, DQS, one data signal line of a RE, or any signal line that requires ODT.

NAND memory device 104B.1 can include two memory cells: 106b.1 and 106b.2, and NAND memory device 104b.2 may include two memory cells: 106b.3 and 106 b.4. Each storage unit 106B.1, 106B.2, 106A.3, and 106A.4 can be a Logical Unit (LUN) and assigned a LUN address. NAND controller 102B may use CE 108B.1 to select either memory cell 106B.1 or memory cell 106B.2 for a data access operation. NAND controller 102B may use CE 108B.2 to select either memory cell 106B.3 or memory cell 106B.4 for a data access operation. That is, in the memory system 100B, the CE signal line may be shared by two memory cells in the memory device.

The signal line 110B may have one end connected to the NAND controller 102B and the other end connected to a plurality of signal pins in the memory units 106b.1 to 106b.4 in shunt. That is, the signal line 110B is shared by all the memory cells 106b.1 to 106 b.4. The signal pin of each memory cell 106b.1 to 106b.4 may be connected to a respective termination resistor: termination resistor 112b.1 in memory cell 106b.1, termination resistor 112b.2 in memory cell 106b.2, termination resistor 112b.3 in memory cell 106b.3, and termination resistor 112b.4 in memory cell 106 b.4. The other end of each termination resistor may be connected to a reference voltage point 1, respectively14b.1, 114b.2, 114b.3 and 114 b.4. The reference voltage may be the midpoint of the power and ground (e.g., V)_DD/2). In at least one embodiment, each termination resistor 112b.1, 112b.2, 112b.3, and 112b.4 may be a tunable resistor. For example, the resistance value of the termination resistor may be programmed and set by the NAND controller 102B. It should be noted that the signal pins of each memory cell 106b.1 to 106b.4 are connected to the input/output receivers in the respective memory cells, respectively, and are in a parallel relationship with the termination resistors.

Memory system 100B may implement the same ODT commands as in memory system 100A. In at least one embodiment, the command may be a set feature command with a command code of "D5" in hexadecimal (e.g., D5 h). NAND memory device 104B.1 may have logic circuit 116B.1 and NAND memory device 104B.2 may have logic circuit 116 B.2. Logic circuits 116b.1 and 116b.2 may be configured to decode a received ODT command and turn on ODT according to the configuration in the command. The resistance values of termination resistors 112B.1, 112B.2, 112B.3, and 112B.4 may be set by logic circuit 116B.1 and logic circuit 116B.2, respectively, according to the settings in the ODT command. The logic circuits 116b.1 and 116b.2 may be implemented in hardware, software, or a combination of hardware and software. For example, the logic circuits 116b.1 and 116b.2 may be implemented by a microprocessor, microcontroller, Field Programmable Gate Array (FPGA), or application specific ic (asic). However, since the CE signal line is shared by two memory cells in one memory device, the ODT command having the non-target setting may turn on the non-target ODT for the two memory cells controlled by the CE signal line or one of the memory cells. For example, if memory unit 106B.1 is selected for dynamic access, an ODT command may be sent on the data bus to turn on the non-targeted ODT for memory units 106B.3 and 106 B.4. It should be noted that for the benefit of signal integrity, it may only be necessary to enable the ODT of one LUN, so in another embodiment, the ODT of memory units 106B.3 or 106B.4 (e.g., one of which may be designated as default to be turned on) may be enabled by one ODT command.

It should be noted that the storage system 100A and the storage system 100B are only two examples. Embodiments in accordance with the present disclosure may have from one to N nonvolatile storage devices, where N is a positive integer. Each non-volatile memory device may have from one to M non-volatile memory cells. Typically, M can be a power of 2, such as 2, 4, 8, and the like. In one embodiment, the CE signal line may be used to control access to a non-volatile memory device containing a memory cell. In another embodiment, the CE signal line may be used to control access to one non-volatile memory cell in a memory device containing two memory cells (e.g., CE 108A.1 of memory cell 106A.1 in FIG. 1A). In yet another embodiment, the CE signal line may be used to control access to a pair of non-volatile memory cells (e.g., CE 108B.1 for memory cells 106B.1 and 106B.2 in FIG. 1B), and the memory cell address may identify which memory cell is selected.

Fig. 2 schematically illustrates an ODT command from a NAND controller to enable and turn off non-target ODT according to one embodiment of the disclosure. The ODT command may be sent from the NAND controller to the NAND memory device via a data bus. The ODT command may be accompanied by a CE signal such that the ODT command may be received and decoded by a CE enabled chip (e.g., a NAND memory device). Other memory devices connected to the NAND interface may also receive signals for an ODT command, but these other NAND memory devices may ignore the ODT command because the CE signals do not enable them. FIG. 2 shows the transmission of two ODT commands from a NAND controller to a NAND memory device. The first ODT command may include a command type field 202, a first address field 204, a second address field 206, and four data fields: d0208, D1210, D2212 and D3214. The first ODT command may be transmitted with CE signal 230. The second ODT command may include a command type field 216, a first address field 218, a second address field 220, and four data fields: d0222, D1224, D2226 and D3228. A second ODT command may be transmitted with CE signal 232.

In an embodiment of NAND memory system 100A, ODT is applied to each LUN. In some embodiments, one of the two address fields of the ODT command may be a LUN address to identify which LUN of the NAND memory device is selected to enable its ODT according to the ODT command. In one embodiment, the command types (e.g., 202 and 216) may be set feature commands with code D5h, the first addresses (e.g., 204 and 218) may be LUN addresses, and the second addresses (e.g., 206 and 220) may be feature addresses for ODT settings.

Assume that LUN 106A.1 of FIG. 1A may need to be dynamically accessed. Any of LUNs 106A.2, 106A.3, 106A.4 may turn on non-target ODT via the two commands of FIG. 2. Taking LUN 106A.3 as an example, CE signals 230 and 232 may be signals on CE signal line 108 A.3. After NAND memory device 104a.2 receives the first command, on-die terminator 112a.3 of memory cell 106a.3 may be placed in an enable state 234 of non-targeted ODT. After the NAND memory device 104A.2 receives the second command in FIG. 2, the on-die terminator 112A.3 of memory cell 106A.3 can be placed in the OFF state 236.

A termination resistor in an off state may be referred to as off or in an off state, where the termination resistor may be disconnected from the signal pin, or equivalently set to a high impedance. The ODT state of the termination resistor may affect the signal transmitted on the signal line, but does not affect the physical connection from the signal pin of the memory cell to an input/output (I/O) signal receiver. For example, if termination resistor 112A.1 is turned off, signal line 110A may still be connected to an I/O signal receiver in memory cell 106 A.1.

Taking an 8-bit data bus as an example, the NAND interface may include 8 signal lines for data (e.g., DQ 0-DQ 7), a differential pair of strobe signals (DQS _ P/DQS _ N), and a differential pair of read enable signals (RE _ P/RE _ N) that may require ODT. The four data fields D0-D3 may contain a configuration of RTT settings and may therefore also be referred to as configuration fields. The RTT setting may specify the value of the resistive terminator for data, strobe, and read enable. In one embodiment, the RTT setting may be a 4-bit field. When four bits of RTT are all zero (which may be expressed in a four-bit format as RTT = 4b' 0000), the ODT may be turned off (or the resistance value may be set to a high impedance); when the RTT is in the range of 4b '0001 to 4b'1111, the discrete value of the resistor of the ODT may be between 15 ohms to 300 ohms. Two bytes of RTT settings may be assigned to the target and non-target ODT configurations, respectively.

Table 1 illustrates an implementation example of the data fields D0 through D3 of the ODT command.

Examples of implementations of data fields in a Table 1 ODT command

As shown in Table 1, the data field D0 may include a four-bit RTT setting for data signal lines DQ0 through DQ7 in the non-target ODT and a four-bit RTT setting for signal line DQS in the non-target ODT. Data field D1 may include a four-bit RTT set, three reserved bits, and an auto-enable bit for signal line RE in the non-targeted ODT. The data field D2 may include a four-bit RTT setting for the data signal lines DQ0 through DQ7 in the target ODT and a four-bit RTT setting for the signal line DQs in the target ODT. Data field D3 may include four reserved bits and a four-bit RTT setting for signal line RE in the target ODT. It should be noted that in some embodiments, the target ODT may be ODT off (or set the target RTT to high impedance).

Table 2 demonstrates an implementation example of RTT settings for ODT commands.

Table 2 RTT setting example

In some embodiments, after the ODT may be turned on, the ODT for the LUN may remain on regardless of the activation or deactivation of the chip enable signal. The ODT may be turned off by a subsequent ODT command, a read command, or a RESET (RESET) command. For example, as shown in FIG. 2, the second ODT command may place an ODT-enabled LUN into an ODT-off state (e.g., LUN 106A.3 changes from an enabled state to an off state).

As shown in table 1, in one embodiment, the ODT configuration field may include a configuration setting (e.g., an auto-enable bit) for automatically enabling ODT. If the NAND controller sets this bit to 1 in the ODT command, the NAND memory device that receives the ODT command can automatically apply the target ODT for any read operation and automatically turn on the non-target ODT after the read operation. If the NAND controller does not set this bit in the ODT command, the NAND memory device will not reopen the non-target ODT after the read operation, so the NAND controller may need to send another ODT command to re-enable the non-target ODT.

In one embodiment, for NAND memory system 100A, when one of the LUNs may need to be dynamically accessed, all other LUNs that are not dynamically accessed may receive the first command of fig. 2 to turn on non-target ODT. In another embodiment, for NAND memory system 100B, a LUN sharing the same CE signal line may not need to turn on its non-target ODT when one of the LUNs may need to be dynamically accessed, while each pair of LUNs of other CE signal lines may need one LUN or both LUNs to turn on the non-target ODT. For example, LUN 106B.1 may be dynamically accessed if needed. LUN 106b.2 may not need to turn on non-target ODT, and the first command of fig. 2 may be sent to CE 108b.2 (e.g., CE signal 230) enabled NAND memory device 104b.2 to turn on non-target ODT for LUN 106b.3 or LUN 106b.4 or both.

Fig. 3 schematically illustrates an ODT command from a NAND controller for switching a target in one embodiment according to the present disclosure. The target switching shown in fig. 3 may be applied to a memory system in which each CE signal line can control one memory cell, for example, the NAND memory system 100A. The signal line 360 may represent a data bus between a NAND controller (e.g., NAND controller 102A) and a NAND memory device (e.g., NAND memory devices 104A.1 and 104 A.2). Signal line 362 may represent a CE signal line (e.g., CE 108 A.1) between the NAND controller and the selected NAND memory cell (e.g., 106 A.1). Signal line 364 may represent a CE signal line (e.g., CE 108 A.3) between the NAND controller and a second NAND memory cell (e.g., 106 A.3). State 366 may represent a non-target ODT state for a first NAND memory unit and state 368 may represent a non-target ODT state for a second NAND memory unit.

In one embodiment, the NAND controller can send ODT commands during system power-up and NAND initialization phases. As shown in fig. 3, the initialization command 302 may be sent on the data bus when the CE enable signal 340 is on the signal line 362. The first ODT command may also be sent via the data bus while CE enable signal 340 is still on. The first ODT command may include a command type field 304, a first address field 306, a second address field 308, and four data fields D0310, D1312, D2314, and D3316. The auto-enable bit may be set (e.g., turned on) in the RTT setting of the data field of the first ODT command. After the first ODT command has been sent, the first NAND memory device receiving the first ODT command can turn on the non-target ODT for the first NAND memory unit, and thus state 366 can illustrate a non-target ODT enabled state 348.

When CE enable signal 340 ends on signal line 362, CE enable signal 344 may turn on signal line 364. When the CE enable signal 344 is on the signal line 364, the initialization command 318 may be sent on the data bus. While CE enable signal 344 is still on, a second ODT command may also be sent via the data bus. The second ODT command may include a command type field 320, a first address field 322, a second address field 324, and four data fields D0326, D1328, D2330, and D3332. The auto-enable bit may be set (e.g., turned on) in the RTT setting of the data field of the second ODT command. After the second ODT command has been sent, the second NAND memory device receiving the second ODT command can turn on the non-target ODT of the second NAND memory unit, and thus state 368 can show a non-target ODT enabled state 356. It should be noted that the horizontal direction from left to right in both fig. 2 and 3 increases with time. Thus, as shown in FIG. 3, the non-target ODT enabled state 348 of the first NAND memory cell and the non-target ODT enabled state 356 of the second NAND memory cell may overlap in time.

In one embodiment, both the non-target ODT enabled state 348 of the first NAND memory unit and the non-target ODT enabled state 356 of the second NAND memory unit may be automatically enabled by setting an automatic enable bit in the first and second ODT commands in FIG. 3. That is, the logic circuits in the NAND memory device can decode a received ODT command and turn on ODT according to the configuration in the command.

When a NAND memory cell is selected as a target of a data access operation, the NAND memory cell in a non-target ODT enabled state may automatically become a target ODT enabled state. For example, as shown in FIG. 3, CE enable signal 342 may originate on CE signal line 362 when the first NAND memory cell is selected for data access. When CE enabled signal 342 begins, state 366 may automatically enter target ODT enabled state 350, which in one embodiment may be equivalent to turning off non-target ODT (e.g., setting the resistance value to a high impedance). The data access commands/data 334 may appear on the data bus during CE signal enable 342. When a second NAND memory cell is subsequently selected for data access, the enable state 342 of the CE signal line 362 may end and the CE signal line 364 may enter the enable state 346. Thus, state 366 may change from target ODT enabled state 350 to non-target ODT enabled state 352 (e.g., setting the resistance value to a non-zero value, which may be set by the configuration value of the data field of the first command), and state 368 may change from non-target ODT enabled state 356 to target ODT enabled state 358, which may be equivalent to turning off the non-target ODT (e.g., setting the resistance value to a high impedance) in one embodiment. When the CE enable signal 346 is on (e.g., pulled low), a data access command/data 336 directed to the second NAND memory cell may appear on the data bus 360.

The target switching shown in fig. 3 may also be applied to a memory system in which each CE signal line can control two memory cells, for example, the NAND memory system 100B. The signal line 360 may represent a data bus between the NAND controller 102B and the NAND memory devices 104B.1 and 104 B.2. Signal line 362 may represent CE 108B.1 between NAND controller 102B and NAND memory device 104 B.1. Signal line 364 may represent CE 108B.2 between NAND controller 102B and NAND memory device 104 B.2. State 366 may represent a non-targeted ODT state for NAND memory device 104b.1 in which one of the two memory units is controlled by an ODT command and the other is always off. For example, the ODT of memory unit 106B.1 is controlled by the ODT command and the ODT of memory unit 106B.2 is always turned off. And state 368 may represent a non-target ODT state for NAND memory device 104b.2 in which one of the two memory units is controlled by an ODT command and the other is always off. For example, the ODT of memory unit 106B.3 is controlled by the ODT command and the ODT of memory unit 106B.4 is always turned off. In this way, the ODT states of NAND memory device 104B.1 and NAND memory device 104B.2 are still automatically enabled and controlled by the corresponding CE signals.

In embodiments where the controller sends an ODT command with an auto-enable bit set to the NAND memory device during system power-up and NAND initialization phases, the target ODT may be automatically enabled when any dynamic write operation may be performed on the NAND memory selected for access; the non-target ODT may be automatically enabled when a non-target NAND memory cell acts as a non-target terminator when accessing other NAND memory devices. This may provide maximum flexibility for system implementation, require minimal investment in firmware implementation, and not incur overhead or throughput penalties on system performance.

It should be noted that the ODT command with the auto-enable bit set may be sent out at any time during operation of the memory system, and need not be sent at initialization. FIG. 3 is only one example of how an ODT command with this auto-enable bit set may affect the operation of a memory system.

In another example implementation, the NAND controller does not set the auto-enable bit in the ODT configuration field. Instead, the NAND controller may issue ODT commands each time a non-target LUN needs to enable a non-target resistive terminator when another non-LUN may become a target and is to be accessed. If the NAND controller circuit is optimized for processing the target LUN and the non-target LUN in synchronization, the NAND controller can arrange one ODT command to the target LUN to open the target LUN ODT and another ODT command to the non-target LUN to open the non-target LUN in sequential order with minimal delay. If the NAND controller is not optimized to process two NAND memory units simultaneously, the firmware of the NAND controller may first send an ODT command to a non-target storage LUN to turn on non-target ODT and then continue to execute regular commands directed to the target NAND memory unit. The normal command may be a command that needs to be sent to a target memory unit regardless of whether ODT needs to be enabled. This implementation may achieve optimal power efficiency by turning on ODT only when needed. If this scheme is implemented at the firmware level, some performance penalty may be introduced. However, since the NAND interface can now operate at higher speeds with non-targeted ODT enabled, system performance will be enhanced to some extent by the higher interface speed instead.

An ODT command implemented according to an embodiment of the present disclosure may replace a conventional ODT configuration and enable command, and both target and non-target ODT may be enabled and configured with only one command. As shown in table 1, RTT fields of the target ODT and the non-target ODT may be set in four data bytes of one ODT command, and the auto-enable bit may provide great flexibility and reduce overhead of switching the target. For example, when a selected LUN (e.g., 106 a.1) is to be accessed as a target, a NAND device containing this LUN may configure ODT (e.g., 112 a.1) according to a target RTT setting in the ODT command for the selected LUN, while other LUNs may enable non-target RTTs according to their respective ODT commands. When a second LUN (e.g., 106 A.2) is to be accessed as a target, the NAND device containing the second LUN can be set to a second LUN-enabled ODT according to the target RTT, while the previously selected LUN and other LUNs can automatically enable non-target RTT settings. In this way, the controller can switch from one target LUN to another without sending ODT commands. Thus, in at least one embodiment, the controller need not issue commands to turn off and enable different target and non-target ODT settings each time a target is switched, thereby greatly reducing overhead.

A memory system implementing ODT commands according to the present disclosure may have a level of flexibility and efficiency supported by any existing non-ODT technology. For example, in a conventional two-step ODT enabling process, each target of the data bus must first be assigned a volume address in a configuration step. A termination matrix configuration is then assigned to each volume so that each volume knows that it has been assigned as a non-target terminator for the other specified volume. During the enabling step, the controller needs to pull all non-target volumes (devices) and the chip enable signal of the target device low. The sniff mode will then be entered once the non-target device detects that its volume address has not been selected. During dynamic data transfer between the controller and the target device, the non-target device will continue to monitor for input commands and turn on its ODT. An ODT command according to the present disclosure may turn on ODT as targeted or untargeted, which is easier to implement.

Furthermore, a NAND controller implementing ODT commands according to the present disclosure need not have pre-existing knowledge of the NAND interface PCB topology. In contrast, conventional NAND controllers require prior knowledge of the NAND interface PCB topology, such as which devices are used as non-target terminations for the target. While the conventional configuration steps are firmware configurable, the chip enable signals are strictly hardware controlled by the controller. Thus, when a target is dynamically accessed, during conventional ODT enabling, the controller must know which particular set of chip enable signals needs to be driven low. This makes the controller design more complex and expensive to support various ODT configurations and a wide range of potential PCB topologies.

Further, in some Toggle NAND devices, commands other than the existing target ODT may be used to support non-target ODT functionality. This introduces undesirable latency because the controller must send a command to disable the target ODT and a different command to enable the non-target ODT each time it switches access between NAND devices. In contrast, an ODT command according to the present disclosure may be one unified command, by which target and non-target ODT settings may be set. As shown in FIG. 3, during initialization, using only one ODT command, a LUN (or NAND device) may switch from a non-target ODT to a target ODT depending on whether it is in a dynamic access mode (e.g., active write or program).

Furthermore, current mainstream controller designs do not support driving multiple chip enable signals at once. To support this functionality, not only are new controller development investments introduced, but new technical risks are also introduced, including racing and competitive conditions that traditional controller designs have sought to avoid. It is worth mentioning that there are other non-ONFI NAND flash memory devices on the market that support non-targeted ODT functionality, but unfortunately they all require pulling down multiple chip enable signals at the same time. A controller implementing ODT commands according to the present disclosure need not pull down multiple chip enable signals simultaneously, and features of embodiments may be implemented in firmware. Thus, implementing ODT commands according to the present disclosure may be more cost effective and easier.

It is also important that embodiments in accordance with the present disclosure avoid a sniff mode, where non-target NAND memory devices are required to dynamically monitor and process commands to determine whether they are selected as targets. During sniff mode, I/O and internal circuitry of the non-target device need to remain on, but consume additional power consumption. Thus, embodiments in accordance with the present disclosure can help reduce power consumption in NAND memory devices.

Fig. 4 is a flow diagram of a process 400 for controlling non-target on-die termination (ODT) according to an embodiment of the disclosure. In block 402, the non-volatile storage device may receive a chip enable signal from the controller on a chip enable signal line. For example, non-volatile storage device 104A.1 may receive a chip enable signal on CE signal line 108A.1, which may be CE signal 230 in FIG. 2 or CE signal 340 in FIG. 3; or nonvolatile storage device 104b.1 may receive a chip enable signal, which may be CE signal 230 in fig. 2 or CE signal 340 in fig. 3, on CE signal line 108 b.1. In block 404, an on termination (ODT) command may be received on the data bus from the controller while the chip enable signal is on. For example, nonvolatile memory device 104a.1 may receive the first ODT command of fig. 2 when CE signal 230 turns on, or the first ODT command of fig. 3 when CE signal 340 turns on; or nonvolatile memory device 104b.1 may receive the first ODT command of fig. 2 when CE signal 230 turns on or fig. 3 when CE signal 340 is stuck.

In block 406, the on-die termination command may be decoded. For example, non-volatile memory device 104A.1 can use logic circuit 116A.1 to decode the received ODT command, or non-volatile memory device 104B.1 can use logic circuit 116B.1 to decode the received ODT command. In block 408, a termination Resistor (RTT) setting in the ODT command may be applied to a selected nonvolatile memory cell in the nonvolatile memory device to enable ODT of the selected nonvolatile memory cell. For example, termination resistor 112a.1 of memory cell 106a.1 may configure non-target ODT enabled state 234 by applying the RTT setting of the first command in fig. 2, or may configure non-target ODT enabled state 348 by applying the RTT setting of the first command in fig. 3; either termination resistor 112b.1 of memory cell 106b.1 may configure non-target ODT enabled state 234 by applying the RTT setting of the first command in fig. 2 or non-target ODT enabled state 348 may be configured by applying the RTT setting of the first command of fig. 3.

Process 400 may be implemented using software (e.g., executable by a computer processor (CPU, GPU, or both)), hardware (e.g., a Field Programmable Gate Array (FPGA) or application specific ic (asic)), firmware, or any suitable combination of the three. In one embodiment, for example, the logic circuits of the non-volatile storage device may be implemented in hardware circuits. Further, process 400 may be programmed in computer processor-executable instructions and executed by a computer processor (e.g., a microprocessor or microcontroller) that executes the executable instructions.

In an exemplary embodiment, a method for controlling on-die termination in a non-volatile memory device is provided. The method can comprise the following steps: a chip enable signal is received from a controller on a chip enable signal line, an on-die termination (ODT) command is received from the controller on a data bus when the chip enable signal is on, the on-die termination command is decoded and a termination Resistor (RTT) setting in the ODT command is applied to a selected nonvolatile memory cell in a nonvolatile memory device to enable ODT for the selected nonvolatile memory cell.

In one embodiment, the ODT command includes a command type code, a memory cell address, and a feature address, and the RTT setting is included in a plurality of data fields of the ODT command.

In one embodiment, the command type code is a code for setting a feature, and the feature address indicates that the feature is ODT.

In one embodiment, the chip enable signal line is used to control access to the non-volatile storage device.

In one embodiment, the chip enable signal line is used to control access to a pair of non-volatile memory cells of the selected non-volatile memory cells.

In one embodiment, the RTT settings include a target ODT setting and a non-target ODT setting.

In one embodiment, the ODT command includes configuration settings for the selected non-volatile memory device to automatically enable non-target ODT.

In one embodiment, the method may further comprise: receiving another chip enable signal from the controller on the chip enable signal line and another memory cell address from the controller on the data bus to select the nonvolatile memory cell for a data access operation, receiving a data access command, data, or both for the data access operation on the data bus when the another chip enable signal is on, automatically switching to a target ODT setting for the data access operation on the selected nonvolatile memory cell, and performing the data access operation using the target ODT setting.

In one embodiment, the target ODT setting is a high impedance ODT resistance value.

In one embodiment, the method may further turn off ODT for the selected nonvolatile memory cell by a subsequent ODT command, read command, or reset command.

In another exemplary embodiment, a non-volatile storage system is provided. The non-volatile memory system may include a controller and a memory device connected to the non-volatile memory device through at least one chip enable signal line and a data bus. The non-volatile memory device may be configured to receive a chip enable signal from a controller on a chip enable signal line, receive an on-die termination (ODT) command from the controller on a data bus when the chip enable signal is on, decode the on-die termination command and apply a termination Resistor (RTT) setting in the ODT command to a selected non-volatile memory cell in the non-volatile memory device, thereby enabling ODT for the selected non-volatile memory cell.

In one embodiment, the chip enable signal line is used to control access to a selected one of the pair of non-volatile memory cells.

In one embodiment, the non-volatile memory device may be further configured to receive another chip enable signal from the controller on the chip enable signal line and another memory cell address from the controller on the data bus to select the selected non-volatile memory cell for a data access operation, receive an access command, data, or both on the data bus while the other chip enable signal is on, automatically switch to a target ODT setting on the selected non-volatile memory cell for the data access operation, and perform the data access operation using the target ODT setting.

In one embodiment, the non-volatile memory system may further include turning off ODT for the selected non-volatile memory unit by a subsequent ODT command, a read command, or a reset command.

Any of the disclosed methods and operations may be implemented as computer-executable instructions (e.g., software code for the operations described herein) stored on one or more computer-readable storage media (e.g., non-transitory computer-readable media). Or more optical disk media, volatile storage components (e.g., DRAM or SRAM) or non-volatile storage components (e.g., hard disk drive)) and executed on a device controller (e.g., firmware executed by an ASIC). Any computer-executable instructions for implementing the disclosed techniques, as well as any data created and used during implementation of the disclosed embodiments, can be stored on one or more computer-readable media (e.g., non-transitory computer-readable media).

While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

1. A method for controlling on-die termination in a non-volatile memory device, comprising:

receiving a chip enable signal from the controller on a chip enable signal line;

receiving an on-die termination (ODT) command from the controller on a data bus when the chip enable signal is on, the ODT command including a target ODT setting, a non-target ODT setting, and an automatic enable bit setting, the target and non-target ODTs being enabled and configured with only one command, wherein RTT fields of the target ODT and the non-target ODT are set in one ODT command;

decoding the on-die termination command; and

applying the termination resistor RTT setting in the ODT command to a selected non-volatile memory cell in a non-volatile memory device to enable the ODT of the selected non-volatile memory cell, wherein when a selected memory cell is to be accessed as a target, the nonvolatile memory device including this memory cell configures ODT for the selected memory cell according to the target RTT setting in the ODT command, while other memory units enable the non-target RTT according to their respective ODT commands, when the second memory unit is to be accessed as a target, the nonvolatile memory device including the second memory unit may be set to the second memory unit enable ODT according to the target RTT, and the previously selected memory location and other memory locations automatically enable the non-target RTT setting, such that, the controller may switch from one target memory unit to another target memory unit without sending an ODT command; automatically enabling the target ODT when performing any dynamic write operations on the nonvolatile memory cells selected for access; non-target ODT is automatically enabled when a non-target non-volatile memory cell acts as a non-target terminator while accessing other non-volatile memory cells.

2. The method of claim 1, wherein the ODT command comprises a command type code, a memory cell address, and a feature address, and wherein the RTT setting is included in a plurality of data fields of the ODT command.

3. The method of claim 2, wherein the command type code is a code for setting a feature, and wherein the feature address indicates that the feature is ODT.

4. The method of claim 3, wherein the chip enable signal line is used to control access to the non-volatile memory device.

5. The method of claim 3, wherein the chip enable signal line is used to control access to a pair of non-volatile memory cells including the selected non-volatile memory cell.

6. The method of claim 1, further comprising:

receiving another chip enable signal from the controller on the chip enable signal line and another memory cell address from the controller on the data bus to select the selected non-volatile memory cell for a data access operation;

when the other chip enable signal is on, receiving a data access command and/or data for the data access operation on the data bus;

automatically switching to a target ODT setting on the selected non-volatile memory unit for the data access operation; and

performing the data access operation using the target ODT setting.

7. The method of claim 6, wherein the target ODT setting is a high impedance ODT resistance value.

8. The method of claim 1, further comprising turning off ODT of the selected nonvolatile memory unit by a subsequent ODT command, a read command, or a reset command.

9. A non-volatile storage system, comprising:

a controller; and

a non-volatile storage device connected to the controller by at least one chip enable signal line and a data bus, the non-volatile storage device configured to:

receiving a chip enable signal from the controller on the chip enable signal line,

receiving an on-die termination (ODT) command from the controller on the data bus when the chip enable signal is on, wherein the ODT command comprises a target ODT setting, a non-target ODT setting and an automatic enable bit setting;

decoding the on-die termination command; and

applying the termination resistor RTT setting in the ODT command to a selected nonvolatile memory cell in a nonvolatile memory device, wherein a target ODT is automatically enabled when any dynamic write operation is performed on the nonvolatile memory cell selected for access; non-target ODT is automatically enabled when a non-target non-volatile memory cell acts as a non-target terminator while accessing other non-volatile memory cells.

10. The non-volatile memory system of claim 9, wherein the ODT command comprises a command type code, a memory cell address, and a feature address, and the RTT settings are included in a plurality of data fields of the ODT command.

11. The nonvolatile memory system according to claim 10, wherein the command type code is a code for setting a feature, and the feature address indicates that the feature is ODT.

12. The non-volatile storage system of claim 11, wherein the chip enable signal line is used to control access to the non-volatile storage device.

13. The non-volatile memory system of claim 11, wherein the chip enable signal line is used to control access to a pair of non-volatile memory cells including the selected non-volatile memory cell.

14. The non-volatile storage system of claim 9, wherein the non-volatile storage device is further configured to:

receiving another chip enable signal from the controller on the chip enable signal line and another memory cell address from the controller on the data bus to perform a data access operation on the selected non-volatile memory cell;

performing the data access operation using the target ODT setting.

15. The non-volatile memory system of claim 14, wherein the target ODT setting is a high impedance ODT resistance value.

16. The non-volatile storage system of claim 9, further comprising: the ODT for the selected nonvolatile memory cell is disabled by a subsequent ODT command, a read command, or a reset command.