CN111949578B - DDR3 controller based on DFI standard - Google Patents
DDR3 controller based on DFI standard Download PDFInfo
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- CN111949578B CN111949578B CN202010781818.7A CN202010781818A CN111949578B CN 111949578 B CN111949578 B CN 111949578B CN 202010781818 A CN202010781818 A CN 202010781818A CN 111949578 B CN111949578 B CN 111949578B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
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Abstract
The DDR3 controller based on the DFI standard comprises a request analysis interface module, a grouping and ID mark module, a Bank read-write management module, a read-write data channel module, a first-level queue buffer module, an instruction sending module, a non-read-write module and a DFI interface module, wherein the invention ensures the high efficiency of rate transmission through a specified grouping principle, a command taking principle and a reordering strategy; the command aging is prevented by setting a group command quantity threshold value and marking a command request time period and combining a reordering strategy; the read-write of the same bank address is ensured to be carried out according to the request sequence through a grouping principle, the related ID attribute is defined to realize the one-to-one correspondence of commands and data, and the reliability of transmission is jointly realized.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a DDR3 controller based on a DFI standard.
Background
Through analysis of the DDR3 protocol standard, two main aspects that can affect DDR3 efficiency are: 1. frequent switching between reading and writing increases bandwidth waste of switching time between reading and writing; 2. frequent switching of different rows of the same bank, and bandwidth waste is caused by increasing the precharge and activation time of the bank; the design of the controller ensures continuous reading or continuous writing operation for a long time as much as possible, and avoids the switching interval between different rows of the same bank as much as possible; the DDR controller in the market at present is mainly an Xilinx official MIG soft core, but the Xilinx MIG core does not consider a mechanism for preventing command aging, and can not guarantee timely response of commands in a reordering strategy process, and can cause continuous aging of the commands, so that command suspension is caused; many controllers in the market cannot achieve both reliability and high efficiency, and can cause aging of requests while maximizing bandwidth, thereby causing unexpected results.
Disclosure of Invention
In order to solve the technical problems, the invention aims to provide a DDR3 controller based on a DFI standard, which is used for improving the bandwidth utilization rate on the premise of ensuring the reliability of data transmission.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
the DDR3 controller based on the DFI standard comprises a request analysis interface module, a grouping and ID mark module, a Bank read-write management module, a read-write data channel module, a first-level queue buffer module, an instruction sending module, a non-read-write module and a DFI interface module, wherein the DFI interface module sends a DFI protocol signal to a PHY supporting the DFI standard, and finally, the DFI protocol signal is sent to DDR3 particles;
the system comprises a request analysis interface module, a grouping and ID mark module, a Bank read-write management module, a first-level queue cache module, an instruction sending module and a DFI interface module, which are electrically connected in sequence, wherein a non-read-write module is electrically connected with the DFI interface module, and the request analysis interface module, a read-write data channel module and the DFI interface module are electrically connected in sequence.
And the request analysis interface module is used for receiving the user request and splitting the request for asynchronous caching.
The read-write data channel module is used for caching read-write data flowing between DDR3 particles and the user interface and exchanging data according to time sequence requirements.
The grouping and ID marking module is used for grouping the split requests, determining the ID attribute corresponding to the read-write command, independently adding the data storage address information ID corresponding to the command to the write command, independently adding the request sequence ID to the read command, and simultaneously endowing the read-write command with the sequence ID.
The Bank read-write management module is used for storing the commands sent by the grouping and ID mark module, analyzing the sequence and ID information; dividing the packet into banks and storing the packets in sequence into corresponding synchronous FIFOs; and simultaneously monitoring and feeding back the information such as bank, group order and the like in each FIFO.
And the first-level queue cache module is used for taking out the command from the bank management module according to a command taking principle, arranging the storage position of the taken-out command in the queue through a reordering strategy, and finally taking out the command from the bottom of the queue in the first-level queue cache module by the command sending module.
And the non-read-write module is used for generating non-read-write commands such as refreshing, initializing and the like.
The instruction sending module is used for fetching commands from the first-level queue cache module, translating all commands in the queue with fixed depth into parallel input signals of the DFI interface module according to the clock frequency relation between the controller and DDR3 particles according to the competition principle.
The DFI interface module is used for sending the signal input by the instruction sending module to the DDR3 physical layer PHY supporting the DFI standard according to the DFI standard protocol, taking data from the read-write data channel module, outputting the data according to the DFI standard protocol, and simultaneously receiving the data input from the physical layer PHY and sending the data to the read-write data channel module.
The read-write data channel module temporarily stores write data corresponding to the write command to a position which can be covered by the address, and when the data of the data is sent to the particles, the covering flag bit corresponding to the address temporarily storing the data is updated in time; storing the read commands in the queue according to the request sequence, temporarily storing the data read back from the DDR3 particles, recording the storage address, and updating the coverage zone bit of the address after the data are sent to the user bus; and a comparison mechanism is also provided for comparing the positions of the requests of the data read back from the particles after the reordering in the user read request queue and transmitting the read-back data to the user bus according to the user read request sequence.
The first-level queue buffer module comprises a command taking principle and a reordering strategy:
the command taking principle is specifically as follows: when the commands are fetched from the Bank read-write management module, the next group of commands are fetched according to the principle of group round robin nested Bank round robin, namely, after one group of commands are fetched, the cycle is performed; in the process of fetching the group command, sequentially and circularly fetching single commands of different banks until the next group is reached, and repeating the principle, wherein the aim is to arrange the commands of different banks in the same type as possible;
the reordering strategy refers to that the storage position relation of each command in the queue should meet the following relation: commands of the same bank and the same type read or write in the same time period are tightly arranged in the cache queue as much as possible, commands are prevented from aging, commands of the same bank and different lines are arranged together as much as possible, and therefore bandwidth waste caused by bank precharge and activation time generated by switching of the commands of the same bank is reduced.
The grouping and ID marking module comprises the following specific steps:
the read-write commands of each bank are grouped according to the sequence of the requests, the read-write commands of the same bank are not distributed beyond groups, a plurality of read commands are distributed to the same group as much as possible on the premise of ensuring that the read-write is free from errors and the number of commands in the group does not exceed a threshold value, and the plurality of write commands are distributed to other groups different from the read commands, so that the read-write separation is realized;
the different IDs of the read-write commands are formed, specifically as follows: marking the initial address according to the data storage of the write command to form address information ID specific to the write command; read request sequence IDs specific to the read commands are formed according to the sequence of the read command requests; the sequence ID of the read/write command defined by setting a threshold value for the number of read/write commands sent from the module changes when the number of read/write commands sent reaches the threshold value limit, and describes that the transmission of the request command changes in a time period.
All commands in the command sending module queue are input to parallel signals of the DFI interface module according to a certain competition principle, the number of the parallel signals is determined according to the proportion of the clock frequency of the DDR3 controller to the working clock frequency of the DDR3 particles and the number of DDR command types, so that the signal quantity sent by the DDR3 controller in a unit period can meet the signal quantity which can be processed by the DDR3 particles in a plurality of periods of the same time under the working frequency of the DDR3 particles, bandwidth matching is realized, meanwhile, the commands sent to the DFI interface module are monitored to map the precharge and activation states of the internal bank of the DDR3 particles, whether the DDR3 commands sent by the commands in the queue according to time sequences can meet the time sequence requirements of signal sending in a plurality of periods under the working clock of the DDR3 particles is checked, and the corresponding cycle of the DDR3 particles can be sent by each DDR3 command is marked. Multiple instructions capable of meeting timing requirements in the same DDR3 particle working clock period can obtain signal line occupation weights with highest priority through competition and send the signal line occupation weights to the DFI interface module, wherein the priority is determined by the delay period of the instructions and the position of a queue to which the instructions belong, and the higher the priority is, the higher the delay period is.
The invention has the beneficial effects that:
the invention ensures the high efficiency of rate transmission through a specified grouping principle, a command taking principle and a reordering strategy; the command aging is prevented by setting a group command quantity threshold value and marking a command request time period and combining a reordering strategy; the read-write of the same address is ensured to be carried out according to the request sequence through a grouping principle, the related ID attribute is defined to realize the one-to-one correspondence between the command and the data, and the reliability of transmission is realized together.
After a user request is split into a single burst command through a command analysis interface module, a grouping and ID mark module groups as many read and write commands as possible on the premise of ensuring reliable reading and writing as possible according to a grouping principle, namely a plurality of write commands are placed in one group as much as possible, and a plurality of read commands are placed in other groups; setting a threshold value of commands in a group, and raising a forbidden enabling bit after the threshold value is reached, wherein a full state is generated in a corresponding group sequence in a Bank read-write management module, and the full state is not canceled until all commands of the group in the Bank read-write management module are sent to a first-level queue cache module, so that the situation that the number of commands in a single group is unlimited can be prevented; the change of the time period to which the command belongs is described by counting the number of the sending requests and changing the sequence ID after the number reaches a threshold value;
the Bank read-write management module stores the read-write commands of the grouped groups into the FIFO of the corresponding Bank under the corresponding group sequence according to DDR3Bank division, records and manages the read-write commands, and timely updates and feeds back the states of the FIFO and the group sequence;
the first-level queue buffer module takes commands from the Bank read-write management module according to the principle of group round robin nested Bank round robin, so that command read-write classification and Bank interleaving are stored in a queue; frequent switching between reading and writing is reduced, the tight arrangement condition of different bank commands is increased, and extra precharge and activation time cannot be caused by the requests among different banks; according to a reordering strategy, commands of the same bank and the same type of reading or writing in the same row in a time period are tightly arranged in a cache queue as much as possible, so that the quick hit probability is increased, the situation that commands of different rows of the same bank are arranged together is reduced, and therefore bandwidth waste caused by bank precharge and activation time generated by switching of the commands of the rows is reduced. Preventing command aging by not participating in reordering (not dequeuing) of commands in different order IDs, i.e., different request periods, and limiting the number of commands in a group together;
the read-write data channel module stores the data corresponding to the write command, and feeds back the address information ID of the stored data of the write command to the command channel, so that the commands and the addresses are in one-to-one correspondence; the data transmission reliability is realized by recording the sequence of the read command requests and feeding back the request sequence ID of the read command to the command channel, so that the data read back after command reordering can be sent to the bus according to the sequence of the read command requests.
Drawings
Fig. 1 is a block diagram of a DDR3 controller based on DFI standard according to an embodiment of the present invention.
FIG. 2 is a block diagram of a block arbitration scheme for a block and ID tag module according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings.
As shown in fig. 1, a reliable and efficient DDR3 controller based on DFI standard includes a request parsing interface module 1, a packet and ID flag module 2, a Bank read/write management module 3, a read/write data channel module 4, a first level queue buffer module 5, an instruction transmitting module 6, a non-read/write module 7, and a DFI interface module 8.
The request analysis interface module 1 is used for receiving commands and data on a user bus; and splitting the command and the data requested by the user into a burst-processable length of DDR3 particles, and asynchronously caching the command and the data into the FIFO.
The grouping and ID mark module 2 is used for giving a grouping sequence to the split command according to a grouping strategy, respectively giving corresponding ID attribute to the read-write command, and then transmitting the command to the Bank read-write management module 3;
wherein the grouping strategy is mainly embodied in four aspects: first aspect: the read-write is separated independently, so that the read command and the write command do not appear in the same group, and the read-write switching time of DDR3 particles is reduced; in the second aspect, the read-write command of the same bank cannot be set up according to the sequence of the requests, so that the DDR3 bandwidth utilization rate is improved by properly adjusting the sequence of the split requests on the premise of not affecting the read-write reliability; third aspect: setting a threshold number limit of each group, when the threshold is reached, the disable enable bit of the group is pulled high, the corresponding group sequence in the Bank read-write management module generates a full state, which indicates that the request is not allowed to be distributed to the group, and the full state of the corresponding group sequence in the Bank read-write management module is not released until the request of the group in the Bank read-write management module is completely taken away, so that the situation of excessive commands in part of the groups is avoided, and the fourth aspect: the number of the groups is limited by the maximum value, and the real-time condition of the priority of the feedback group in the Bank read-write management module 3 is used as the judgment condition of the current group allocation;
the ID attribute given to the read/write command by the grouping and ID flag module 2 has three contents, which are explained as follows: 1. the position attribute of the write command is independently possessed, specifically, the initial address of the data corresponding to the write command stored in the RAM in the read-write data channel module is used for conveniently taking the data corresponding to the write command from the read-write data channel module; 2. the request sequence attribute of the read command is independently owned, specifically, the sequence of the read command in the user request, so that the cached data read back from the DDR particles can be conveniently sent to the bus according to the sequence of the user request; 3. the sequence attribute of the read-write command is that the sequence state changes once after the number of the read-write commands sent from the module reaches the threshold value of the counter, the sequence state describes that the command requests to be sent change in a time period, and the counter is cleared at the same time, so that the counting is restarted, and whether the commands are located in the same time period or not can be found by checking the sequence state;
the method and the device have the advantages of considering request response rate and bandwidth utilization rate, and guaranteeing reliable response of requests and improving bandwidth utilization rate through a plurality of means such as read-write rearrangement, read-write grouping, fast hit queue insertion, bank command interpolation, threshold value setting and the like.
The packet arbitration implementation principle is shown in fig. 2:
taking the write command of bank0 as an example when requesting currently, the arbitration thinking is as follows:
(1) If the latest read group N of the corresponding Bank0 exists in the Bank read-write management module 3, and the number of members of the group N+1 does not reach a threshold value, namely the group is not in a full state, and the priority of the group N+1 is lower than that of the group N, a group N+I is assigned to the Bank0 write command;
(2) If the latest read group N of the corresponding Bank0 does not exist in the Bank read-write management module 3, the Bank read-write management module has the latest write command of the Bank0, and the Bank0 is assigned with a group order M under the condition that the group M where the latest write command of the Bank0 exists in the Bank read-write management module is not in a full state;
(3) If the latest read group N of the corresponding Bank0 does not exist in the Bank read-write management module 3, the latest write command of the Bank0 exists in the Bank read-write management module, and if the group M of the Bank0 latest write command in the Bank read-write management module is in a full state, the group P of the latest write effective command exists and is not full, the latest write sequence group P is assigned to the Bank0 write command;
(4) If the latest read group N of the corresponding Bank0 does not exist in the Bank read-write management module 3, the latest write command of the Bank0 does not exist in the Bank read-write management module, the group P where the latest write command exists is not full, and the latest write sequence group P is assigned to the Bank0 write command;
(5) If the latest read group N of the corresponding Bank0 does not exist in the Bank read-write management module 3, and no latest write command effective group P of the Bank0 exist in the Bank read-write management module; if the latest read command effective group U exists, the bank0 write command is assigned a group U+1, and if the latest read command effective group does not exist, the bank0 is assigned a group 0 in an initialization stage;
(6) Otherwise, wait to give a pause flag to pause the grouping.
The Bank read-write management module 3 is used for storing the command sent from the grouping and ID mark module 2, and storing the command in the synchronous FIFO of the corresponding Bank under the corresponding grouping sequence by analyzing the grouping sequence and ID information and caching the grouping sequence and the grouping sequence; meanwhile, the content of all FIFO in the module is monitored, the information such as which bank is read or written in the command of each group in the module, whether the number of commands of each group reaches a threshold value or not generates a full state corresponding to the group order, the current group of the latest read and write commands with the lowest priority of each bank, the current group priority condition, the current latest group of the latest read and write commands with the lowest priority and the like is used as an arbitration condition for grouping and ID mark module 2 to assign the commands to the group order; the priority of the group is defined as the highest priority of the group where the command which is being fetched by the command sending module 4 is located, and the group is added with one on the basis, and the priority is one level lower; it should also be followed that the full state of each group is maintained until the group data is completely transmitted after the number of commands of the group reaches the threshold to generate the full state, and the full state cannot be canceled, and the priority of the group is the lowest.
The read-write data channel module 4 is used as a channel for exchanging DDR3 particles with user data; the method mainly has three functions, namely, in the first aspect, temporary storage of write data corresponding to a write command is realized, after the data of the command is sent to the DFI interface module 8, a flag bit which can be covered by an address of the data is updated and temporarily stored in time, the write data of the next command can determine which address to put by checking whether each address can cover the flag bit or not and is fed back to the grouping and ID flag module 2 to serve as address information ID of the write command; the second aspect stores the read command in the queue according to the request sequence, temporarily stores the data read back from the DDR3 particles, records the storage address, and updates the address to cover the flag bit after the data is sent to the user bus; the third aspect is provided with a comparing mechanism for comparing the positions of the requests to which the reordered data read back from the granule belong in the read request queue by extracting the request sequence ID of the read command, and transmitting the read back data to the user bus in the read request sequence.
The first-level queue buffer module 5 is used for realizing the reordering of the same-type commands of the same-row same-bank same-order IDs, the precharge and activation time of the commands between the same types among different rows of the same bank can be reduced by the same-row same-bank reordering, the order attribute of the IDs is checked, the different-order IDs cannot participate in the reordering, the command aging is prevented, the commands of different types cannot participate in the reordering, and the reliability of reading and writing is ensured; the main implementation mode is that commands are fetched from the Bank read-write management module 3 through a queue with fixed threshold depth, and queue inserting positions are arranged for the newly fetched commands according to the principle that commands with the same rank, the same type and the same order ID are tightly arranged as much as possible; after the commands enter the queue in sequence, checking whether the same type of read or write commands of the same bank and the same line exist, taking the write commands as an example, if the read commands of the same bank and the same line exist, the queue is not inserted, if the read commands of the same bank and the same line do not exist, checking whether the write commands of the same bank and the same line exist, if the read commands of the same bank and the same line exist, checking the sequence ID bits, the sequence ID is consistent, the commands can be inserted and arranged behind the write commands of the same bank and the same line, and the commands behind the same can correspondingly move one bit backwards, so that the bandwidth utilization rate is improved, and meanwhile, the commands can be prevented from aging.
The non-read-write module 7 is configured to generate other non-read-write commands such as refresh, initialization, etc. to the DFI interface module 8.
The command sending module outputs a signal to the DFI interface module 8, and parallel output is required to be realized according to the frequency proportion of the clock frequency of the DDR3 controller and the working clock frequency of the DDR3 particles, so that the signal quantity sent by the DDR3 controller in a unit period can meet the signal quantity which can be processed by the DDR3 particles in a plurality of periods of the working frequency of the DDR3 controller, and bandwidth matching is realized.
The instruction sending module 6 is configured to fetch corresponding read-write commands from the first-level queue buffer module 4, store the commands in a queue with a fixed depth, and update status flags of the DDR3 granule bank precharge, the activation, etc. by monitoring a command mapping DDR3 granule internal bank precharge and activation status sent to the DFI interface module, all commands in the queue in one period can check whether the timing sequence meets the periodic sending requirement by checking the status of the DDR3 granule, send commands meeting the timing sequence of the DDR3 granule to the DFI interface module 8, where the commands sent by the read-write commands related to different positions of the queue according to the DDR3 protocol and the timing sequence have a phenomenon of competing for the same signal line at the same time, and arrange the contention according to the following principle:
taking the frequency ratio of the DDR3 controller clock frequency to the DDR3 particle working clock frequency as 1:4 as an example; because an individual write command in the queue may be converted into instructions of DDR3 protocol and time sequence, such as bank activation, row address writing, precharge and the like, the write signal required by the row address writing instruction is used for explanation, in order to map the command sent by the row address writing instruction on the period meeting the time sequence to a specific period of DDR3 granule working clock, 4 parallel write signal lines are required to correspond to 4 periods of DDR3 working clock under a single period of the controller in order to meet bandwidth matching; namely, if the first period under the DDR3 working clock starts to meet the time sequence requirement, a competition request is input on the write signal line 1, and the other steps are performed in the same way; if a plurality of row address write instructions compete for the same write signal line together, the write signal line 1 is sequentially allocated according to the sequence from the write signal line 1 to the write signal line 4, firstly checking whether the write signal line 1 has an occupation request, if a plurality of the write signal lines or one write signal line exist, directly allocating the occupation rights of the write signal line 1 to the write signal line if the write signal line has a plurality of the write signal lines or one write signal line exists, and if a plurality of the write signal lines or one write signal line exist, the write signal line 1 needs to compete, wherein the delay priority needs to be checked firstly, and the occupation rights with high delay priority are obtained; if the delay priorities are consistent, checking the queue priority, and acquiring the occupation weight of the instruction with the high queue priority; the instruction which does not acquire the right of the write signal line 1 is transferred to the competing priority on the write signal line 2; by analogy, if the period has a request and does not acquire the right of occupation, the delay priority of the period is increased by one level; the delay priority is used for describing the waiting time of the request, the queue priority is used for describing the request which position in the queue is provided by the command, the queue priority is fixed, the bottom priority of the queue is highest, the top is lowest along with the position being far away.
The DFI interface module 8 translates commands input by the instruction sending module 6 and the non-read-write module 7 into DFI standard output; meanwhile, analyzing the ID to take out the data corresponding to the command from the corresponding position in the read-write data channel module 4 and output the data according to the DFI standard; the system is also used for monitoring the transmitted read command and sequentially transmitting the read command to the read-write data channel module 4; and simultaneously, read-back data input according to the DFI standard is received, and the data is processed and then sent to the read-write data channel module 4.
It should be understood that various other corresponding changes and modifications can be made by one skilled in the art according to the technical concept of the present invention, and all such changes and modifications should fall within the scope of the claims of the present invention.
Claims (5)
1. The DDR3 controller based on the DFI standard is characterized by comprising a request analysis interface module, a grouping and ID mark module, a Bank read-write management module, a read-write data channel module, a first-level queue buffer module, an instruction sending module, a non-read-write module and a DFI interface module, wherein the DFI interface module sends DFI protocol signals to a PHY supporting the DFI standard, and finally, the DFI protocol signals are sent to DDR3 particles;
the system comprises a request analysis interface module, a grouping and ID mark module, a Bank read-write management module, a first-level queue cache module, an instruction sending module and a DFI interface module, which are electrically connected in sequence, wherein a non-read-write module is electrically connected with the DFI interface module, and the request analysis interface module, a read-write data channel module and the DFI interface module are electrically connected in sequence;
the request analysis interface module is used for receiving a user request and splitting the request for asynchronous caching;
the read-write data channel module is used for caching read-write data flowing between DDR3 particles and the user interface and exchanging data according to time sequence requirements;
the grouping and ID mark module is used for grouping the decomposed requests, determining ID attributes corresponding to the read-write commands, independently adding data storage address information ID corresponding to the write commands, independently adding request sequence ID to the read commands, and simultaneously endowing sequence ID to the read-write commands;
the Bank read-write management module is used for storing the command sent by the upper module, analyzing the sequence and ID information; dividing the bank, and sequentially storing the bank and the bank into corresponding synchronous FIFOs; simultaneously monitoring and feeding back the bank and group sequence information in each FIFO;
the first-level queue buffer module is used for taking out commands from the Bank read-write management module according to a command taking principle, arranging the positions of the taken-out commands in the queue through a reordering strategy, and finally taking out the commands from the bottom of the queue by the command sending module;
the non-read-write module is used for generating a refresh and initialization non-read-write command;
the instruction sending module is used for fetching commands from the first-level queue cache module, translating all commands in the self queue into parallel input signals of the DFI interface module according to the clock frequency relation between the controller and DDR3 particles according to the competition principle;
the DFI interface module is used for transmitting the signal input by the instruction transmitting module to the DDR3 physical layer PHY supporting the DFI standard according to the DFI standard protocol; data is taken from the read-write data channel module, and the data is output according to the DFI standard protocol; and meanwhile, data input from a physical layer PHY is received and sent to a read-write data channel module.
2. The DDR3 controller based on DFI standard of claim 1, wherein the read/write data channel module temporarily stores write data corresponding to a write command to a location where an address can be covered, updates a flag bit corresponding to the address temporarily storing the data in time after the data is transmitted to the granule, stores a read command in a queue according to a request order, temporarily stores data read back from the DDR3 granule, records the stored address, and updates the flag bit corresponding to the address after the data is transmitted to the user bus; and a comparison mechanism is also provided for comparing the positions of the requests of the reordered data read back from the particles in the user read request queue and transmitting the read-back data to the user bus according to the user read request sequence.
3. The DFI standard-based DDR3 controller of claim 1, wherein the primary queue buffer module comprises a fetch rule and a reorder policy:
the command taking principle is specifically that when commands are taken from a Bank read-write management module, a group of commands are taken out according to the principle of group round robin nested Bank round robin, namely a group of commands are taken out, and then a group of commands are taken out, and the cycle is carried out; sequentially and circularly taking single commands of different banks in the process of taking the group command until the next group is reached, and repeating the principle;
the reordering strategy refers to that the storage position relation of each command in the queue should meet the following relation:
commands of the same bank and the same type of read or write in the same time period are tightly arranged in a cache queue, so that the commands of the same bank and the same line are not rearranged, the commands are prevented from aging by arranging the commands in time periods, the situation that commands of different lines of the same bank are arranged together is reduced, and further bandwidth waste caused by bank precharge and activation time generated by frequent line address switching is reduced.
4. The DDR3 controller based on DFI standard of claim 1, wherein said grouping and ID tag module is specifically:
the read-write commands of all banks are grouped according to the sequence of the requests, the read-write commands of the same Bank are not distributed beyond groups, a plurality of read commands are divided into the same group on the premise that the read-write is not wrong and the number of commands in the group does not exceed a threshold value, and the plurality of write commands are divided into other groups different from the read commands, so that the read-write separation is realized;
the different IDs of the read-write commands are formed, specifically as follows: marking the initial address according to the data storage of the write command to form address information ID specific to the write command, and forming read request sequence ID specific to the read command according to the sequence of the read command; the method comprises the steps that the number of read-write commands sent from a module is counted, and a threshold value is set for commands which can be sent in a single time period to define the sequence ID of all the read-write commands; after the number of the sent read-write commands reaches the threshold limit, the sequence changes, and the sequence is described as the time period transmission change of command request transmission.
5. The DDR3 controller based on DFI standard of claim 1, wherein all commands in the command sending module queue are input to parallel signals of the DFI interface module according to a certain contention principle, the number of parallel signals is determined according to the ratio of the DDR3 controller clock frequency to the DDR3 granule working clock frequency and the number of DDR command types, so that the signal quantity sent by the DDR3 controller in a unit cycle can meet the signal quantity that can be processed by the DDR3 granule in a plurality of cycles of the same time under the working frequency, thereby realizing bandwidth matching, and simultaneously, by monitoring the command mapping DDR3 granule internal bank precharge and activation state sent to the DFI interface module, checking whether all commands in the queue can meet the timing requirement of the DDR3 command sent by the DDR3 granule working clock in a plurality of cycles according to the timing sequence, and marking the cycle position of the DDR3 granule working clock where each command is met; when a plurality of instructions capable of meeting the requirements request the same signal line, the priority determined by the delay aging period of the instructions and the queue position to which the instructions belong is used for determining which signal can acquire the signal line occupation weight through competition and then is sent to the DFI interface module.
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| CN113032303A (en) * | 2021-04-25 | 2021-06-25 | 无锡芯思维科技有限公司 | DDR4SDRAM access efficiency optimization method in FPGA |
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| CN113553277B (en) * | 2021-06-24 | 2023-06-09 | 西安电子科技大学 | DDR5SDRAM high throughput rate and low delay PHY interface circuit device |
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| CN114721722B (en) * | 2022-06-06 | 2022-09-02 | 深流微智能科技(深圳)有限公司 | Multi-level cache system and electronic device |
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| CN115834643B (en) * | 2023-02-20 | 2023-05-02 | 广州机智云物联网科技有限公司 | System and method for data intercommunication of Internet of things equipment |
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