CN111949391A - Timer implementation method, device, equipment and storage medium based on multi-core architecture - Google Patents
Timer implementation method, device, equipment and storage medium based on multi-core architecture Download PDFInfo
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- CN111949391A CN111949391A CN202010866664.1A CN202010866664A CN111949391A CN 111949391 A CN111949391 A CN 111949391A CN 202010866664 A CN202010866664 A CN 202010866664A CN 111949391 A CN111949391 A CN 111949391A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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Abstract
The application provides a method, a device, equipment and a storage medium for realizing a timer based on a multi-core architecture, wherein the method for realizing the timer based on the multi-core architecture comprises the following steps: when a timer event is triggered, a timer node is established; adding the timer node into the timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is arranged in the timer queue in a heap mode; calculating to obtain a forwarding period, and detecting whether an overtime timer node exists in a timer queue according to the creation time of a timer event and the overtime period of the timer event in the forwarding period; when an overtime timer node exists in the timer queue, executing an overtime task according to task information of the overtime timer node; and executing the data forwarding task after the overtime task is executed. The method and the device can realize the function of the timer without reducing the system performance of the multi-core architecture, particularly the computing performance of the multi-core architecture.
Description
Technical Field
The present application relates to the field of artificial intelligence, and in particular, to a method, an apparatus, a device, and a storage medium for implementing a timer based on a multi-core architecture.
Background
At present, network attacks are increasing, and a great number of network security devices are developed and applied to practical environments. On the other hand, with the current rich and diverse applications and the popularization of networks, the performance requirements on network security devices are higher and higher, and therefore, in order to adapt to the change of the current requirements, the architecture of network security products is also changed greatly, that is, from the traditional system security engine and the sending and receiving packets are processed by a single cpu, the cpu resources are not distinguished, the architecture evolves to the case that a plurality of cpus concurrently process data at the same time and each cpu generally performs data forwarding in a dead-cycle manner.
However, the evolved multi-core forwarding architecture has the following defects: when the timer is implemented by using an interrupt or semaphore, the forwarding efficiency of the multi-core forwarding architecture is greatly reduced.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, a device, and a storage medium for implementing a timer based on a multi-core architecture, so as to implement a function of the timer without reducing system performance of the multi-core architecture, especially without reducing computing performance of the multi-core architecture.
Therefore, the application provides a timer implementation method based on a multi-core architecture, and the method comprises the following steps:
when a timer event is triggered, creating a timer node, wherein the timer node comprises creation time of the timer event, an overtime period of the timer event and task information of the timer event;
adding the timer node into a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is stacked in the timer queue;
calculating to obtain a forwarding period;
detecting whether an overtime timer node exists in the timer queue or not according to the creation time of the timer event and the overtime period of the timer event in the forwarding period;
when the timer node exists in the timer queue, executing an overtime task according to the task information of the overtime timer node;
and executing the data forwarding task after the overtime task is executed.
In the embodiment of the application, the timer node is placed in the timer queue, and the problem of low system performance caused by using a semaphore mode or an interrupt mode can be avoided according to the judgment result of the overtime timer node in the timer queue in the forwarding period, so that the multi-core architecture can be ensured to process a large amount of data at a high speed.
In the first aspect of the present application, as an optional implementation manner, after the executing a timeout task according to the task information of the timeout timer node and before the executing a data forwarding task, the method further includes:
deleting the timeout timer node from the timer queue;
and when the deletion of the overtime timer node is completed, adjusting the sequence of the nodes in the timer queue so as to enable the node which is overtime firstly in the next forwarding period to be positioned at the top of the stack in the timer queue.
In this optional embodiment, after the execution of the timeout task is completed, the timeout timer node corresponding to the timeout task is deleted from the timer queue, which can ensure that the first timeout timer node is stored at the top of the heap in the timer queue, so that the first timeout timer node can be processed in time in the next forwarding period.
In the first aspect of the present application, as an optional implementation manner, the calculating a forwarding period includes:
acquiring the total data forwarding times from a first time point to a second time point;
and when the interval from the first time point to the second time point meets a preset condition, calculating to obtain the forwarding period according to the interval from the first time point to the second time point and the total data forwarding times.
In this optional embodiment, when the interval from the first time point to the second time point satisfies the preset condition, the forwarding period may be calculated according to the interval from the first time point to the second time point and the total number of data forwarding times in the period from the first time point to the second time point.
In the first aspect of the present application, as an optional implementation manner, the calculation formula of the forwarding period obtained by calculating according to the interval from the first time point to the second time point and the total number of data forwarding times is:
y＝[a/c]；
wherein y represents the forwarding period, a represents an interval from the first time point to the second time point, c represents the total number of times of data forwarding, and "[ ]" represents rounding the result of a/c.
In this alternative embodiment, the forwarding period may be calculated by the calculation formula y ═ a/c.
In the first aspect of the present application, as an optional implementation manner, the preset condition is:
a2-a1>100s；
where a2 denotes the second time point and a1 denotes the first time point.
In this alternative embodiment, by the preset condition of a2-a1>100s, it is possible to avoid obtaining a misaligned time point, and thus avoid calculating a wrong forwarding cycle.
In the first aspect of the present application, as an optional implementation manner, the adding the timer node to a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is arranged in the timer queue includes:
calculating to obtain an expiration time point of the timer event according to the creation time of the timer event and the timeout period of the timer event;
and judging whether the timer event is earlier than the node in the timer queue to be overtime according to the time point of the expiration of the timer event, and if so, piling the timer event at the top of the timer queue.
In this optional embodiment, when creating a new timer node, if the new timer node is timed out first, the new timer node is placed at the top of the heap of the timer node, so that it can also be ensured that, in the stage of creating the timer node, the timer node that is timed out first is located at the top of the heap of the timer node.
In the first aspect of the present application, as an optional implementation manner, the detecting, in the forwarding period, whether there is a timeout timer node in the timer queue according to the creation time of the timer event and the timeout period of the timer event includes:
acquiring current system time;
calculating a difference between the current system time and the creation time of the timer event;
and comparing the difference with the overtime period of the timer event, and if the difference is greater than or equal to the overtime period of the timer event, determining that an overtime timer node exists in the timer queue.
In this optional embodiment, it may be determined whether a timer node corresponding to one timer event is an overtime timer node according to the current system time, the timeout period of the timer event, and the creation time of the timer event.
A second aspect of the present application discloses a timer implementation apparatus based on a multi-core architecture, the apparatus including:
the system comprises a creating module and a processing module, wherein the creating module is used for creating a timer node when a timer event is triggered, and the timer node comprises creation time of the timer event, an overtime period of the timer event and task information of the timer event;
a stacking module, configured to add the timer node into a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is stacked in the timer queue;
the first calculation module is used for calculating to obtain a forwarding period;
a detection module, configured to detect whether an overtime timer node exists in the timer queue according to the creation time of the timer event and the timeout period of the timer event in the forwarding period;
the first task execution module is used for executing an overtime task according to the task information of the overtime timer node when the timer node exists in the timer queue;
and the second task execution module is used for executing the data forwarding task after the overtime task is finished.
The multi-core architecture-based timer implementation apparatus disclosed in the second aspect of the present application can place the timer node in the timer queue by executing the multi-core architecture-based timer implementation method, and can avoid the problem of low system performance caused by using a semaphore manner or an interrupt manner by using a determination result of an overtime timer node in the timer queue in a forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
A third aspect of the present application discloses a multi-core architecture based timer implementation apparatus, including:
a processor; and
a memory configured to store machine readable instructions that, when executed by the processor, perform a multi-core architecture based timer implementation of the first aspect of the present application.
The device of the third aspect of the present application, by executing the method for implementing a timer based on a multi-core architecture, may place a timer node in a timer queue, and may avoid the problem of low system performance caused by using a semaphore mode or an interrupt mode, according to a determination result of an overtime timer node in the timer queue in a forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
A fourth aspect of the present application discloses a storage medium, where the storage medium stores a computer program, and the computer program executes the method for implementing a multi-core architecture-based timer according to the first aspect of the present application when running.
The storage medium according to the fourth aspect of the present application, by executing the method for implementing a timer based on a multi-core architecture, can place a timer node in a timer queue, and can avoid the problem of low system performance caused by using a semaphore mode or an interrupt mode by using a determination result of an overtime timer node in the timer queue in a forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a flowchart illustrating a method for implementing a timer based on a multi-core architecture according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of sub-steps of step 102 of FIG. 1;
FIG. 3 is a schematic flow chart of sub-steps of step 104 of FIG. 1;
FIG. 4 is a schematic structural diagram illustrating an apparatus for implementing a timer based on a multi-core architecture according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a multi-core architecture based timer implementation device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Prior to describing embodiments of the present application in detail, a description of related art is provided.
With the increase of data volume, the processing performance of cpus is required to be higher and higher, so in order to improve the processing capacity of data volume, in the prior art, a multi-core architecture composed of a plurality of cpus is generally adopted to process mass data.
Further, the multi-core architecture may relate to cooperative work of cpus, and at present, the cooperative work of multiple cpus is mainly achieved through cooperation before multiple processes, and more specifically, the cooperation among multiple processes is achieved in a semaphore manner, where when each process is switched to an execution state, operations such as modification of semaphores may be performed. Further, since the time of each process in the execution state is limited, one process is switched out, but the semaphore is not modified, and the next process is affected on the operation of the semaphore, so that the semaphore is mistaken.
In view of the above problems, the multi-core system in the prior art adopts a solution that when a process is switched out and a signal is modified, a next process is switched to an execution state, that is, the next process needs to wait, so that the performance of the multi-core architecture is reduced, and particularly, the computing capability is reduced.
Based on the above description, the embodiments of the present application are described below.
Example one
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for implementing a timer based on a multi-core architecture according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
101. when a timer event is triggered, a timer node is created, wherein the timer node comprises creation time of the timer event, an overtime period of the timer event and task information of the timer event;
102. adding the timer node into the timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is arranged in the timer queue in a heap mode;
103. calculating to obtain a forwarding period;
104. detecting whether an overtime timer node exists in a timer queue or not according to the creation time of the timer event and the overtime period of the timer event in a forwarding period;
105. when a timer node exists in the timer queue, executing an overtime task according to task information of the overtime timer node;
106. and executing the data forwarding task after the overtime task is executed.
In the embodiment of the application, the timer node is placed in the timer queue, and the problem of low system performance caused by using a semaphore mode or an interrupt mode can be avoided according to the judgment result of the overtime timer node in the timer queue in the forwarding period, so that the multi-core architecture can be ensured to process a large amount of data at a high speed.
Compared with the prior art, the method of the embodiment of the application places the timer nodes in the timer queue, periodically judges whether the timer queue has the overtime timer nodes or not by taking one forwarding period as a unit, and executes the overtime task if the timer queue has the overtime timer nodes, so that the application can realize high-speed data processing in a dead-cycle mode without the help of semaphores, and the timing function is realized.
It should be noted that the embodiment of the present application is applicable to processing a fixed data forwarding task, where the fixed data forwarding task refers to that a system processes one data forwarding task with a relatively fixed forwarding period, so that the relatively fixed forwarding period can be calculated, and if the fixed data forwarding task is not processed, the forwarding periods of different data forwarding tasks are different, and thus the relatively fixed forwarding period cannot be calculated.
In the embodiment of the present application, as an optional implementation manner, in step 105: after executing the timeout task according to the task information of the timeout timer node and before executing the data forwarding task in step 106, the method according to the embodiment of the present application further includes the steps of:
deleting the overtime timer node from the timer queue;
and when the deletion of the overtime timer node is completed, adjusting the sequence of the nodes in the timer queue so as to enable the node which is overtime firstly in the next forwarding period to be positioned at the top of the heap in the timer queue.
In this optional embodiment, after the execution of the timeout task is completed, the timeout timer node corresponding to the timeout task is deleted from the timer queue, which can ensure that the first timeout timer node is stored at the top of the heap in the timer queue, so that the first timeout timer node can be processed in time in the next forwarding period.
In the embodiment of the present application, as an optional implementation manner, step 103: calculating to obtain a forwarding period, comprising the following substeps:
acquiring the total data forwarding times from a first time point to a second time point;
and when the interval from the first time point to the second time point meets the preset condition, calculating to obtain a forwarding period according to the interval from the first time point to the second time point and the total data forwarding times.
In this optional embodiment, when the interval from the first time point to the second time point satisfies the preset condition, the forwarding period may be calculated according to the interval from the first time point to the second time point and the total number of data forwarding times in the period from the first time point to the second time point.
In the embodiment of the present application, as an optional implementation manner, the steps of: calculating the forwarding period according to the interval from the first time point to the second time point and the total data forwarding times to obtain a calculation formula:
y＝[a/c]；
wherein y represents a forwarding period, a represents an interval from a first time point to a second time point, c represents a total number of data forwarding, and "[ ]" represents rounding the result of a/c.
In this alternative embodiment, the forwarding period may be calculated by the calculation formula y ═ a/c.
In the embodiment of the present application, as an optional implementation manner, the preset condition is:
a2-a1>100s；
where a2 denotes the second time point and a1 denotes the first time point.
In this alternative embodiment, by the preset condition of a2-a1>100s, it is possible to avoid obtaining a misaligned time point, and thus avoid calculating a wrong forwarding cycle.
In the embodiment of the present application, as an alternative implementation, as shown in fig. 2, step 102: adding a timer node to a timer queue according to a creation time of the timer event and a timeout period of the timer event such that a timer node stack is queued in the timer queue, comprising the substeps of:
1021. calculating to obtain an overdue time point of the timer event according to the creation time of the timer event and the overtime period of the timer event;
1022. and judging whether the timer event is overtime before the node in the timer queue according to the overtime time point of the timer event, and if so, stacking the timer event on the top of the timer queue.
In this optional embodiment, when creating a new timer node, if the new timer node is timed out first, the new timer node is placed at the top of the heap of the timer node, so that it can also be ensured that, in the stage of creating the timer node, the timer node that is timed out first is located at the top of the heap of the timer node.
In the embodiment of the present application, as an alternative implementation, as shown in fig. 3, step 104: detecting whether a timeout timer node exists in a timer queue according to the creation time of a timer event and the timeout period of the timer event in a forwarding period, comprising the substeps of:
1041. acquiring current system time;
1042. calculating a difference between the current system time and the creation time of the timer event;
1043. and comparing the difference with the overtime period of the timer event, and if the difference is greater than or equal to the overtime period of the timer event, determining that an overtime timer node exists in the timer queue.
In this optional embodiment, it may be determined whether a timer node corresponding to one timer event is an overtime timer node according to the current system time, the timeout period of the timer event, and the creation time of the timer event.
Example two
Referring to fig. 4, fig. 4 is a flowchart illustrating an apparatus for implementing a timer based on a multi-core architecture according to an embodiment of the present application. As shown in fig. 4, the apparatus includes:
a creating module 201, configured to create a timer node when a timer event is triggered, where the timer node includes creation time of the timer event, an timeout period of the timer event, and task information of the timer event;
a stacking module 202, configured to add a timer node into a timer queue according to a creation time of the timer event and an timeout period of the timer event, so that the timer node is stacked in the timer queue;
the first calculation module 203 is configured to calculate a forwarding period;
a detecting module 204, configured to detect whether an overtime timer node exists in a timer queue according to creation time of a timer event and an overtime period of the timer event in a forwarding period;
a first task executing module 205, configured to execute an overtime task according to task information of an overtime timer node when the timer node exists in the timer queue;
and a second task execution module 206, configured to execute the data forwarding task after the timeout task is completed.
The multi-core architecture-based timer implementation device disclosed in the embodiment of the present application can place the timer node in the timer queue by executing the multi-core architecture-based timer implementation method, and can avoid the problem of low system performance caused by using a semaphore manner or an interrupt manner by using a determination result of an overtime timer node in the timer queue in a forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
Compared with the prior art, the device disclosed by the embodiment of the application places the timer nodes in the timer queue, periodically judges whether the timer queue has the overtime timer nodes or not by taking one forwarding period as a unit, and executes an overtime task if the timer queue has the overtime timer nodes, so that the application can realize high-speed data processing in a dead-cycle mode without the help of semaphores, and the timing function is realized.
It should be noted that the embodiment of the present application is applicable to processing a fixed data forwarding task, where the fixed data forwarding task refers to that a system processes one data forwarding task with a relatively fixed forwarding period, so that the relatively fixed forwarding period can be calculated, and if the fixed data forwarding task is not processed, the forwarding periods of different data forwarding tasks are different, and thus the relatively fixed forwarding period cannot be calculated.
In this embodiment of the present application, as an optional implementation manner, the apparatus of this embodiment of the present application further includes:
the deleting module is used for deleting the overtime timer node from the timer queue;
and the adjusting module is used for adjusting the sequence of the nodes in the timer queue when the deletion of the overtime timer node is completed, so that the node which is overtime firstly in the next forwarding period is positioned at the top of the heap in the timer queue.
In this optional embodiment, after the execution of the timeout task is completed, the timeout timer node corresponding to the timeout task is deleted from the timer queue, which can ensure that the first timeout timer node is stored at the top of the heap in the timer queue, so that the first timeout timer node can be processed in time in the next forwarding period.
In this embodiment of the present application, as an optional implementation manner, a specific manner in which the first calculation module 203 performs the calculation to obtain the forwarding period is as follows:
acquiring the total data forwarding times from a first time point to a second time point;
and when the interval from the first time point to the second time point meets the preset condition, calculating to obtain a forwarding period according to the interval from the first time point to the second time point and the total data forwarding times.
In this optional embodiment, when the interval from the first time point to the second time point satisfies the preset condition, the forwarding period may be calculated according to the interval from the first time point to the second time point and the total number of data forwarding times in the period from the first time point to the second time point.
In this embodiment of the present application, as an optional implementation manner, a calculation formula of a forwarding period obtained by calculating according to an interval from a first time point to a second time point and a total number of data forwarding times is:
y＝[a/c]；
wherein y represents a forwarding period, a represents an interval from a first time point to a second time point, c represents a total number of data forwarding, and "[ ]" represents rounding the result of a/c.
In this alternative embodiment, the forwarding period may be calculated by the calculation formula y ═ a/c.
In the embodiment of the present application, as an optional implementation manner, the preset condition is:
a2-a1>100s；
where a2 denotes the second time point and a1 denotes the first time point.
In this alternative embodiment, by the preset condition of a2-a1>100s, it is possible to avoid obtaining a misaligned time point, and thus avoid calculating a wrong forwarding cycle.
In this embodiment of the present application, as an optional implementation manner, the stacking module 202 performs a specific manner of adding a timer node into a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is stacked in the timer queue:
calculating to obtain an overdue time point of the timer event according to the creation time of the timer event and the overtime period of the timer event;
and judging whether the timer event is overtime before the node in the timer queue according to the overtime time point of the timer event, and if so, stacking the timer event on the top of the timer queue.
In this optional embodiment, when creating a new timer node, if the new timer node is timed out first, the new timer node is placed at the top of the heap of the timer node, so that it can also be ensured that, in the stage of creating the timer node, the timer node that is timed out first is located at the top of the heap of the timer node.
In this embodiment of the present application, as an optional implementation manner, a specific way for the detecting module 204 to detect whether there is a timeout timer node in the timer queue according to the creation time of the timer event and the timeout period of the timer event in the forwarding period is as follows:
acquiring current system time;
calculating a difference between the current system time and the creation time of the timer event;
and comparing the difference with the overtime period of the timer event, and if the difference is greater than or equal to the overtime period of the timer event, determining that an overtime timer node exists in the timer queue.
In this optional embodiment, it may be determined whether a timer node corresponding to one timer event is an overtime timer node according to the current system time, the timeout period of the timer event, and the creation time of the timer event.
EXAMPLE III
Referring to fig. 5, fig. 5 is a schematic structural diagram of a multi-core architecture based timer implementation device according to an embodiment of the present application. As shown in fig. 5, the apparatus includes:
a processor 301; and
the memory 302 is configured to store machine-readable instructions, and when the instructions are executed by the processor 301, the method for implementing the multi-core architecture-based timer according to the first embodiment of the present application is performed.
The device of the embodiment of the application can place the timer node into the timer queue by executing the timer implementation method based on the multi-core architecture, and can avoid the problem of low system performance caused by a semaphore mode or an interrupt mode by the judgment result of the overtime timer node in the timer queue in the forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
Example four
The embodiment of the application discloses a storage medium, wherein a computer program is stored in the storage medium, and the computer program executes the multi-core architecture-based timer implementation method in the embodiment of the application when running.
The storage medium of the embodiment of the application can place the timer node into the timer queue by executing the method for implementing the timer based on the multi-core architecture, and can avoid the problem of low system performance caused by a semaphore mode or an interrupt mode by using a judgment result of an overtime timer node in the timer queue in a forwarding period, thereby ensuring that the multi-core architecture can process a large amount of data at a high speed.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
It should be noted that the functions, if implemented in the form of software functional modules and sold or used as independent products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for implementing a timer based on a multi-core architecture is characterized by comprising the following steps:
when a timer event is triggered, creating a timer node, wherein the timer node comprises creation time of the timer event, an overtime period of the timer event and task information of the timer event;
adding the timer node into a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is stacked in the timer queue;
calculating to obtain a forwarding period;
detecting whether an overtime timer node exists in the timer queue or not according to the creation time of the timer event and the overtime period of the timer event in the forwarding period;
when the overtime timer node exists in the timer queue, executing an overtime task according to the task information of the overtime timer node;
and executing the data forwarding task after the overtime task is executed.
2. The method of claim 1, wherein after the performing a timeout task according to the task information of the timeout timer node and before the performing a data forwarding task, the method further comprises:
deleting the timeout timer node from the timer queue;
and when the deletion of the overtime timer node is completed, adjusting the sequence of the nodes in the timer queue so as to enable the node which is overtime firstly in the next forwarding period to be positioned at the top of the stack in the timer queue.
3. The method of claim 1, wherein the calculating a forwarding period comprises:
acquiring the total data forwarding times from a first time point to a second time point;
and when the interval from the first time point to the second time point meets a preset condition, calculating to obtain the forwarding period according to the interval from the first time point to the second time point and the total data forwarding times.
4. The method according to claim 3, wherein the calculation formula for calculating the forwarding period according to the interval from the first time point to the second time point and the total number of data forwarding times is:
y＝[a/c]；
wherein y represents the forwarding period, a represents an interval from the first time point to the second time point, c represents the total number of times of data forwarding, and "[ ]" represents rounding the result of a/c.
5. The method of claim 4, wherein the preset condition is:
a2-a1>100s；
where a2 denotes the second time point and a1 denotes the first time point.
6. The method of claim 1, wherein said adding the timer node to a timer queue based on a creation time of the timer event and a timeout period of the timer event to cause the timer node to be queued in the timer queue comprises:
calculating to obtain an expiration time point of the timer event according to the creation time of the timer event and the timeout period of the timer event;
and judging whether the timer event is earlier than the node in the timer queue to be overtime according to the time point of the expiration of the timer event, and if so, piling the timer event at the top of the timer queue.
7. The method of claim 1, wherein the detecting whether a timeout timer node exists in the timer queue according to the creation time of the timer event and the timeout period of the timer event within the forwarding period s comprises:
acquiring current system time;
calculating a difference between the current system time and the creation time of the timer event;
and comparing the difference with the overtime period of the timer event, and if the difference is greater than or equal to the overtime period of the timer event, determining that an overtime timer node exists in the timer queue.
8. An apparatus for implementing a timer based on a multi-core architecture, the apparatus comprising:
the system comprises a creating module and a processing module, wherein the creating module is used for creating a timer node when a timer event is triggered, and the timer node comprises creation time of the timer event, an overtime period of the timer event and task information of the timer event;
a stacking module, configured to add the timer node into a timer queue according to the creation time of the timer event and the timeout period of the timer event, so that the timer node is stacked in the timer queue;
the first calculation module is used for calculating to obtain a forwarding period;
a detection module, configured to detect whether an overtime timer node exists in the timer queue according to the creation time of the timer event and the timeout period of the timer event in the forwarding period;
the first task execution module is used for executing an overtime task according to the task information of the overtime timer node when the timer node exists in the timer queue;
and the second task execution module is used for executing the data forwarding task after the overtime task is finished.
9. A multi-core architecture based timer implementation device, comprising:
a processor; and
a memory configured to store machine readable instructions that, when executed by the processor, perform the multi-core architecture based timer implementation method of any of claims 1-7.
10. A storage medium storing a computer program, wherein the computer program is operable to perform the multi-core architecture based timer implementation method according to any of claims 1-7.
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