CN111949203B - Memory, control method and control device thereof - Google Patents
Memory, control method and control device thereof Download PDFInfo
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- CN111949203B CN111949203B CN201910414905.6A CN201910414905A CN111949203B CN 111949203 B CN111949203 B CN 111949203B CN 201910414905 A CN201910414905 A CN 201910414905A CN 111949203 B CN111949203 B CN 111949203B
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000013507 mapping Methods 0.000 claims abstract description 98
- 239000000872 buffer Substances 0.000 claims description 31
- 238000012790 confirmation Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a memory, a control method and a control device thereof. The control method of the memory comprises the following steps: receiving a first operation command, and determining a first read-write mode corresponding to the first operation command, wherein the first read-write mode is continuous read-write or random read-write; and determining a mapping mode corresponding to the first read-write mode as a target mapping mode to execute the first operation command. The memory control method provided by the embodiment of the invention has the advantages of high read-write speed and small occupied space.
Description
Technical Field
Embodiments of the present invention relate to data storage technologies, and in particular, to a memory, a control method thereof, and a control device thereof.
Background
An embedded multimedia card (eMMC, embedded Multi Media Card) is a main storage device in mobile terminals such as mobile phones and tablet computers, and uses a NAND flash memory as a storage medium to store software, data, and the like in the mobile terminal.
Existing eMMC firmware all employ a single mapping, such as a block mapping or page mapping. The block mapping is suitable for continuous reading and writing, and the continuous reading and writing performance is better by using the block mapping because the data volume of the continuous reading and writing is larger and is an integral multiple of the block capacity; however, since the random read/write has a small data size and a non-aligned page capacity, a large amount of space is wasted in the mapping relationship in units of blocks. The page mapping is suitable for random reading and writing, and does not occupy excessive space; however, for continuous reading and writing, a large amount of data is read and written in units of pages, which results in a longer reading and writing time and reduced reading and writing performance.
Disclosure of Invention
The invention provides a memory, a control method and a control device thereof, so as to realize high reading and writing speed and small occupied space.
In a first aspect, an embodiment of the present invention provides a method for controlling a memory, including:
receiving a first operation command, and determining a first read-write mode corresponding to the first operation command, wherein the first read-write mode is continuous read-write or random read-write;
and determining a mapping mode corresponding to the first read-write mode as a target mapping mode to execute the first operation command.
Optionally, determining the mapping manner corresponding to the first read-write mode as the target mapping manner to execute the first operation command includes:
if the first read-write mode is continuous read-write, determining a block unit mapping as a target mapping mode corresponding to the continuous read-write mode and executing the first operation command by adopting the block unit mapping;
and if the first read-write mode is random read-write, determining a page unit mapping as a target mapping mode corresponding to the random read-write mode and executing the first operation command by adopting the page unit mapping.
Optionally, the memory includes a storage module, the storage module including a plurality of physical blocks;
receiving a first operation command and determining a first read-write mode corresponding to the first operation command includes:
determining a first operation data amount corresponding to the first operation command according to the first operation command;
if the first operation data amount is detected to be larger than or equal to the first data amount, judging that a first read-write mode corresponding to the first operation command is continuous read-write;
and if the first operation data amount is detected to be smaller than the first data amount, judging that the first read-write mode corresponding to the first operation command is random read-write.
Optionally, the first data amount is 1/4 of the rated capacity of the physical block.
In a second aspect, an embodiment of the present invention further provides a control device for a memory, including:
the command acquisition module is used for receiving a first operation command and determining a first read-write mode corresponding to the first operation command, wherein the first read-write mode is continuous read-write or random read-write;
and the determining module is used for determining a mapping mode corresponding to the first read-write mode as a target mapping mode so as to execute the first operation command.
Optionally, the determining module includes:
a first confirmation unit configured to determine a block unit map as a target mapping manner corresponding to a continuous read-write if the first read-write mode is the continuous read-write mode and execute the first operation command using the block unit map;
and a second confirmation unit configured to determine a page unit mapping as a target mapping manner corresponding to the random read-write and execute the first operation command using the page unit mapping if the first read-write mode is random read-write.
Optionally, the memory includes a storage module, the storage module including a plurality of physical blocks;
the command acquisition module includes:
a data amount obtaining unit, configured to determine a first operation data amount corresponding to the first operation command according to the first operation command;
a first determining unit, configured to determine that a first read-write mode corresponding to the first operation command is continuous read-write if the first operation data amount is detected to be greater than or equal to a first data amount;
and the second judging unit judges that the first read-write mode corresponding to the first operation command is random read-write if the first operation data amount is detected to be smaller than the first data amount.
Optionally, the first data amount is 1/4 of the rated capacity of the physical block.
In a third aspect, an embodiment of the present invention further provides a memory, including any one of the control devices described in the second aspect.
The technical scheme provided by the embodiment of the invention adopts a hybrid mapping mechanism, and adopts different mapping modes for continuous reading and writing and random reading and writing, so that the problems of long reading and writing time or excessive space occupation caused by single mapping in the prior art are solved, and the effects of high speed during continuous reading and writing and small space occupation during random reading and writing are realized.
Drawings
Fig. 1 is a flow chart of a method for controlling a memory according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another method for controlling a memory according to an embodiment of the present invention;
FIG. 3 is a flow chart illustrating the execution of a first operation command;
fig. 4 is a schematic structural diagram of a memory control device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a flow chart of a method for controlling a memory according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps:
step 110, receiving a first operation command, and determining a first read-write mode corresponding to the first operation command, where the first read-write mode is continuous read-write or random read-write.
And 120, determining a mapping mode corresponding to the first read-write mode as a target mapping mode to execute the first operation command.
The technical scheme provided by the embodiment of the invention adopts a hybrid Mapping mechanism (Block-Page Mapping), and adopts different Mapping modes for continuous reading and writing and random reading and writing, so that the problems of long reading and writing time or excessive space occupation caused by single Mapping in the prior art are solved, and the effects of high speed in continuous reading and writing and small space occupation in random reading and writing are realized.
Fig. 2 is a flow chart of another method for controlling a memory according to an embodiment of the present invention, where step 110 and step 120 are further refined based on the technical solution provided in the previous embodiment, and explanations of terms identical to or corresponding to the above embodiments are not repeated herein.
Optionally, receiving the first operation command and determining the first read-write mode corresponding to the first operation command includes:
and determining a first operation data amount corresponding to the first operation command according to the first operation command.
And if the first operation data amount is detected to be larger than or equal to the first data amount, judging that the first read-write mode corresponding to the first operation command is continuous read-write.
And if the first operation data amount is detected to be smaller than the first data amount, judging that the first read-write mode corresponding to the first operation command is random read-write.
Optionally, determining the mapping manner corresponding to the first read-write mode as the target mapping manner to execute the first operation command includes:
and if the first read-write mode is continuous read-write, determining a block unit mapping as a target mapping mode corresponding to the continuous read-write mode and executing the first operation command by adopting the block unit mapping.
And if the first read-write mode is random read-write, determining a page unit mapping as a target mapping mode corresponding to the random read-write mode and executing the first operation command by adopting the page unit mapping.
Based on the above refinement, as shown in fig. 2, the method for controlling a memory according to the embodiment of the present invention may include the following steps:
step 210, determining a first operation data amount corresponding to the first operation command according to the first operation command.
Step 220, if the first operation data amount is detected to be greater than or equal to the first data amount, determining that the first read-write mode corresponding to the first operation command is continuous read-write.
Step 230, if the first operation data amount is detected to be smaller than the first data amount, determining that the first read-write mode corresponding to the first operation command is random read-write.
Step 240, if the first read-write mode is continuous read-write, determining a block unit mapping as a target mapping mode corresponding to the continuous read-write mode and executing the first operation command by using the block unit mapping.
Step 250, if the first read-write mode is random read-write, determining a page unit mapping as a target mapping mode corresponding to the random read-write mode and executing the first operation command by using the page unit mapping.
The memory receives a first operation command sent by the host, and determines a first operation data amount corresponding to the first operation command according to the first operation command. And detecting that the first operation data amount is larger than the first data amount, so as to judge that the first read-write mode corresponding to the first operation command is continuous read-write. And further determining the block unit mapping as a target mapping mode corresponding to the continuous reading and writing, and executing the first operation command by adopting the block unit mapping. Fig. 3 is a schematic flow chart of executing the first operation command, and as shown in fig. 3, when the first operation command is executed by using block unit mapping, the memory uses 32 sequential buffers (Sequential Buffer) to execute the first operation command. The memory includes a memory module including a plurality of Physical blocks 330 (Physical blocks); the storage module further includes an address Mapping table reserved area, where the address Mapping table reserved area is used to build an address Mapping table 320 (Mapping Tables), and the address Mapping table 320 is used to store a Mapping relationship between a Logical address of the Logical Block 310 (Logical Block) and a physical address of the physical Block 330. The first operation command includes writing and reading, and if the first operation command is writing, the memory selects unoccupied buffers (Sequential Buffer Idx) from the 32 buffers Sequential Buffer as a Block Mapping relationship (Block Mapping), where the Block Mapping relationship includes address Mapping relationships related to reading and writing, such as a New Block (New Block) and an Old Block (Old Block). The first time the memory will fetch a Block from the Free Block (Free Block) as the New Block of the unoccupied buffer, e.g. Physical Block Number (PBN) 1001 physical Block, into which data is written via the sequential buffer channel (Sequential Buffer Entry). If the New Block is full, the memory will convert it to an item Block (Entry Block), then the Block will be converted to an Old Block, then reassigned Sequential Buffer when re-written, continue to select a Block from Free Block as the New Block of Sequential Buffer, then assign and write, and so on. If the first operation command is read, the memory first confirms whether Sequential Buffer exists, if Sequential Buffer exists, then continues to judge whether the data is in the New Block of Sequential Buffer, if the data is in the New Block of Sequential Buffer, the data is read out from the Block through the address information and other information recorded in the New Block; if the data is not in the New Block of Sequential Buffer, the data is inevitably in the Old Block, and the data is read from the Block by the address information or the like recorded in the Old Block. If Sequential Buffer is not present, the data must be read in the Entry Block, and the amount of data to be read is an integer multiple of the Block size, and at this time, the data is read from the Block by the address information recorded in the Entry Block.
In the technical solution provided in this embodiment, step 220 and step 230 have no sequence requirement, step 240 and step 250 have no sequence requirement, and those skilled in the art can change the sequence without departing from the scope of the present invention.
Optionally, the memory includes a storage module, the storage module including a plurality of physical blocks; the first data amount is 1/4 of the rated capacity of the physical block. Wherein, a threshold value can be set in the firmware of the memory to be 1/4 of the rated capacity of the physical block, the first data volume is set to be too large, and the continuous read-write with larger data volume is easily judged to be random read-write, so that the first operation command is executed by adopting page unit mapping, and the read-write time is long; the first data size is set to be too small, so that random reading and writing with smaller data size is easily judged to be continuous reading and writing, and therefore the first operation command is executed by adopting block unit mapping, and space waste is caused. Therefore, the embodiment of the invention reasonably sets the first data volume, which not only shortens the reading and writing time, but also avoids the space waste. The memory receives a first operation command sent by the host, and determines a first operation data amount corresponding to the first operation command according to the first operation command. If the first operation data amount is detected to be greater than or equal to 1/4 of the rated capacity of the physical block, the first read-write mode corresponding to the first operation command is judged to be continuous read-write. If the first operation data amount is detected to be smaller than 1/4 of the rated capacity of the physical block, the first read-write mode corresponding to the first operation command is judged to be random read-write.
The technical scheme provided by the embodiment of the invention adopts a hybrid mapping mechanism, and improves the speed of continuous reading and writing by adopting block unit mapping to carry out continuous reading and writing with larger data volume, and adopts page unit mapping to carry out random reading and writing with smaller data volume, so as to save storage space, solve the problems of long reading and writing time or space waste caused by single mapping in the prior art, and realize the effects of high speed and small occupied space during continuous reading and writing.
Based on the same inventive concept, the embodiment of the present invention further provides a control device for a memory, which is the same as or corresponding to the above embodiment, and explanation of terms is not repeated herein, and fig. 4 is a schematic structural diagram of the control device for a memory provided in the embodiment of the present invention, as shown in fig. 4, where the device includes:
a command obtaining module 41, configured to receive a first operation command, and determine a first read-write mode corresponding to the first operation command, where the first read-write mode is continuous read-write or random read-write;
a determining module 42, configured to determine a mapping manner corresponding to the first read-write mode as a target mapping manner to execute the first operation command.
Optionally, the command acquisition module 41 includes:
the data amount obtaining unit 411 is configured to determine, according to the first operation command, a first operation data amount corresponding to the first operation command.
The first determining unit 412 is configured to determine that the first read/write mode corresponding to the first operation command is continuous read/write if the first operation data amount is detected to be greater than or equal to the first data amount.
The second determination unit 413 determines that the first read-write mode corresponding to the first operation command is random read-write if it is detected that the first operation data amount is smaller than the first data amount.
Optionally, the determining module 42 includes:
the first confirmation unit 421 is configured to determine the block unit map as a target map corresponding to the continuous read/write mode and execute the first operation command by using the block unit map if the first read/write mode is the continuous read/write mode.
The second confirmation unit 422 is configured to determine the page unit mapping as a target mapping manner corresponding to the random read-write and execute the first operation command using the page unit mapping if the first read-write mode is the random read-write mode.
Optionally, the memory includes a storage module including a plurality of physical blocks, and the first data amount is 1/4 of a rated capacity of the physical blocks.
The embodiment of the invention synchronously considers two single mappings, namely block unit mapping and page unit mapping, and adopts a hybrid mapping mechanism. The continuous reading and writing with larger data volume is performed by adopting the block unit mapping, so that the speed of continuous reading and writing is improved, and the random reading and writing with smaller data volume is performed by adopting the page unit mapping, so that the storage space is saved, the problems of long reading and writing time or space waste caused by adopting single mapping in the prior art are solved, and the effects of high speed and small occupied space during random reading and writing during continuous reading and writing are realized.
Based on the same inventive concept, the embodiments of the present invention further provide a memory, where the memory includes the control device according to any one of the above embodiments, and explanations of terms identical to or corresponding to those of the above embodiments are not repeated herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (7)
1. A method for controlling a memory, comprising:
receiving a first operation command, and determining a first read-write mode corresponding to the first operation command, wherein the first read-write mode is continuous read-write or random read-write;
determining a mapping manner corresponding to the first read-write mode as a target mapping manner to execute the first operation command, including:
if the first read-write mode is continuous read-write, determining a block unit mapping as a target mapping mode corresponding to the continuous read-write mode and executing the first operation command by adopting the block unit mapping;
if the first read-write mode is random read-write, determining a page unit mapping as a target mapping mode corresponding to the random read-write mode and executing the first operation command by adopting the page unit mapping;
when the first operation command is executed by adopting block unit mapping, the memory adopts a plurality of sequence buffers to execute the first operation command, wherein the first operation command comprises writing and reading;
if the first operation command is writing, the memory selects an unoccupied buffer from a plurality of sequential buffers as a block mapping relation;
if the first operation command is read, the memory firstly confirms whether a sequence buffer exists, if so, judges whether the data is in a new block of the sequence buffer, and if so, reads the data from the new block through address information recorded in the new block;
reading data from an old block by address information recorded in the old block if the data is not in a new block of the sequence buffer;
if there is no sequence buffer, the data is in the project block, the data quantity to be read is integer times of the block capacity, at this time, the data is read out from the project block through the address information recorded in the project block.
2. The control method according to claim 1, wherein the memory includes a memory module including a plurality of physical blocks;
receiving a first operation command and determining a first read-write mode corresponding to the first operation command includes:
determining a first operation data amount corresponding to the first operation command according to the first operation command;
if the first operation data amount is detected to be larger than or equal to the first data amount, judging that a first read-write mode corresponding to the first operation command is continuous read-write;
and if the first operation data amount is detected to be smaller than the first data amount, judging that the first read-write mode corresponding to the first operation command is random read-write.
3. The control method according to claim 2, characterized in that the first data amount is 1/4 of the rated capacity of the physical block.
4. A control device of a memory, comprising:
the command acquisition module is used for receiving a first operation command and determining a first read-write mode corresponding to the first operation command, wherein the first read-write mode is continuous read-write or random read-write;
a determining module, configured to determine a mapping manner corresponding to the first read-write mode as a target mapping manner to execute the first operation command;
the determining module includes:
a first confirmation unit configured to determine a block unit map as a target mapping manner corresponding to a continuous read-write if the first read-write mode is the continuous read-write mode and execute the first operation command using the block unit map;
a second confirmation unit configured to determine a page unit mapping as a target mapping manner corresponding to random read-write if the first read-write mode is random read-write and execute the first operation command using the page unit mapping;
when the first operation command is executed by adopting block unit mapping, the memory adopts a plurality of sequence buffers to execute the first operation command, wherein the first operation command comprises writing and reading;
if the first operation command is writing, the memory selects an unoccupied buffer from a plurality of sequential buffers as a block mapping relation;
if the first operation command is read, the memory firstly confirms whether a sequence buffer exists, if so, judges whether the data is in a new block of the sequence buffer, and if so, reads the data from the new block through address information recorded in the new block;
reading data from an old block by address information recorded in the old block if the data is not in a new block of the sequence buffer;
if there is no sequence buffer, the data is in the project block, the data quantity to be read is integer times of the block capacity, at this time, the data is read out from the project block through the address information recorded in the project block.
5. The control device of claim 4, wherein the memory comprises a memory module comprising a plurality of physical blocks;
the command acquisition module includes:
a data amount obtaining unit, configured to determine a first operation data amount corresponding to the first operation command according to the first operation command;
a first determining unit, configured to determine that a first read-write mode corresponding to the first operation command is continuous read-write if the first operation data amount is detected to be greater than or equal to a first data amount;
and the second judging unit judges that the first read-write mode corresponding to the first operation command is random read-write if the first operation data amount is detected to be smaller than the first data amount.
6. The control device of claim 5, wherein the first amount of data is 1/4 of the physical block rated capacity.
7. A memory comprising the control device of any one of claims 4-6.
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| KR20090098275A (en) * | 2008-03-13 | 2009-09-17 | 주식회사 엠트론스토리지테크놀로지 | Flash memory system |
| CN104424124A (en) * | 2013-09-10 | 2015-03-18 | 联想(北京)有限公司 | Memory device, electronic equipment and method for controlling memory device |
| WO2016194979A1 (en) * | 2015-06-02 | 2016-12-08 | 日本電気株式会社 | Storage system, storage control device, storage control method, and program |
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| US7159068B2 (en) * | 2003-12-22 | 2007-01-02 | Phison Electronics Corp. | Method of optimizing performance of a flash memory |
| KR101289931B1 (en) * | 2011-09-23 | 2013-07-25 | 한양대학교 산학협력단 | Method and apparatus for storing data in flash memory using address mapping with various block sizes |
| US10599333B2 (en) * | 2016-03-09 | 2020-03-24 | Toshiba Memory Corporation | Storage device having dual access procedures |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20090098275A (en) * | 2008-03-13 | 2009-09-17 | 주식회사 엠트론스토리지테크놀로지 | Flash memory system |
| CN104424124A (en) * | 2013-09-10 | 2015-03-18 | 联想(北京)有限公司 | Memory device, electronic equipment and method for controlling memory device |
| WO2016194979A1 (en) * | 2015-06-02 | 2016-12-08 | 日本電気株式会社 | Storage system, storage control device, storage control method, and program |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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