CN111935416A

CN111935416A - Method for storing zoomed image based on FPGA

Info

Publication number: CN111935416A
Application number: CN202010035704.8A
Authority: CN
Inventors: 严飞; 马可; 刘银萍; 夏金锋; 蔡静怡; 孙舒; 陈伟
Original assignee: Nanjing University of Information Science and Technology
Current assignee: Nanjing University of Information Science and Technology
Priority date: 2020-01-14
Filing date: 2020-01-14
Publication date: 2020-11-13

Abstract

The invention discloses a method for storing zoomed images based on an FPGA (field programmable gate array), which comprises the following steps of: (1) initializing an external dynamic random access memory by the FPGA; (2) acquiring an original image from a video source and zooming the original image; (3) caching K bytes of data of the zoomed image into an internal storage FIFO of the FPGA; (4) storing the K bytes of data in the FIFO into an external memory DDR 4; (5) the FIFO reads m storage data from the DDR 4; (6) and reading and displaying the image data. The image data is stored in the DDR4 external memory, so that the use of an on-chip memory of the FPGA is reduced, the image data caching space is increased, and images needing a large amount of caching data can be processed; by adopting the DDR4 with high reading and writing speed, the data loss caused by too low reading speed is avoided, and the image data processing efficiency is improved.

Description

Method for storing zoomed image based on FPGA

Technical Field

The invention relates to a method for storing zoomed images, in particular to a method for storing zoomed images based on an FPGA.

Background

With the requirement for image data quality becoming higher and higher, the original image data needs to be scaled, and at present, the types of algorithms for image scaling are many, but are generally implemented by interpolation algorithms, where the algorithms include: the most used algorithms at present adopt a bilinear interpolation algorithm.

In the prior art, after image data is obtained by using an FPGA through a bilinear interpolation algorithm and is zoomed, the image data is mainly stored in an FIFO (first in first out) in the FPGA, although the reading and writing speed is improved to a certain extent, the FIFO memory in the FPGA is limited, and images needing a large amount of cache data cannot be processed.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a method for storing zoomed images based on FPGA, which is quick and effective and can buffer a large amount of image data.

The technical scheme is as follows: the invention relates to a method for storing zoomed images, which comprises the following steps: (1) initializing an external dynamic random access memory by the FPGA; (2) acquiring an original image from a video source and zooming the original image; (3) caching K bytes of data of the zoomed image into an internal storage FIFO of the FPGA; (4) storing the K bytes of data in the FIFO into an external memory DDR 4; (5) the FIFO reads m storage data from the DDR 4; (6) and reading and displaying the image data.

In the step (2), the original image is zoomed by adopting a bilinear interpolation algorithm.

In the step (3), the zoomed image data is put into K bytes of image cache data to an asynchronous clock FIFO of an internal storage of the FPGA at a preset putting-in speed; counting is carried out when data is put in, when K bytes of data are counted up, a full signal is enabled, a counter is cleared, and when a read empty signal is enabled, counting is carried out again; when detecting that the FIFO full signal is set to be 1, the DDR4 starts to read K bytes of cache data from the asynchronous clock FIFO of the internal memory of the FPGA at a preset reading speed; storing K bytes into FIFO according to preset speed, if the zoomed image data is not enough K bytes, that is, the zoomed image resolution is not integer multiple of K, supplementing q 0 and putting K bytes into FIFO according to preset speed.

The steps for calculating q are as follows:

(3-1) resetting the counter N and the accumulator Y;

(3-2) adding K to the accumulator Y and adding 1 to the counter N;

(3-3) storing the accumulator and counter data in corresponding registers;

and (3-4) comparing Y in the accumulator with the data generated by the multiplier in the comparator.

In the step (4), when detecting that the FIFO full signal is set to 1, the DDR4 starts to read K bytes of cache data from the asynchronous clock FIFO of the FPGA internal memory at a preset reading speed.

In step (5), when the internal memory FIFO needs to read data from the external memory, the asynchronous clock FIFO reads m buffer data from the DDR4 according to a preset reading speed, and the data are buffered in the FIFO.

In the step (6), the display interface of each channel image reads and displays image data from the corresponding buffer FIFO of each channel.

Has the advantages that: compared with the prior art, the invention has the following remarkable effects: 1. the image data is stored in a DDR4 external memory, so that the use of an FPGA on-chip memory is reduced, the image data cache space is increased, and an image which needs a large amount of cache data can be processed; 2. by adopting the DDR4 with high reading and writing speed, the data loss caused by too low reading speed is avoided, and the image data processing efficiency is improved.

Drawings

Fig. 1 is a schematic diagram of image source scaling according to the present invention;

FIG. 2 is a schematic diagram of an image data flow according to the present invention;

FIG. 3 is a flow chart illustrating the calculation of q and N according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the detailed description.

The data storage method of the invention, as shown in fig. 1, comprises the following steps:

(1) the FPGA initializes the external dynamic random access memory and enables the external dynamic random access memory to read data normally.

(2) As shown in fig. 2, the original image resolution is obtained from the video source as W1 × H1, and the original image is scaled by the bilinear interpolation algorithm to W2 × H2.

(3) And (3) putting the zoomed image data into K bytes of image cache data into an asynchronous clock FIFO of an internal storage of the FPGA at a preset putting speed, counting the data at the same time, when the K bytes of data are fully counted, enabling a full signal, resetting the counter, and when a read empty signal is enabled, starting to count again.

And storing the images into the FIFO according to the preset putting speed every time, if the last data of the scaled images W2H 2 is not enough K bytes, namely the resolution of the scaled images W2H 2 is not an integral multiple of K, and supplementing q 0 s to put the K bytes into the FIFO according to the preset putting speed.

As shown in fig. 3, which is an image data stream of the present invention, the q-step is calculated as follows:

(3-1) firstly, resetting the counter N and the accumulator Y;

(3-2) adding K to the accumulator Y and adding 1 to the counter N;

(3-3) storing the accumulator and counter data in corresponding registers;

(3-4) comparing Y in the accumulator with the data W2 × H2 generated by the multiplier in the comparator, and repeating (3-3) if Y is less than W2 × H2; if Y is larger than or equal to W2H 2, the buffering times N are output, and q is Y-W2H 2, the scaling image W2H 2 is stored in the FIFO for N times, and the last insufficient data is compensated for q 0 s.

When detecting the FIFO full signal is set to 1, DDR4 begins to read K bytes of cache data from the FPGA internal memory asynchronous clock FIFO at a predetermined read speed.

(4) When detecting the FIFO full signal is set to 1, DDR4 begins to read K bytes of cache data from the FPGA internal memory asynchronous clock FIFO at a predetermined read speed.

(5) When the internal memory FIFO needs to read data from the external memory, the asynchronous clock FIFO reads m buffer data from the DDR4 according to a preset reading speed, and the data is buffered in the FIFO.

(6) And the display interface of each channel image fetches and displays image data from the corresponding channel cache FIFO.

Claims

1. An FPGA-based zoomed image storage method is characterized by comprising the following steps: (1) initializing an external dynamic random access memory by the FPGA; (2) acquiring an original image from a video source and zooming the original image; (3) caching K bytes of data of the zoomed image into an internal storage FIFO of the FPGA; (4) storing the K bytes of data in the FIFO into an external memory DDR 4; (5) the FIFO reads m storage data from the DDR 4; (6) and reading and displaying the image data.

2. The FPGA-based scaled image storage method of claim 1, wherein in said step (2), said original image is scaled using a bilinear interpolation algorithm.

3. The method for storing the scaled image based on the FPGA of claim 1, wherein in the step (3), the scaled image data is put into the asynchronous clock FIFO of the internal storage of the FPGA for K bytes of image buffer data at a preset putting speed; counting is carried out when data is put in, when K bytes of data are counted up, a full signal is enabled, a counter is cleared, and when a read empty signal is enabled, counting is carried out again;

storing K bytes into FIFO according to preset speed, if the zoomed image data is not enough K bytes, that is, the zoomed image resolution is not integer multiple of K, supplementing q 0 and putting K bytes into FIFO according to preset speed.

4. The FPGA-based post-zoom image storage method of claim 3, wherein the step of computing q is as follows:

(3-1) resetting the counter N and the accumulator Y;

(3-2) adding K to the accumulator Y and adding 1 to the counter N;

(3-3) storing the accumulator and counter data in corresponding registers;

5. The FPGA-based scaled image storage method of claim 1, wherein in step (4), when detecting that the FIFO full signal is set to 1, the DDR4 starts to read K bytes of cache data from the asynchronous clock FIFO of the FPGA internal memory at a predetermined reading speed.

6. The FPGA-based scaled image storage method of claim 1, wherein in step (5), when the internal memory FIFO needs to read data from the external memory, the asynchronous clock FIFO reads m buffered data from the DDR4 at a predetermined reading speed, and the data is buffered in the FIFO.

7. The method for storing the zoomed image based on the FPGA of claim 1, wherein in the step (6), the display interface of each channel image reads and displays the image data from the corresponding channel buffer.