CN111934675A - Time delay circuit - Google Patents
Time delay circuit Download PDFInfo
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- CN111934675A CN111934675A CN202010976358.3A CN202010976358A CN111934675A CN 111934675 A CN111934675 A CN 111934675A CN 202010976358 A CN202010976358 A CN 202010976358A CN 111934675 A CN111934675 A CN 111934675A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The invention discloses a delayer circuit, which comprises a PVT tracking circuit, a reference delayer and N signal delayers, wherein the PVT tracking circuit comprises a PVT tracking circuit, a reference delayer and a plurality of signal delayers; the PVT (process, power supply voltage and temperature) tracking circuit is used for outputting a tracking control signal to the reference delayer according to a reference clock signal; the reference delayer is used for adjusting the relation between the input phase and the output phase according to the tracking control signal, and then feeding back the clock signal to the PVT tracking circuit so that the PVT tracking circuit can generate an adjusted tracking control signal according to the fed-back clock signal; and adjusting the relation between the input phase and the output phase of other on-chip delayers according to the adjusted tracking control signal. The delay circuit provided by the invention can make the delay time of the delay insensitive to PVT variation.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a delayer circuit.
Background
The conventional delayer generally comprises a CMOS inverter chain delayer, a current starvation delayer and the like, however, the delay of the CMOS inverter chain delayer and the current starvation delayer varies greatly with the process, the power voltage and the temperature (PVT), and various chips need stable delay, so the conventional delayer is not suitable for being applied to chips requiring stable delay.
Disclosure of Invention
The invention mainly aims to provide a delayer circuit, aiming at solving the problem that the delayer circuit is sensitive to the process, the power supply voltage and the temperature change.
In order to achieve the above object, the present invention provides a delay circuit, which includes a PVT tracking circuit, a reference delay, and N signal delays; wherein the content of the first and second substances,
the PVT tracking circuit is used for outputting a tracking control signal to the reference delayer according to a reference clock signal;
the reference delayer is used for adjusting the relation between the input phase and the output phase according to the tracking control signal, then feeding back the clock signal to the PVT tracking circuit, so that the PVT tracking circuit generates an adjusted tracking control signal according to the fed-back clock signal, and adjusting the relation between the input phase and the output phase of each of the N signal delayers on the chip according to the adjusted tracking control signal.
In one embodiment, the PVT tracking circuit includes a phase detector, a phase voltage conversion circuit, and a filter; wherein the content of the first and second substances,
the phase discriminator is provided with a first signal input end, a second signal input end and an output end, and is used for comparing the phase between a first signal input by the first signal input end and a second signal input by the second signal input end and outputting a phase difference signal to the phase voltage conversion circuit;
the input end of the phase voltage conversion circuit is connected with the output end of the phase discriminator, and the phase voltage conversion circuit is used for outputting a converted voltage signal to the filter according to the received phase difference signal;
and the input end of the filter is connected with the output end of the phase voltage conversion circuit, and the filter is used for outputting the filtered tracking control signal to the reference delayer according to the received voltage signal.
In one embodiment, the reference delay comprises a voltage controlled delay line.
In one embodiment, the reference delay comprises an oscillator and a frequency divider, and the oscillator is connected with the frequency divider; wherein the content of the first and second substances,
the oscillator is used for outputting an oscillation signal to the frequency divider according to the tracking control signal;
the frequency divider is configured to output a frequency-divided clock signal according to the oscillation signal to adjust a relationship between an input phase and an output phase of the reference delay, and then feed back the frequency-divided clock signal to the PVT tracking circuit, so that the PVT tracking circuit generates an adjusted tracking control signal according to the fed-back frequency-divided clock signal to control the N signal delays to adjust respective input phases and output phases.
In one embodiment, the reference delay unit includes a plurality of stages of first delay units, and the plurality of stages of first delay units are arranged in series.
In an embodiment, each stage of the first delay unit includes a first switch tube and a first inverter, an input end of the first inverter is used for receiving an input signal, and an output end of the first inverter is used for outputting an output signal;
the controlled end of the first switch tube is connected with the PVT tracking circuit, and the output end of the first switch tube is connected with the controlled end of the first phase inverter.
In one embodiment, the first inverter comprises a second switch tube and a third switch tube;
the input end of the second switch tube is connected with a power supply end, the controlled end of the second switch tube is the input end of the first phase inverter, the controlled end of the second switch tube is interconnected with the controlled end of the third switch tube, the output end of the second switch tube is the output end of the first phase inverter, the output end of the second switch tube is interconnected with the output end of the third switch tube, and the input end of the third switch tube is the controlled end of the first phase inverter.
In one embodiment, the signal delayer comprises a plurality of stages of second delay units, and the plurality of stages of second delay units are arranged in series.
In an embodiment, each stage of the second delay unit includes a fourth switch tube and a second inverter, an input end of the second inverter is used for receiving an input signal, and an output end of the second inverter is used for outputting an output signal;
and the controlled end of the fourth switching tube is connected with the PVT tracking circuit, and the output end of the fourth switching tube is connected with the controlled end of the second phase inverter.
In one embodiment, the second inverter comprises a fifth switching tube and a sixth switching tube;
the input end of the fifth switching tube is connected with a power supply end, the controlled end of the fifth switching tube is the input end of the first phase inverter, the controlled end of the fifth switching tube is interconnected with the controlled end of the sixth switching tube,
the output end of the fifth switching tube is the output end of the first phase inverter, the output end of the fifth switching tube is interconnected with the output end of the sixth switching tube, and the input end of the sixth switching tube is the controlled end of the first phase inverter.
In the technical scheme of the invention, the delay circuit provided by the invention comprises a PVT tracking circuit, a reference delay unit and N signal delay units; the PVT tracking circuit is used for outputting a tracking control signal to the reference delayer according to a reference clock signal; the reference delayer is used for adjusting the relation between the input phase and the output phase according to the tracking control signal, and then feeding back the clock signal to the PVT tracking circuit so that the PVT tracking circuit can generate an adjusted tracking control signal according to the fed-back clock signal; and adjusting the relation between the input phase and the output phase of other on-chip delayers according to the adjusted tracking control signal. The delay circuit provided by the invention can make the delay time of the delay insensitive to PVT change. The delay circuit provided by the invention can make the delay time of N signal delays insensitive to PVT change and save the chip area.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of a COMS inverter chain in the prior art;
FIG. 2 is a schematic diagram of a circuit structure of a current starvation type delay unit in the prior art;
FIG. 3 is a functional diagram of a delay circuit according to an embodiment of the present invention;
FIG. 4 is a functional diagram of another embodiment of a delay circuit of the present invention;
FIG. 5 is a functional diagram of a delay circuit according to another embodiment of the present invention;
FIG. 6 is a waveform diagram of an embodiment of the first delay cell of the present invention;
FIG. 7 is a diagram of an embodiment of a multi-stage first delay cell of the present invention;
FIG. 8 is a circuit diagram of an embodiment of the reference controlled delay of the present invention;
fig. 9 is a circuit diagram of a signal delay device according to an embodiment of the invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | PVT tracking circuit | 210 | A |
| 110 | |
211 | |
| 120 | Phase voltage conversion circuit | 212 | A |
| 130 | Filter with a filter element having a plurality of |
300 | Signal delayer 1- |
| 200 | |
310 | |
| 201 | |
311 | |
| 202 | |
312 | Second inverter |
The objects, features and advantages of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides a time delay circuit.
At present, the conventional delayers generally have several basic structures, such as a CMOS inverter chain, a current starvation type delayer and the like.
Referring to fig. 1, a CMOS inverter chain is composed of an even number of CMOS inverters connected in series with each other,
although the CMOS inverter chain has a simple structure, the structure of the CMOS inverter chain is easily affected by power supply voltage, temperature, and process, and has poor stability, and is not suitable for application to a delay circuit structure requiring stability.
Referring to fig. 2, the current starving type delay device is composed of a plurality of MOS transistors (e.g., a first MOS transistor NM1, a second MOS transistor NM2, a third MOS transistor NM3, a fourth MOS transistor NM4, a fifth MOS transistor NM5, a sixth MOS transistor NM6, and a seventh MOS transistor NM 7), a plurality of capacitors (e.g., a first capacitor C1 and a second capacitor C2), and a current source Iref, wherein an input terminal IN is used for inputting a delay signal, an output terminal OUT is used for outputting a delay signal, and the current source Iref is used for limiting a current flowing through a branch circuit, and due to a mirror relationship of the current source, a delay of the current starving type delay device is related to the current source Iref and a capacitor (e.g., a first capacitor C1 and a second capacitor C2), and since the current source Iref is generated on-chip, a strong process variation is involved, and a capacitor is also related to a process, that is, the delay signal output by the output terminal OUT of the current starving type delay device is unstable, the current starvation type delayer cannot meet the application requiring stable delay.
Referring to fig. 3 to 9, in an embodiment of the present invention, a delay circuit includes a PVT (Process Voltage and Temperature) tracking circuit 100, a reference delay 200, and N signal delays 300; wherein the content of the first and second substances,
the PVT tracking circuit 100 is configured to output a tracking control signal to the reference delay 200 according to a reference clock signal;
the reference delayer 200 is configured to adjust a relationship between an input phase and an output phase of the PVT tracking circuit 100 according to the tracking control signal, and then feed back a clock signal of the reference delayer to the PVT tracking circuit 100, so that the PVT tracking circuit 100 generates an adjusted tracking control signal according to the fed back clock signal, and adjusts a relationship between an input phase and an output phase of each of the N signal delayers 300 on the chip according to the adjusted tracking control signal.
For convenience of understanding, a delay circuit including a reference delay 200 is taken as an example for explanation, and assuming that the reference delay 200 is expected to output a delay time T, the delay time of the reference delay 200 is greater than or less than T due to process, Power Voltage and Temperature (PVT), so that the signal output by the reference delay 200 is unstable; however, the tracking control signal Vc compensates the reference delay 200 for PVT variations so that the reference delay 200 does not vary with process, supply voltage and temperature (PVT) variations, i.e., the reference delay 200 delays the output delay time T insensitive to PVT variations. For example, by increasing the voltage of the tracking control signal Vc, the delay time T will be shortened, thereby correcting the increase in delay time T due to process, supply voltage, and temperature (PVT) variations; correcting a decrease in the delay time T caused by process, power supply voltage and temperature (PVT) variations by decreasing the voltage of the tracking control signal Vc to increase the delay time T, such that the delay time T of the reference delayer 200 does not vary with the process, power supply voltage and temperature (PVT) variations using the tracking control signal Vc; that is, when N signal delayers 300 are consistent with the circuit structure of the reference delayer 200 and on the same chip, the reference delayer 200 and N signal delayers 300 are consistent with the effect/influence of the process, the power voltage and the temperature (PVT), because the tracking control signal Vc controls the reference delayer 200 of the PVT tracking circuit 100 to be insensitive, then controlling other N signal delayers 300 by using the tracking control signal Vc also makes the delay of these delayers insensitive to the process, the power voltage and the temperature (PVT), and it should be noted that the insensitive is that the delay time of the delayers does not change with the change of the process, the power voltage and the temperature (PVT). The delay time T is set according to the user requirement, and is not limited here; IN addition, the N signal delayers 300 can be a signal delayer 1, a signal delayer 2, … …, a signal delayer N, and the like, and the signal delayer 1 has a delayed signal input end IN1 and a delayed signal output end OUT1, the input end IN1 and the output end OUT1 of the signal delayer 1 are respectively used for inputting and outputting delayed signals, and similarly, since the signal delayer 2, … … and the signal delayer N are consistent with the principle of the signal delayer 1, the signal delayer 2 has a delayed signal input end IN2 and a delayed signal output end OUT2, and the signal delayer N has a delayed signal input end INN and a delayed signal output end OUTN, and detailed description thereof is omitted; in addition, the number of N is set according to the user requirement, and is not limited here.
In the technical scheme of the invention, the delayer circuit disclosed by the invention comprises a PVT tracking circuit 100, a reference delayer 200 and N signal delayers 300; the PVT tracking circuit 100 is configured to output a tracking control signal to the reference delay 200 according to a reference clock signal; the reference delayer 200 is configured to adjust a relationship between an input phase and an output phase thereof according to the tracking control signal, and then feed back a clock signal thereof to the PVT tracking circuit 100, so that the PVT tracking circuit 100 generates an adjusted tracking control signal according to the fed back clock signal; and adjusting the relation between the input phase and the output phase of other on-chip delayers according to the adjusted tracking control signal. The delay circuit provided by the invention can make the delay time of the delay insensitive to PVT variation, and because the PVT tracking circuit 100, the reference delay 200 and the N signal delays 300 are integrated on a chip, the chip area is also saved.
In one embodiment, referring to fig. 3-5, the PVT tracking circuit 100 includes a phase detector 110, a phase voltage conversion circuit 120, and a filter 130; wherein the content of the first and second substances,
the phase detector 110 has a first signal input terminal, a second signal input terminal and an output terminal, and the phase detector 110 is configured to compare phases between a first signal input by the first signal input terminal and a second signal input by the second signal input terminal, and output a phase difference signal to the phase voltage conversion circuit 120; it is understood that a first signal input terminal of the phase detector 110 is used for inputting a reference clock signal, and a second signal input terminal of the phase detector 110 is used for receiving the clock signal fed back by the reference delay 200;
the phase voltage converting circuit 120 is also called a phase comparator, an input end of the phase voltage converting circuit 120 is connected to an output end of the phase detector 110, and the phase voltage converting circuit 120 is configured to output a converted voltage signal to the filter 130 according to the received phase difference signal; in addition, the phase voltage conversion circuit 120 may be implemented by a charge pump or the like, and is not limited herein.
An input end of the filter 130 is connected to an output end of the phase voltage conversion circuit 120, and the filter 130 is configured to output the filtered tracking control signal to the reference delay 200 according to the received voltage signal. Since the output voltage of the phase voltage converting circuit 120 has ripples, the voltage signal output by the phase voltage converting circuit 120 is output to the filter 130 for filtering, so that the output signal is smoother, and thus the influence on the subsequent signal is eliminated. It should be noted that the filter 130 may be implemented by using a loop low pass filter 130 (LPF), and in some other embodiments, other circuits may also be implemented according to requirements, and are not limited herein.
In one embodiment, the reference delay 200 includes a voltage controlled delay line, which is an element or device for delaying an electrical signal for a period of time.
In one embodiment, referring to fig. 3 to 5, the reference delay 200 includes an oscillator 201 and a frequency divider 202, where the oscillator 201 and the frequency divider 202 are connected; wherein the content of the first and second substances,
the oscillator 201 is configured to output an oscillation signal to the frequency divider 202 according to the tracking control signal;
the frequency divider 202 is configured to output a frequency-divided clock signal according to the oscillation signal to adjust a relationship between an input phase and an output phase of the reference delay 200, and then feed back the frequency-divided clock signal to the PVT tracking circuit 100, so that the PVT tracking circuit 100 generates an adjusted tracking control signal according to the fed-back frequency-divided clock signal to control the N signal delays 300 to adjust respective input phases and output phase relationships. It should be noted that the principle of using the phase detector 110, the phase voltage conversion circuit 120, the filter 130, the oscillator 201, the frequency divider 202, and the N signal delay units 300 is the same as that of using the phase detector 110, the phase voltage conversion circuit 120, the filter 130, and the reference delay unit 200, and the delay time of each signal delay unit 300 is controlled by the tracking control signal Vc and is insensitive to PVT changes.
Further, in an embodiment, referring to fig. 3 to 9, the reference delay 200 includes a plurality of stages of first delay units 210, and the plurality of stages of first delay units 210 are arranged in series. Specifically, referring to fig. 7, the reference delayer 200 includes four stages of first delay units 210, and each of the first delay units 210 is arranged in series; it can be understood that the PVT tracking circuit 100 is equivalent to a loop consisting of the phase detector 110, the phase voltage conversion circuit 120, the filter 130 and the reference delay 200, the output of the reference delay 200 is aligned with the input phase due to the action of negative feedback, so that the tracking control signal Vc is also in a stable state, the delay time of the reference delay 200 is insensitive to PVT variation, in addition, each of the first delay units 210 has the same delay unit due to the consistent circuit structure of each of the first delay units 210, and the reference delay 200 and N of the signal delays 300 have the same circuit structure, and the reference delay 200 and N of the signal delays 300 are on the same chip, so that the process, temperature and voltage (PVT) variation has the same effect on the delay units of both, therefore, the tracking control signal output by the PVT tracking circuit 100 controls the delay time of the N signal delay units 300 to be insensitive to PVT variation. For example, referring to fig. 6, assuming that the period of the input reference clock is T, then the tracking control signal Vc is stabilized, i.e. the delay period of each first delay cell 210 is fixed to T/N, N is the number of stages of the first delay cell 210, in this embodiment, N =4, which represents that four first delay cells 210 are cascaded, SCL represents the waveform diagram of the external reference clock, N1, N2, N3, OUT represent the waveforms of the delay lag external reference clock 1/4 periods, 2/4 periods, 3/4 periods and one period, respectively, that is, the rising edge of the waveform OUT of the output of the reference delay 200 is aligned with the rising edge of the input reference clock SCL, N2 outputs the waveform leading OUT output waveform T/4 periods, N1 outputs the waveform leading N2 output waveforms T/4 periods, N2 outputs the waveform N3 leading waveforms T/4 periods, therefore, when the period T of the input reference clock is constant, the delay of each first delay unit 210 does not vary with process, temperature and voltage (PVT) variations due to the effect of negative feedback.
Specifically, in an embodiment, referring to fig. 8, each stage of the first delay unit 210 includes a first switch 211 and a first inverter, an input end of the first inverter is used for receiving an input signal, and an output end of the first inverter is used for outputting an output signal;
the controlled terminal of the first switch tube 211 is connected to the PVT tracking circuit 100, and the output terminal of the first switch tube 211 is connected to the controlled terminal of the first inverter. It should be noted that, in this embodiment, the circuit structures of the first delay units 210 of each stage are the same, and the first switch tube 211 is an NMOS tube, and in some other embodiments, the first switch tube 211 may also be a triode or an IGBT, which is not limited specifically here.
Further, in an embodiment, referring to fig. 8, the first inverter 212 includes a second switch tube and a third switch tube;
the input end of the second switch tube is connected with a power supply end, the controlled end of the second switch tube is the input end of the first phase inverter 212, the controlled end of the second switch tube is interconnected with the controlled end of the third switch tube, the output end of the second switch tube is the output end of the first phase inverter 212, the output end of the second switch tube is interconnected with the output end of the third switch tube, and the input end of the third switch tube is the controlled end of the first phase inverter 212. The second switching tube and the third switching tube may also be any one or a combination of multiple kinds of MOS tubes, triodes, and IGBTs, which is not limited herein; for convenience of understanding, a reference delay 200 formed by four stages of the first delay cells 210 connected in series is taken as an example for explanation, for convenience of distinction, each first delay cell 210 is respectively referred to as a first-stage delay cell, a second-stage delay cell, a third-stage delay cell and a fourth-stage delay cell, wherein the first-stage delay cell is formed by a first MOS transistor NM1, a second MOS transistor NM2 and a third MOS transistor NM3, the second-stage delay cell is formed by a fourth MOS transistor NM4, a fifth MOS transistor NM5 and a sixth MOS transistor NM6, the third-stage delay cell is formed by a seventh MOS transistor NM7, an eighth MOS transistor NM8 and a ninth MOS transistor NM9, the fourth-stage delay cell is formed by a tenth MOS transistor NM10, an eleventh MOS transistor NM11 and a twelfth MOS transistor NM12, wherein the gate of the first MOS transistor NM1 is the controlled terminal of the first switching transistor 211, the drain of the first MOS transistor NM1 is connected with the source of the third MOS transistor NM3, the source of the first MOS transistor NM1 is grounded, the source of the second MOS transistor is connected to the power supply end, the drain of the second MOS transistor is connected to the drain of the third MOS transistor, the gate of the second MOS transistor NM2 is the input end of the first inverter 212, the gate of the second MOS transistor NM2 is connected to the gate of the third MOS transistor NM3, the drain of the second MOS transistor NM2 is the output end of the first inverter 212, it should be noted that the first MOS transistor NM1 is an NMOS transistor, the second MOS transistor NM2 is a PMOS transistor, and the third MOS transistor NM3 is an NMOS transistor, wherein the second MOS transistor NM2 and the third MOS transistor NM3 form the first inverter 212. Since the second stage delay unit, the third stage delay unit and the fourth stage delay unit have the same circuit structure as the first stage delay unit, the description is omitted here. Since the plurality of stages of first delay cells 210 are connected in series and integrated on one chip, the area of the entire chip is small.
In one embodiment, the signal delay device 300 includes a plurality of stages of second delay units, and the plurality of stages of second delay units are arranged in series. It should be noted that, the delay of the first delay unit 210 in the reference delay unit 200 does not change with the supply voltage, temperature and process variations due to the negative feedback, but the input voltage Vc of the first delay unit 210 changes with the supply voltage, temperature and process variations, and Vc tracks the changes of these factors, so that the Vc is used to control the places on the chip where delay is needed, for example, where delay is needed, N signal delays 300, that is, the signal delay unit 1, the signal delay unit 2 … … and the signal delay unit N, and the delay of the signal delay unit 1, the signal delay unit 2 … … and the signal delay unit N is insensitive to the supply voltage, temperature and process variations due to the Vc tracking the supply voltage, temperature and process variations.
Further, in an embodiment, each stage of the second delay unit 310 includes a fourth switch and a second inverter, an input end of the second inverter is used for receiving an input signal, and an output end of the second inverter is used for outputting an output signal;
the controlled end of the fourth switching tube 311 is connected to the PVT tracking circuit 100, and the output end of the fourth switching tube 311 is connected to the controlled end of the second inverter 312.
Specifically, the second inverter 312 includes a fifth switching tube and a sixth switching tube;
the input end of the fifth switching tube is connected with a power supply end, the controlled end of the fifth switching tube is the input end of the first phase inverter 212, the controlled end of the fifth switching tube is connected with the controlled end of the sixth switching tube, the output end of the fifth switching tube is the output end of the first phase inverter 212, the output end of the fifth switching tube is interconnected with the output end of the sixth switching tube, and the input end of the sixth switching tube is the controlled end of the first phase inverter 212. It should be noted that the fourth switching tube 311 is an NMOS tube, the fifth switching tube is a PMOS tube, and the sixth switching tube is an NMOS tube, in addition, in some other embodiments, the fourth switching tube 311, the fifth switching tube, and the sixth switching tube may also be other switches with on/off capability, for example, any one or a combination of a triode and an IGBT, which is not limited herein. Specifically, in this embodiment, referring to fig. 9, where a thirteenth MOS transistor NM13, a fourteenth MOS transistor NM14 and a fifteenth MOS transistor NM15 constitute a second delay unit 310, a sixteenth MOS transistor NM16, a seventeenth MOS transistor NM17 and a eighteenth MOS transistor NM18 constitute a second delay unit 310, a nineteenth MOS transistor NM19, a twentieth MOS transistor NM20 and a twenty-first MOS transistor NM21 constitute a second delay unit 310, similarly, a twenty-second MOS transistor NM22, a twenty-third MOS transistor NM23 and a twenty-fourth MOS transistor NM24 constitute a second delay unit 310, for convenience of understanding, the second delay unit 310 composed of the thirteenth MOS transistor NM13, the fourteenth MOS transistor NM14 and the fifteenth MOS transistor NM15 is taken as an example, where the thirteenth MOS transistor NM8 may be implemented by an NMOS transistor, the fourteenth MOS transistor NM14 is implemented by an NM15, the fifteenth MOS 92 is implemented by an NMOS transistor NM 638, and the fourteenth MOS transistor is taken as a controlled gate electrode 686311, the source of the thirteenth MOS transistor NM13 is grounded, the drain of the thirteenth MOS transistor NM13 is connected to the source of the fifteenth MOS transistor NM15, wherein the gate of the fourteenth MOS transistor NM14 is the input terminal of the second inverter 312, the drain of the fourteenth MOS transistor NM14 is the output terminal of the second inverter 312, the drain of the fourteenth MOS transistor NM14 is connected to the drain of the fifteenth MOS transistor NM15, the gate of the fourteenth MOS transistor NM14 is connected to the gate of the fifteenth MOS transistor NM15, and the source of the fourteenth MOS transistor NM14 is connected to the power supply terminal.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A delay circuit comprising a PVT tracking circuit, a reference delay, and N signal delays; wherein the content of the first and second substances,
the PVT tracking circuit is used for outputting a tracking control signal to the reference delayer according to a reference clock signal;
the reference delayer is used for adjusting the relation between the input phase and the output phase according to the tracking control signal, then feeding back the clock signal to the PVT tracking circuit, so that the PVT tracking circuit generates an adjusted tracking control signal according to the fed-back clock signal, and adjusting the relation between the input phase and the output phase of each of the N signal delayers on the chip according to the adjusted tracking control signal.
2. The delay circuit of claim 1, wherein the PVT tracking circuit comprises a phase detector, a phase-to-voltage conversion circuit, and a filter; wherein the content of the first and second substances,
the phase discriminator is provided with a first signal input end, a second signal input end and an output end, and is used for comparing the phase between a first signal input by the first signal input end and a second signal input by the second signal input end and outputting a phase difference signal to the phase voltage conversion circuit;
the input end of the phase voltage conversion circuit is connected with the output end of the phase discriminator, and the phase voltage conversion circuit is used for outputting a converted voltage signal to the filter according to the received phase difference signal;
and the input end of the filter is connected with the output end of the phase voltage conversion circuit, and the filter is used for outputting the filtered tracking control signal to the reference delayer according to the received voltage signal.
3. The delay circuit of claim 1, wherein the reference delay comprises a voltage controlled delay line.
4. The delay circuit of claim 1, wherein the reference delay comprises an oscillator and a frequency divider, the oscillator and the frequency divider being coupled; wherein the content of the first and second substances,
the oscillator is used for outputting an oscillation signal to the frequency divider according to the tracking control signal;
the frequency divider is configured to output a frequency-divided clock signal according to the oscillation signal to adjust a relationship between an input phase and an output phase of the reference delay, and then feed back the frequency-divided clock signal to the PVT tracking circuit, so that the PVT tracking circuit generates an adjusted tracking control signal according to the fed-back frequency-divided clock signal to control the N signal delays to adjust respective input phases and output phases.
5. The delay circuit of claim 1, wherein the reference delay comprises a plurality of stages of first delay cells arranged in series.
6. The delay circuit of claim 5, wherein each stage of the first delay cell comprises a first switch and a first inverter, an input terminal of the first inverter is for receiving an input signal, and an output terminal of the first inverter is for outputting an output signal;
the controlled end of the first switch tube is connected with the PVT tracking circuit, and the output end of the first switch tube is connected with the controlled end of the first phase inverter.
7. The delay circuit of claim 6, wherein the first inverter comprises a second switch and a third switch;
the input end of the second switch tube is connected with a power supply end, the controlled end of the second switch tube is the input end of the first phase inverter, the controlled end of the second switch tube is interconnected with the controlled end of the third switch tube, the output end of the second switch tube is the output end of the first phase inverter, the output end of the second switch tube is interconnected with the output end of the third switch tube, and the input end of the third switch tube is the controlled end of the first phase inverter.
8. The delay circuit of claim 1, wherein the signal delay comprises a plurality of stages of second delay cells, the plurality of stages of the second delay cells being arranged in series.
9. The delay circuit of claim 8, wherein each stage of the second delay cell comprises a fourth switch and a second inverter, an input of the second inverter is for receiving an input signal, and an output of the second inverter is for outputting an output signal;
and the controlled end of the fourth switching tube is connected with the PVT tracking circuit, and the output end of the fourth switching tube is connected with the controlled end of the second phase inverter.
10. The delay circuit of claim 9, wherein the second inverter comprises a fifth switching tube and a sixth switching tube;
the input end of the fifth switching tube is connected with a power supply end, the controlled end of the fifth switching tube is the input end of the first phase inverter, the controlled end of the fifth switching tube is interconnected with the controlled end of the sixth switching tube,
the output end of the fifth switching tube is the output end of the first phase inverter, the output end of the fifth switching tube is interconnected with the output end of the sixth switching tube, and the input end of the sixth switching tube is the controlled end of the first phase inverter.
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| CN202010976358.3A CN111934675A (en) | 2020-09-17 | 2020-09-17 | Time delay circuit |
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| CN202010976358.3A CN111934675A (en) | 2020-09-17 | 2020-09-17 | Time delay circuit |
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Application publication date: 20201113 |