CN111933609A - Bump structure of flip chip and preparation method thereof - Google Patents

Bump structure of flip chip and preparation method thereof Download PDF

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Publication number
CN111933609A
CN111933609A CN202010636480.6A CN202010636480A CN111933609A CN 111933609 A CN111933609 A CN 111933609A CN 202010636480 A CN202010636480 A CN 202010636480A CN 111933609 A CN111933609 A CN 111933609A
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China
Prior art keywords
bump
substrate
insulating layer
metallization
flip chip
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Pending
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CN202010636480.6A
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Chinese (zh)
Inventor
徐高卫
李坤
杨帆
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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Priority to CN202010636480.6A priority Critical patent/CN111933609A/en
Publication of CN111933609A publication Critical patent/CN111933609A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to a salient point structure of a flip chip and a preparation method thereof, wherein the salient point structure comprises a substrate, wherein salient points which are made of the same material as the substrate are formed on the substrate; insulating layers are covered on the surface of the substrate and the surface of the salient point; a metallization layer is formed on the insulating layer; the metallization layer comprises a metal wiring layer and bump metallization, and the bump metallization extends from an insulating layer on the upper portion of the bump to the insulating layer right above the substrate through the bump side wall coated by the insulating layer; the metal wiring layer is positioned on the insulating layer right above the substrate and is in metalized connection with the salient points. The preparation method is realized by an etching method, and the ultrathin salient points can be prepared, so that the low-loss and low-delay transmission of high-bandwidth signals is facilitated, and the method can be used for flip chip interconnection of high-frequency circuits. The invention has the advantages of high rigidity, good shape retention and good consistency, reduces the risk of short circuit of the salient points, and ensures the quality of flip chip bonding and the packaging reliability.

Description

Bump structure of flip chip and preparation method thereof
Technical Field
The invention relates to a bump technology in the technical field of semiconductor packaging, in particular to a bump structure of a flip chip and a preparation method thereof.
Background
The bump technology is a key technology of the flip chip technology. With the wide application of flip chip technology to high performance and consumer electronics, the mechanical, electrical and thermodynamic loads borne by the bumps are getting heavier. With the increasing requirement on the package reliability of the component, the preparation of the bumps becomes more and more important. In high frequency modules, for example, to ensure that the flip-chip bumps are capable of transmitting high bandwidth signals, the thickness of the flip-chip bumps often needs to be made very small, such as a few microns. The research on the bump technology is also particularly important.
The existing bump manufacturing methods mainly comprise vapor plating of solder bumps, electroplating of bumps (solder bumps, copper columns and the like) and laser ball implantation. The evaporation method has great waste of bump materials; the electroplating method has complex process, such as slow electroplating speed, high requirements on electroplating solution and current control for long-time electroplating, complex reflux control and the like; the flatness of the solder ball prepared by the laser ball implantation method is not high, and the diameter of the conventional implantable solder ball is limited to more than 40um, so that the thickness of the solder ball is difficult to reach the order of micrometers. In addition, the bump preparation is generally performed on a flip chip and is often a wafer level process, so that there is a risk of breakage of the chip wafer. The quality of the chip bump preparation directly affects the quality of flip chip bonding and the reliability of the flip chip bonding, so a method for preparing a bump structure with simple process, high bump flatness, good consistency and good shape retention is required to be found.
Disclosure of Invention
The invention aims to provide a bump structure of a flip chip and a preparation method thereof, which can ensure the flip chip welding quality and the packaging reliability.
The technical scheme adopted by the invention for solving the technical problems is as follows: the bump structure of the flip chip comprises a substrate, wherein bumps made of the same material as the substrate are formed on the substrate; insulating layers are covered on the surface of the substrate and the surface of the salient point; a metallization layer is formed on the insulating layer; the metallization layer comprises a metal wiring layer and bump metallization, and the bump metallization extends from an insulating layer on the upper portion of the bump to the insulating layer right above the substrate through the bump side wall coated by the insulating layer; the metal wiring layer is positioned on the insulating layer right above the substrate and is in metalized connection with the salient points.
The salient points are of convex structures with 40-60-degree inclined edges.
The bottom width of the salient points is larger than the top width.
The height of the salient point is 3-300 mu m.
The bump metallization covers the side wall of the bump in a full-coverage mode.
The salient point metallization adopts a climbing line form to climb from the side wall of the salient point to the upper part of the salient point.
The technical scheme adopted by the invention for solving the technical problems is as follows: the preparation method of the bump structure of the flip chip comprises the following steps:
(1) providing a substrate, and forming salient points with the same material as the substrate on the surface of the substrate;
(2) forming an insulating layer on the substrate, so that the insulating layer completely covers the surfaces of the substrate and the salient points;
(3) forming a metallization layer on the insulating layer; the metallization layer comprises a metal wiring layer and bump metallization; the bump metallization extends from the insulating layer on the upper portion of the bump to the insulating layer right above the substrate through the bump side wall coated by the insulating layer; the metal wiring layer is located on the insulating layer right above the substrate and is connected with the salient points in a metallization mode.
In the step (1), the convex points are directly formed on the surface of the substrate in a micro-machining mode.
And (3) forming the insulating layer in the step (2) on the substrate by adopting a thermal oxidation method or a deposition method.
And (4) patterning the metallization layer in the step (3) on the insulating layer by adopting a sputtering mode.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the salient point structure is directly formed by micromachining on the substrate, so that the salient point process is simple, the salient point structure can be obtained by adopting etching and metal deposition methods, complicated processes such as reflux and the like are omitted, and meanwhile, the preparation of salient points on a chip (wafer) is avoided, so that the risk of crushing a flip chip is avoided. Compared with a common solder bump, the bump material is consistent with a substrate, the rigidity is high, the robustness to the flip-chip bonding pressure is strong, the bump can be obtained through an etching method, the consistency of the height of the bump is controllable, the flatness of the substrate is controllable, the flip-chip bonding quality is guaranteed to have high yield, the shape retention is good after the bump is formed, and the risk that the solder ball collapses to cause short circuit of adjacent solder balls is reduced. In addition, the shape of the bump structure is controllable and optimized, and an extremely thin bump can be prepared, so that low-loss and low-delay transmission of high-bandwidth signals are facilitated.
Drawings
Fig. 1 to 4 are schematic flow charts illustrating a method for fabricating a bump structure of a flip chip according to an embodiment;
FIG. 5 is a top view of an intermediate stage of the embodiment for ease of understanding;
FIG. 6 is a schematic diagram of flip chip bonding on a substrate having a bump structure;
FIGS. 7-8 are schematic views of bump structures of various alternative embodiments;
FIG. 9 is a schematic diagram of an alternative embodiment bump metallization;
in the figure, 101-substrate, 102-bump, 201-insulating layer, 301-metallization layer, 302-bump metallization, 303-metal wiring layer, 401-conductive adhesive, 501-flip chip.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a bump structure of a flip chip and a preparation method thereof, wherein the flow of the preparation method is shown in figures 1-4, and specifically comprises the following steps:
(1) a substrate 101 is provided, and the substrate 101 is cleaned conventionally. The substrate 101 may be a silicon wafer or other substrate materials that can be processed by etching, and in this step, the substrate is an n-type (100) silicon wafer.
(2) A bump 102 is formed on the surface of the substrate 101 (see fig. 1). Wherein, the salient point can be formed by micro-processing, such as wet etching, and the salient point is a convex structure with 40-60 degrees inclined edge. The shape of bump can be round platform shape or be cylindrical, prismoid etc. its height can be between 3um ~ 300 um. In this step, the bump 102 is etched by a wet method to form a circular truncated cone structure.
The salient points are directly formed on the substrate in a micro-processing mode, the material of the salient points is the same as that of the substrate, the advantages of high rigidity and good shape-preserving performance are guaranteed, meanwhile, the extremely thin salient points can be prepared by an etching method, low-loss and low-delay transmission of high-bandwidth signals are facilitated, and therefore the salient points can be used for flip chip interconnection of high-frequency circuits.
(3) An insulating layer 201 is formed on the substrate 101, and the insulating layer 201 completely covers the substrate 101 and the surface of the bump 102 (see fig. 2). The insulating layer 201 may be formed by using other non-organic materials such as silicon oxide or silicon nitride, and further may be formed by using a thermal oxidation method to form a silicon oxide layer or by depositing an insulating material such as silicon nitride. In this step, a thermal oxidation treatment is performed on the surface of the substrate 101 including the bump 102 to form a surface silicon oxide layer.
(4) A metallization layer 301 is sputtered on the surface of the insulating layer 201 (see fig. 3). The metallization layer 301 comprises a metal routing layer 303 and bump metallization 302 (see fig. 4-5); the bump metallization 302 extends from the insulating layer 201 on the upper portion of the bump 102 to the insulating layer 201 directly above the substrate 101 through the bump sidewall covered by the insulating layer 201; the metal wiring layer 303 is located on the insulating layer 201 directly above the substrate 101 and connected to the bump metallization 302. The metal layer can be thickened by electroplating during sputtering, and the metallization layer is Cu, Al or other metals conforming to the electroplating process. Wherein bump metallization 302 and metal wiring layer 303 may be formed simultaneously and may be formed of the same material.
In this step, the metallization layer 301 is TiW/Cu, wherein TiW is used as an adhesion layer and Cu is used as a seed layer. The bump metallization 302 extends on the insulating layer 201 directly above the substrate 101 via a sidewall at the top of the bump 102 covering the insulating layer 201. The metal wiring layer 303 is located on the insulating layer 201 directly above the substrate 101 and connected to the bump metallization 302. In fig. 5, the position distribution of the bump metallization 302 and the metal wiring layer 303 on the insulating layer 201 can be seen. Lithographically defining an interconnect line pattern on the metallization layer 301; after photoetching definition, electroplating and thickening the metallization layer 301 to a certain thickness to obtain bump metallization 302 and a metal wiring layer 303; and removing the photoresist, and etching the metallization layer 301 to obtain the bump metallization 302 and the metal wiring layer 303.
(5) The flip chip 501 is attached to the substrate 101 of the bump 102 through an anisotropic conductive adhesive 401. In this step, the flip chip 501 is bonded to the substrate 101 by curing the conductive adhesive 401, and is electrically connected to the bump metallization 302 on the substrate 101, so that the flip chip bonding is realized.
Therefore, the method can improve the strength and the quality of the salient points of the flip chip, has simple process and easy operation, reduces the packaging difficulty of the flip chip, improves the packaging reliability, and has wide application prospect in the technical field of flip chip interconnection.
It should be noted that the convex structure with the bevel edge of 40-60 ° in this embodiment may be as shown in fig. 7, that is, the bump structure in the above embodiment, the bump 102 has a truncated cone shape, so that the bottom width is greater than the top width, and the slope is provided to facilitate the formation and adhesion of the subsequent metallization layer 301. As shown in fig. 8, the bump 102 may be a frustum of a prism, in which the bottom width is also greater than the top width, and the slope is a plane, and the photolithographic pattern only needs to be adjusted during the photolithographic definition, which can be implemented based on the bump preparation process described above.
Fig. 8 and 9 respectively show embodiments of different profiles of the bump metallization 302, which are mainly embodied in different wiring manners of the bump metallization 302 on the bump 102, in fig. 8, on the bump 102 covering the insulating layer 201, the bump metallization 302 extends from the upper portion of the bump 102 to the insulating layer 201 directly above the substrate 101 through a sidewall, which is different from fig. 9 in that whether the sidewall of the entire bump 102 is completely covered, and the bump metallization 302 is completely covered. In fig. 9, the bump metallization 302 is mainly in the form of a climbing line, which is on the insulating layer 201 and climbs from right above the substrate 101 to the upper portion of the bump along the sidewall of the bump, thereby forming the bump metallization 302. The bump metallization 302 is formed into its outline shape by lithography definition and etching, so the pattern shape of the bump metallization 302 on the bump 102 structure can be flexibly adjusted according to the circuit requirements, and can be a pattern such as complete metal deposition, climbing line, etc.
As can be easily found, the salient point structure is directly formed by micromachining on the substrate, so that the salient point process is simple, the salient point structure can be obtained by adopting etching and metal deposition methods, complicated processes such as reflux and the like are omitted, and meanwhile, the preparation of salient points on a chip (wafer) is avoided, so that the risk of crushing a flip chip is avoided. Compared with a common solder bump, the bump material is consistent with a substrate, the rigidity is high, the robustness to the flip-chip bonding pressure is strong, the bump can be obtained through an etching method, the consistency of the height of the bump is controllable, the flatness of the substrate is controllable, the flip-chip bonding quality is guaranteed to have high yield, the shape retention is good after the bump is formed, and the risk that the solder ball collapses to cause short circuit of adjacent solder balls is reduced. In addition, the shape of the bump structure is controllable and optimized, and an extremely thin bump can be prepared, so that low-loss and low-delay transmission of high-bandwidth signals are facilitated.

Claims (10)

1. A bump structure of a flip chip comprises a substrate and is characterized in that bumps made of the same material as the substrate are formed on the substrate; insulating layers are covered on the surface of the substrate and the surface of the salient point; a metallization layer is formed on the insulating layer; the metallization layer comprises a metal wiring layer and bump metallization, and the bump metallization extends from an insulating layer on the upper portion of the bump to the insulating layer right above the substrate through the bump side wall coated by the insulating layer; the metal wiring layer is positioned on the insulating layer right above the substrate and is in metalized connection with the salient points.
2. The bump structure of flip chip according to claim 1, wherein the bump is a convex structure having a bevel of 40 ° to 60 °.
3. The bump structure of flip chip according to claim 1, wherein the bump has a bottom width greater than a top width.
4. The bump structure of the flip chip according to claim 1, wherein the height of the bump is 3 μm to 300 μm.
5. The bump structure of flip chip as claimed in claim 1, wherein the bump metallization covers sidewalls of the bumps in a full coverage manner.
6. The bump structure of the flip chip as claimed in claim 1, wherein the bump metallization is in the form of a ramp line that ramps from a sidewall of the bump to an upper portion of the bump.
7. A method for preparing a bump structure of a flip chip is characterized by comprising the following steps:
(1) providing a substrate, and forming salient points with the same material as the substrate on the surface of the substrate;
(2) forming an insulating layer on the substrate, so that the insulating layer completely covers the surfaces of the substrate and the salient points;
(3) forming a metallization layer on the insulating layer; the metallization layer comprises a metal wiring layer and bump metallization; the bump metallization extends from the insulating layer on the upper portion of the bump to the insulating layer right above the substrate through the bump side wall coated by the insulating layer; the metal wiring layer is located on the insulating layer right above the substrate and is connected with the salient points in a metallization mode.
8. The method for preparing the bump structure of the flip chip according to claim 7, wherein the bumps are directly formed on the surface of the substrate in the step (1) by micromachining.
9. The method for preparing a bump structure of a flip chip according to claim 7, wherein the insulating layer in the step (2) is formed on the substrate by a thermal oxidation method or a deposition method.
10. The method for preparing the bump structure of the flip chip according to claim 7, wherein the metallization layer in the step (3) is formed by patterning on the insulating layer by sputtering.
CN202010636480.6A 2020-07-03 2020-07-03 Bump structure of flip chip and preparation method thereof Pending CN111933609A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104173A1 (en) * 2003-09-30 2005-05-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
JP2011134971A (en) * 2009-12-25 2011-07-07 Denso Corp Semiconductor device and method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050104173A1 (en) * 2003-09-30 2005-05-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
JP2011134971A (en) * 2009-12-25 2011-07-07 Denso Corp Semiconductor device and method of manufacturing the same

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