CN111932430B - Image encryption method based on FPGA - Google Patents

Abstract

The invention discloses an image encryption method based on an FPGA, which comprises the following steps: initializing a dynamic random access memory by an FPGA; (2) the FPGA reads the original image; (3) The FPGA acquires time sequence information of an original image, and establishes a random sequence; (4) respectively performing encryption operation and storing the image. The invention has no requirement on the length of the key and has wider application range; the requirement on image data encryption can be met by adding a simple random sequence with a known initial value, the security performance is high, the data loss caused by too slow encryption speed is avoided, and the image data encryption processing efficiency is improved; the added random sequence combination initial value is known, the pixel clock Pclk signal is known, the operability is high, and the reduction degree is high; the random sequence is generated randomly and variously, the generated key stream is also diversified, the encryption effect is stronger, and the practicability is higher.

Description

A Method of Image Encryption Based on FPGA

technical field

The invention relates to an image encryption method, in particular to an FPGA-based image encryption method.

Background technique

Image encryption technology can generally be divided into two categories, namely airspace image encryption technology and compressed image encryption technology. For example, the invention patent CN 107659753 B mainly provides an image compression and encryption method, which performs T hash operations on the initial key, obtains a measurement matrix according to the T hash values, and uses the measurement matrix to calculate the column The semi-tensor compressed sensing of the vector is used to obtain the encrypted image; although this invention has better confidentiality, the original plaintext image has a strong correlation between adjacent rows and adjacent columns, and the calculation is large and slow, which is safe. The performance depends entirely on the length of the key, and the operability still needs to be improved. Another example is the invention patent CN 105513002 B, which changes the pixel sum of the image through the modular operation between rows and columns and breaks the strong correlation between adjacent rows and adjacent columns of the original plaintext image; The problem of the same key stream used by the traditional algorithm to encrypt different images is changed; through the gray value diffusion operation of the image, the mutual influence between two adjacent pixels is established, and the key directly participates in the output of the ciphertext image; Although the invention can partially effectively prevent brute force attacks, the key stream used in the image encryption process has nothing to do with the plaintext image, which leads to the same key stream used when encrypting different images.

Therefore, there are certain common problems in the way of image encryption using chaotic encryption method. Although it can resist the known plaintext system attack, the feature "pixel sum" of the plaintext image does not change before the diffusion, which is easy to cause differential attacks; the secret key is only used to generate the key stream in the encryption process, and does not directly participate in the ciphertext image The encryption algorithm only considers the scrambling of the pixel position of the image, the security of the final output file depends entirely on the length of the key, and the encryption speed is slow, which cannot meet some simple and fast encryption requirements.

Contents of the invention

Purpose of the invention: the purpose of this invention is to provide a kind of FPGA-based image encryption method that carries out real-time encryption protection to image quickly and effectively.

Technical scheme: encryption method of the present invention comprises the steps: (1) FPGA initializes DRAM; (2) FPGA reads original image; (3) FPGA obtains the timing information of original image, and FPGA sets up random sequence; ( 4) Carry out encryption operation and store the image respectively.

In step (3), the FPGA reads the information in the random access memory DDR to obtain the row synchronization signal, field synchronization signal, row rear edge signal, row front edge signal, column rear edge information, column front edge information, and row enable signal pixels of the original image Point data information; when encountering the pixel clock Pclk signal, the FPGA simultaneously counts the horizontal synchronization Hsync and the vertical synchronization Vsync of the original image.

In step (3), the internal D flip-flops and gate circuits of the FPGA form a random sequence; there are 8 D flip-flops, 3 AND gates, and 4 XOR gate circuits, which are combined to form random sequences of different combination sequences; _{FR( X)} [7:0], F _G(X) [7:0], F _B(X) [7:0] 3 random sequence generators and the position of the gate digital circuit remains unchanged, and the XOR digital circuit signal In order to start from DFF0 and shift back one bit respectively; the random sequence _FR(X) , F _G(X) and F _B(X) has an initial value, and the initial value is a fixed value, which is determined by the horizontal synchronization signal Hsync or the field synchronization signal Vsync decides.

In step (4), row operation and column operation are respectively performed on the encrypted signal to obtain effective row enable DE, and finally obtain a new encrypted image signal, and store it in the dynamic random access memory (DDR).

Beneficial effects: Compared with the prior art, the present invention has the following remarkable effects: 1. There is no requirement for the length of the key, and the scope of application is wider; 2. By adding a simple random sequence with known initial values, the image Data encryption requirements, high security performance, avoiding data loss due to too slow encryption speed, and improving image data encryption processing efficiency; 3. The initial value of the added random sequence combination is known, the pixel clock Pclk signal is known, and operability High, high degree of restoration; 4. The generation of random sequences is arbitrary and diverse, and the generated key streams are also diverse, with stronger encryption effects and higher practicality.

Description of drawings

Fig. 1 is the step flowchart of image encryption of the present invention;

Fig. 2 is a schematic diagram of the image encryption process of the present invention;

Fig. 3 is a schematic diagram of the random sequence generator of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Figure 1 is a flow chart of the image encryption steps of the present invention, Figure 2 is the specific steps of the present invention, and Figure 3 is a schematic diagram of the random sequence generator of the present invention. The image encryption method concrete steps of the present invention are as follows:

(1) The FPGA initializes the external DRAM, and enables the external DRAM to read data normally.

(2) An image is composed of three colors of RGB, and the FPGA reads the original image, and the 8 bits of red, green and blue are represented as R[7:0], G[7:0], and B[7:0] respectively.

(3) The FPGA reads the information in the random access memory DDR to obtain the timing information of the original image. Obtain the pixel point data information of the original image's line synchronization signal, field synchronization signal, line back edge signal, line front edge signal, column back edge information, column front edge information, row enable signal, etc.

FPGA internal D flip-flops and gate circuits form a random sequence. There are a total of 8 D flip-flops, 3 AND gates, and 4 XOR gate circuits, which are combined to form random sequences of different combination sequences. Among them, FR _(X) [7:0], F _G(X) [7:0], F _B(X) [7:0] 3 random sequence generators and gate digital circuit positions remain unchanged, The XOR digital circuit signals are sequentially shifted backward by one bit starting from DFF0. Digital circuits are clear and complex. In the end, random time series with different numbers are obtained, all of which are 8-bit variables.

(3-1) When encountering the pixel clock Pclk signal, the FPGA simultaneously counts the horizontal synchronization Hsync and the vertical synchronization Vsync of the original image.

(3-2) Consider the size of an image as V rows and H columns, that is, each row has H pixels, and there are V rows in total. When the row synchronous Hsync signal and row valid data counting of one row is over, enter a new column and perform the data operation of the next row. When the counting of the field synchronous Vsync signal and field valid data ends, it means that the reading of one frame of image ends.

(3-3) The random sequences FR _(X) , F _G(X) and F _B(X) have initial values, and the initial values are fixed values, which are determined by the horizontal synchronization signal Hsync or the vertical synchronization signal Vsync. But the numerical value of the random sequence changes with the pixel clock Pclk, and there is no specific rule.

(3-4) When the pixel clock Pclk signal is encountered, the result of the XOR encryption operation between the random sequence _FR(X) [7:0] and the original image R[7:0] is output as red;

The F _G(X) [7:0] of the random sequence and the G[7:0] of the original image are XORed and encrypted as a green output;

The result of the XOR encryption operation between F _B(X) [7:0] of the random sequence and B[7:0] of the original image is output in blue.

(4) Row operation and column operation are respectively performed on the encrypted R, G, and B signals to obtain an effective row enable DE, and finally obtain a new encrypted image signal, and store it in the dynamic random access memory DDR.

Claims (3)

1. An image encryption method based on FPGA, characterized in that: comprises the following steps: (1) FPGA initializes DRAM; (2) FPGA reads original image; (3) FPGA obtains the timing information of original image, and FPGA Establish a random sequence; (4) perform encryption operations and store images separately; In step (3), the FPGA reads the information in the random access memory DDR to obtain the row synchronization signal, field synchronization signal, row trailing edge signal, row leading edge signal, column trailing edge information, column leading edge information, and pixels of the row enable signal of the original image Point data information; When the pixel clock Pclk signal is encountered, the FPGA simultaneously counts the horizontal synchronization Hsync and the vertical synchronization Vsync of the original image; In step (3), the internal D flip-flops and gate circuits of the FPGA form a random sequence; there are 8 D flip-flops, 3 AND gates, and 4 XOR gate circuits, which are combined to form random sequences of different combination sequences; F _{R( X)} [7:0], F _G(X) [7:0], F _B(X) [7:0] 3 random sequence generators, the position of the AND gate digital circuit remains unchanged, and the XOR digital circuit signal In order to start from DFF0 and move backward one by one respectively. 2. the image encryption method based on FPGA according to claim 1, is characterized in that, random sequence FR _(X) , F _{G (X)} , F _{B (X)} has initial value, and initial value is fixed value, It is determined by the horizontal sync signal Hsync or the vertical sync signal Vsync. 3. The image encryption method based on FPGA according to claim 1, characterized in that, in step (4), row operation and column operation are respectively performed on the encrypted signal to obtain effective row enable DE, and finally obtain a new encryption The image signal is stored in the dynamic random access memory (DDR).

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