CN111932430B - Image encryption method based on FPGA - Google Patents

Image encryption method based on FPGA Download PDF

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CN111932430B
CN111932430B CN202010040430.1A CN202010040430A CN111932430B CN 111932430 B CN111932430 B CN 111932430B CN 202010040430 A CN202010040430 A CN 202010040430A CN 111932430 B CN111932430 B CN 111932430B
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fpga
image
row
encryption
signal
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CN111932430A (en
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严飞
刘伟奇
蔡静怡
刘银萍
陆宝毅
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Nanjing University of Information Science and Technology
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Nanjing University of Information Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/0021—Image watermarking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

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Abstract

The invention discloses an image encryption method based on an FPGA, which comprises the following steps: initializing a dynamic random access memory by an FPGA; (2) the FPGA reads the original image; (3) The FPGA acquires time sequence information of an original image, and establishes a random sequence; (4) respectively performing encryption operation and storing the image. The invention has no requirement on the length of the key and has wider application range; the requirement on image data encryption can be met by adding a simple random sequence with a known initial value, the security performance is high, the data loss caused by too slow encryption speed is avoided, and the image data encryption processing efficiency is improved; the added random sequence combination initial value is known, the pixel clock Pclk signal is known, the operability is high, and the reduction degree is high; the random sequence is generated randomly and variously, the generated key stream is also diversified, the encryption effect is stronger, and the practicability is higher.

Description

Image encryption method based on FPGA
Technical Field
The invention relates to an image encryption method, in particular to an image encryption method based on an FPGA.
Background
Image encryption techniques can be generally divided into two categories, namely, spatial domain image encryption techniques and compressed image encryption techniques. According to the invention, CN 107659753B mainly provides a compression encryption method for an image, wherein T hash operations are carried out on an initial key, a measurement matrix is obtained according to T hash values, and half tensor compression sensing is carried out on the column vector by using the measurement matrix so as to obtain an encrypted image; the invention has better confidentiality, but the strong correlation between adjacent rows and adjacent columns of the original plaintext image has large calculation amount and low speed, the security completely depends on the length of the secret key, and the operability is still to be improved. For example, the invention patent CN 105513002B changes the pixel sum of the image by the modulo operation between rows and the modulo operation between columns, and breaks the strong correlation between the adjacent rows and the adjacent columns of the original plain image; the problem of the same key stream adopted when the traditional algorithm encrypts different images is solved; establishing the mutual influence between two adjacent pixels through the gray value diffusion operation of the image, wherein the secret key directly participates in the output of the ciphertext image; although the invention can partially and effectively prevent violent attacks, the key stream used in the encryption process of the image is irrelevant to the plaintext image, so that the key stream used in the encryption of different images is consistent.
Therefore, the image encryption method using the chaotic encryption method has a certain common problem. Although the method can resist the attack of the known plaintext system, the characteristics of the plaintext image, namely 'pixel sum', are not changed before diffusion, so that differential attack is easy to cause; the secret key is only used for generating a key stream in the encryption process and does not directly participate in the acquisition of the ciphertext image; the encryption algorithm only considers the scrambling of the pixel positions of the image, the security of the final output file completely depends on the length of the key, the encryption speed is low, and some concise and rapid encryption requirements cannot be met.
Disclosure of Invention
The invention aims to: the invention aims to provide an FPGA-based image encryption method for quickly and effectively carrying out real-time encryption protection on images.
The technical scheme is as follows: the encryption method comprises the following steps: initializing a dynamic random access memory by an FPGA; (2) the FPGA reads the original image; (3) The FPGA acquires time sequence information of an original image, and establishes a random sequence; (4) respectively performing encryption operation and storing the image.
In the step (3), the FPGA reads information in the random access memory DDR to obtain a row synchronous signal, a field synchronous signal, a row trailing edge signal, a row leading edge signal, column trailing edge information, column leading edge information and pixel point data information of a row enabling signal of an original image; when encountering the pixel clock Pclk signal, the FPGA counts the row synchronization Hsync and the field synchronization Vsync for the original image at the same time.
In the step (3), a random sequence is formed by a D trigger and a gate circuit in the FPGA; a total of 8D flip-flops, 3 AND gates, 4The exclusive OR gate circuits are respectively combined to form random sequences of different combined sequences; f (F) R(X) [7:0]、F G(X) [7:0]、F B(X) [7:0]The positions of the 3 generators of random sequences and the gate digital circuit are unchanged, and the exclusive or digital circuit signals are respectively and sequentially shifted one bit from the DFF 0; random sequence F R(X) 、F G(X) 、F B(X) Has an initial value, and the initial value is a fixed value, and is determined by the row synchronization signal Hsync or the field synchronization signal Vsync.
In the step (4), row operation and column operation are respectively carried out on the signals of the encryption operation, so that an effective row enable DE is obtained, and finally, a new encrypted image signal is obtained and stored in a dynamic random access memory DDR.
The beneficial effects are that: compared with the prior art, the invention has the following remarkable effects: 1. the length of the key is not required, and the application range is wider; 2. the requirement on image data encryption can be met by adding a simple random sequence with a known initial value, the security performance is high, the data loss caused by too slow encryption speed is avoided, and the image data encryption processing efficiency is improved; 3. the added random sequence combination initial value is known, the pixel clock Pclk signal is known, the operability is high, and the reduction degree is high; 4. the random sequence is generated randomly and variously, the generated key stream is also diversified, the encryption effect is stronger, and the practicability is higher.
Drawings
FIG. 1 is a flowchart illustrating steps for image encryption according to the present invention;
FIG. 2 is a schematic diagram of an image encryption process according to the present invention;
fig. 3 is a schematic diagram of a random sequence generator according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
Fig. 1 is a flowchart showing the steps of image encryption according to the present invention, fig. 2 is a flowchart showing the specific steps of the present invention, and fig. 3 is a diagram showing a random sequence generator according to the present invention. The image encryption method specifically comprises the following steps:
(1) The FPGA initializes the external dynamic random access memory and enables the external dynamic random access memory to read data normally.
(2) One image consists of RGB three colors, and the FPGA reads the original image, and each 8 bits of RGB is respectively represented as R7:0, G7:0 and B7:0.
(3) The FPGA reads information in the DDR, and time sequence information of an original image is obtained. And obtaining pixel point data information of a line synchronous signal, a field synchronous signal, a line trailing edge signal, a line leading edge signal, column trailing edge information, column leading edge information, a line enabling signal and the like of the original image.
The D flip-flops and gates within the FPGA form a random sequence. A total of 8D flip-flops, 3 AND gates and 4 exclusive OR gates are combined to form random sequences of different combined sequences. Wherein F is R(X) [7:0]、F G(X) [7:0]、F B(X) [7:0]The positions of the 3 generators of random sequences and the AND gate digital circuit are unchanged, and the exclusive OR digital circuit signals are respectively shifted one bit after each other from the DFF 0. Digital circuits are clear and complex. Finally, the random time sequences with different numbers are obtained and are all 8bit variables.
(3-1) when encountering the pixel clock Pclk signal, the FPGA counts the row sync Hsync and the field sync Vsync for the original image at the same time.
(3-2) the size of one image is regarded as V rows and H columns, i.e., H pixels per row, for a total of V rows. When the row synchronization Hsync signal and the row valid data count of one row are finished, a new column is entered and the data operation of the next row is performed. When the field sync Vsync signal and the field valid data count end, it indicates that one frame image reading ends.
(3-3) random sequence F R(X) 、F G(X) 、F B(X) Has an initial value, and the initial value is a fixed value, and is determined by the row synchronization signal Hsync or the field synchronization signal Vsync. But the value of the random sequence varies with the pixel clock Pclk, with no particular regularity.
(3-4) when encountering the pixel clock Pclk signal, F of random sequence R(X) [7:0]R7:0 with original image]The result of exclusive or encryption operation is output as red;
f of random sequence G(X) [7:0]G [7:0] with the original image]The result of the exclusive or encryption operation is taken as green output;
f of random sequence B(X) [7:0]B [7:0] with the original image]The result of the exclusive or encryption operation is output as blue.
(4) And respectively performing row operation and column operation on the R, G, B signals of the encryption operation to obtain an effective row enable DE, finally obtaining a new encrypted image signal, and storing the new encrypted image signal into a dynamic random access memory DDR.

Claims (3)

1. An image encryption method based on FPGA is characterized in that: the method comprises the following steps: initializing a dynamic random access memory by an FPGA; (2) the FPGA reads the original image; (3) The FPGA acquires time sequence information of an original image, and establishes a random sequence; (4) performing encryption operation and storing the image respectively;
in the step (3), the FPGA reads information in the random access memory DDR to obtain a row synchronous signal, a field synchronous signal, a row trailing edge signal, a row leading edge signal, column trailing edge information, column leading edge information and pixel point data information of a row enabling signal of an original image;
when encountering a pixel clock Pclk signal, the FPGA counts the row synchronization Hsync and the field synchronization Vsync of the original image at the same time;
in the step (3), a random sequence is formed by a D trigger and a gate circuit in the FPGA; a total of 8D triggers, 3 AND gates and 4 exclusive OR gates are combined to form random sequences of different combined sequences respectively; f (F) R(X) [7:0]、F G(X) [7:0]、F B(X) [7:0]The positions of the 3 generators of random sequences and the AND gate digital circuit are unchanged, and the exclusive OR digital circuit signals are respectively shifted one bit after each other from the DFF 0.
2. The FPGA-based image encryption method according to claim 1, wherein the random sequence F R(X) 、F G(X) 、F B(X) Has an initial value, and the initial value is a fixed value, and is determined by the row synchronization signal Hsync or the field synchronization signal Vsync.
3. The FPGA-based image encryption method according to claim 1, wherein in step (4), the encryption signals are respectively subjected to row operation and column operation to obtain an effective row enable DE, and a new encrypted image signal is finally obtained and stored in the dynamic random access memory DDR.
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