CN111931923B - Near memory computing system - Google Patents
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- 239000003990 capacitor Substances 0.000 claims description 8
- 238000004364 calculation method Methods 0.000 claims description 4
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- 239000010703 silicon Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000013473 artificial intelligence Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000013528 artificial neural network Methods 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4818—Threshold devices
- G06F2207/4824—Neural networks
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Abstract
The invention discloses a near-memory computing system, which comprises a plurality of computing nodes. Each operation node receives a plurality of input signals and outputs operation result signals. Each operation node comprises a plurality of nonvolatile memory units and a processing circuit. Each nonvolatile memory cell stores a weight value in a write operation and outputs a weight signal according to the weight value in a read operation. The processing circuit is coupled to the plurality of nonvolatile memory cells. The processing circuit receives a plurality of input signals and calculates a plurality of weight signals generated by a plurality of nonvolatile memory units to generate operation result signals. The plurality of nonvolatile memory cells and the processing circuit are fabricated by different or the same processes.
Description
Technical Field
The present invention relates to a near-memory computing system, and more particularly, to a near-memory computing system capable of performing analog operations.
Background
As artificial intelligence (artificial intelligence, AI) is applied to more and more fields, and since algorithms of artificial intelligence require a large amount of operations, there is also an increasing demand for hardware suitable for the operations of artificial intelligence. In general, artificial intelligence systems must process a large number of operations in a short time to make accurate predictions or decisions, so data operations are typically processed in a parallel fashion.
Neural networks are a common type of artificial intelligence system. The neural network comprises a plurality of nodes, each node can receive data from other nodes to perform operation, and the operation result can be used by other nodes as input data. Because artificial intelligence operates on large amounts of data, the data is typically stored in external memory and stored in internal memory when needed. Thus, the bandwidth of accessing data will significantly affect the instruction cycle of the artificial intelligence system, and the energy consumption required to access data will also burden the artificial intelligence system.
Disclosure of Invention
An embodiment of the invention provides a near memory computing system. The near memory computing system comprises a plurality of computing nodes, wherein each computing node is used for receiving a plurality of input signals and outputting a computing result signal.
Each operation node comprises a plurality of nonvolatile memory units and a processing circuit. Each nonvolatile memory cell stores a weight value in a write operation and outputs a weight signal according to the weight value in a read operation. The processing circuit is coupled to the plurality of nonvolatile memory cells. The processing circuit receives a plurality of input signals and calculates a plurality of weight signals generated by a plurality of nonvolatile memory units to generate operation result signals.
The plurality of nonvolatile memory units and the processing circuit are arranged on two different chips, and the processing circuit and the plurality of nonvolatile memory units are directly coupled with each other between the two chips through face-to-face welding or a plurality of through silicon vias.
Another embodiment of the present invention provides a near memory computing system. The near memory computing system comprises a plurality of computing nodes, wherein each computing node is used for receiving a plurality of input signals and outputting a computing result signal.
Each operation node comprises a plurality of nonvolatile memory units and a processing circuit. Each nonvolatile memory cell stores a weight value in a write operation and outputs a weight signal according to the weight value in a read operation. The processing circuit is coupled to the plurality of nonvolatile memory cells. The processing circuit receives a plurality of input signals and calculates a plurality of weight signals generated by a plurality of nonvolatile memory units to generate operation result signals.
The near memory computing system is formed on a system-on-chip, and the processing circuit is directly coupled to the plurality of nonvolatile memory cells through connection structures on the chip.
Drawings
FIG. 1 is a schematic diagram of a near memory computing system according to an embodiment of the invention.
FIG. 2 is a schematic diagram of an operation node according to an embodiment of the present invention.
FIG. 3 is a diagram showing a connection structure between a nonvolatile memory cell and a processing circuit according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of a nonvolatile memory cell according to an embodiment of the invention.
Wherein reference numerals are as follows:
10 near memory computing system
100 arithmetic node
L1 to LN layer
1101-110X nonvolatile memory cell
120 processing circuit
1221 to 122X operating units
CT: control transistor
CM current mirror
BD (BD: welding structure)
SIG WT1- To SIG WTX Weight signal
SIG WI1- To SIG WIX Weighted input signal
SIG IN1- To SIG INX Input signal
SW1, SW2 switch
T1A, T A transistor
SIG ctrl1 、SIG ctrl2 Control signal
VS1 first system voltage terminal
VS2 second system voltage terminal
I WT1 To I WTX Current flow
I W1 To I WX Weight current
C1 capacitance
CMP comparator
SIG CR Calculation result signal
Vref, reference voltage
CP1, CP2 chip
111 first selection transistor
112 floating gate transistor
113 second selection transistor
114 control assembly
115 purge assembly
SL source line
BL bit line
CL control line
EL clearing line
Detailed Description
FIG. 1 is a schematic diagram of a near memory computing system 10 according to an embodiment of the invention. Near memory system 10 may include a plurality of compute nodes 100. Each of the operation nodes 100 may receive a plurality of input signals and may output an operation result signal.
In some embodiments, the near memory computing system 10 may be applied in a neural network to perform operations of artificial intelligence. That is, the plurality of operation nodes 100 may be connected to each other through a hierarchical structure, so that an operation result signal generated by one operation node may be used as an input signal of another operation node. For example, in fig. 1, the operation node 100 may be divided into a plurality of layers L1 to LN, where N is an integer greater than 1. The operation node of the first layer L1 receives the input signal given by the system, and the operation node of the second layer L2 receives the operation result signal generated by the operation node of the first layer as the input signal.
Fig. 2 is a schematic diagram of an operation node 100 according to an embodiment of the present invention. In fig. 2, the operation node 100 may include a plurality of nonvolatile memory units 1101 to 110X and a processing circuit 120, where X is an integer greater than 1. In some embodiments, each of the nonvolatile memory cells 1101 to 110X may store a weight value in a write operation and may output a weight signal according to the stored weight value in a read operation.
The processing circuit 120 may be connected toReceiving input signal SIG IN1 To SIG INX And can be applied to input signal SIG IN1 To SIG INX And weight signals SIG generated by nonvolatile memory units 1101 to 110X WT1 To SIG WTX Performing an operation to generate an operation result signal SIG- CR . For example, the processing circuit 120 may convert each input signal SIG IN1 To SIG INX And weight signal SIG WT1 To SIG WTX Multiplying the corresponding weight signals and taking the sum of the products as an operation result signal SIG CR 。
In the prior art, the weight value is stored in the external memory, so the processing circuit 120 must access the weight value in the memory system through the bus. Because artificial intelligence operations require large amounts of data, accessing large amounts of data from memory often takes a lot of time, resulting in reduced operation performance. However, in the operation node 100. Since the processing circuit 120 can be directly coupled to the nonvolatile memory cells 1101 to 110X, the time required to access the memory data can be significantly shortened.
In addition, in some embodiments, the nonvolatile memory cells 1101-110X and the processing circuit 120 may be manufactured by different processes to achieve a better balance of cost and performance. Fig. 3 shows a connection structure between nonvolatile memory cells 1101 to 110X and processing circuit 120 according to an embodiment of the present invention. In fig. 3, the processing circuit 120 and the nonvolatile memory units 1101 to 110X may be provided on different chips CP1 and CP 2. In this case, the processing circuit 120 may be directly coupled to the processing circuit 120 and the nonvolatile memory units 1101 to 110X through a face-to-face solder structure (face-to-face bonding structures) BD between the chips CP1 and CP 2. That is, micro bumps (micro bumps) of the chips CP1 and CP2 may be directly soldered to each other.
However, in some embodiments, chip stack soldering techniques may also be used to connect the processing circuit 120 and the nonvolatile memory cells 1101-110X. For example, the processing circuit 120 and the nonvolatile memory units 1101-110X may be coupled to each other through-silicon vias (through silicon vias, TSVs) between the chips CP1 and CP 2. Furthermore, in some embodiments, the near memory computing system 10 may be formed in a system-on-a-chip (SOC), and the processing circuit 120 may be directly coupled to the nonvolatile memory cells 1101-110X through on-chip interconnect structures.
In addition to the fact that the near memory system 10 can reduce the time required for accessing the memory by directly coupling the processing circuit 120 and the nonvolatile memory units 1101 to 110X, the operation node 100 can also utilize the analog weight signal SIG generated by the nonvolatile memory units 1101 to 110X WT1 To SIG WTX Analog operations are performed to reduce the burden of complex operations.
In some embodiments, the nonvolatile memory cell 100 may be written to and have different write states to store different weight values. For example, in a write operation, each nonvolatile memory cell 1101-110X may be verified with a corresponding specific current or voltage according to the weight value to be stored. In this case, in the read operation, each of the nonvolatile memory cells 1101 to 110X will also output a weight signal having a specific current value or a specific voltage value according to the writing state thereof.
For example, in fig. 2, the weight signals SIG generated by the nonvolatile memory units 1101 to 110X WT1 To SIG WTX May be a current I WT1 To I WTX . In this case, if the weight value stored in the nonvolatile memory unit 1101 is greater than the weight value stored in the nonvolatile memory unit 110X, the weight signal SIG WT1 Is the current I of (2) WT1 Will be greater than the weight signal SIG WTX Is the current I of (2) WTX 。
In this case, the processing circuit 120 will be at current I WT1 To I WTX Form of receiving weight signal SIG WT1 To SIG WTX And can utilize weight signal SIG WT1 To SIG WTX To perform analog operations. For example, the processing circuit 120 may include a plurality of operation units 1221 to 122X. Each of the operation units 1221 to 122X may be coupled to a corresponding one of the nonvolatile memory units 1101 to 110XAnd (5) a meta. For example, the operation unit 1221 may be coupled to the nonvolatile memory unit 1101, and the operation unit 122X may be coupled to the nonvolatile memory unit 110X.
In fig. 2, each of the operation units 1221 to 122X may include a current mirror CM and a control transistor CT. The current mirror CM may be coupled to the corresponding nonvolatile memory cell and may replicate the weight signal generated by the corresponding nonvolatile memory cell to generate the weight current. For example, the current mirror CM of the operation unit 1221 may copy the weight signal SIG generated by the nonvolatile memory unit 1101 WT1 I.e. current I WT1 And generates a weighting current I W1 While the current mirror CM of the operation unit 122X can copy the weight signal SIG generated by the nonvolatile memory unit 110X WTX I.e. current I WTX And generates a weighting current I WX 。
In addition, the control transistor CT has a first end, a second end and a control end, wherein the first end of the control transistor CT can receive the weight current, the second end of the control transistor CT can output the weight input signal, and the control end of the control transistor CT can receive the input signal SIG IN1 To SIG INX Corresponding to the input signal. In some embodiments, each input signal SIG IN1 To SIG INX The duration of (2) may represent the input value to which it corresponds. For example, if the signal SIG is input IN1 Represented input values greater than input signal SIG INX Representative input value, input signal SIG IN1 The duration (pulse width) of the signal is longer than the input signal SIG INX Is not shown, is not shown.
In this case, during the calculation, the first terminal of the control transistor CT of the operation unit 1221 will receive the AND weight signal SIG WT1 Related weighting current I W1 The control terminal of the control transistor CT of the operation unit 1221 receives the input signal SIG IN1 So that the control transistor CT is turned on for the duration of its pulse. Therefore, it corresponds to the operation unit 1221 inputting the signal SIG -IN1 And weight signal SIG WT1 Multiplying to produce a weighted input signal SIG WI1 . Similarly, the operation unit 122X will be based on the input signal SIG -INX Weight signal SIG WTX Generates a weighted input signal SIG by the product of (1) WIX 。
In FIG. 2, the processing circuit 120 may further include a capacitor C1 to weight the input signal SIG WI1 To SIG WIX Integration is performed. The capacitor C1 has a first end and a second end, the first end of the capacitor C1 may be coupled to the second end of the control transistor CT of the operation unit 1221 to 122X, and the second end of the capacitor C1 may be coupled to the first system voltage end VS1. In this case, during the operation, the capacitor C1 will be weighted by the input signal SIG WI1 To SIG WIX And outputs a final voltage via the first terminal of the capacitor C1.
In addition, the processing circuit 120 may further include a comparator CMP for comparing the operation result signal SIG CR Compared with the reference voltage Vref, a pulse signal is generated for the next operation node to be directly used as an input signal. However, in some embodiments, the processing circuit 120 may include other components to generate the operation result signal SIG with a desired form according to the system requirements CR 。
Furthermore, in fig. 2, the current mirror CM may include transistors T1A and T2A and switches SW1 and SW2. The transistor T1A has a first terminal, a second terminal and a control terminal, the first terminal of the transistor T1A may be coupled to the second system voltage terminal VS2, and the second terminal of the transistor T1A may be coupled to the corresponding nonvolatile memory cell. The transistor T2A has a first terminal, a second terminal and a control terminal, the first terminal of the transistor T2A may be coupled to the second system voltage terminal VS2, the second terminal of the transistor T2A may be coupled to the first terminal of the control transistor CT, and the control terminal of the transistor T2A may be coupled to the control terminal of the transistor T1A. The switch SW1 has a first end, a second end and a control end, the first end of the switch SW1 is coupled to the second system voltage end VS2, the second end of the switch SW1 is coupled to the control end of the transistor T1A, and the control end of the switch SW1 receives the control signal SIG ctrl1 . The switch SW2 has a first end, a second end and a control end, the first end of the switch SW2 is coupled to the control end of the transistor T1A, and the second end of the switch SW2 is coupled to the transistor T1A, and a control terminal of the switch SW2 receives the control signal SIG ctrl2 。
In this case, the transistors T1A and T2A can be used to copy the weight signal generated by the corresponding nonvolatile memory cell, and the switches SW1 and SW2 can be used to control the operation timing to increase the operation accuracy.
For example, when the operation node 100 is in the standby mode, the nonvolatile memory units 1101 to 110X of the operation node 100 may be in a read state and ready to output the weight signal SIG WT1 To SIG WTX . However, in the standby mode, the switches SW1 of the operation units 1221 to 122X in the processing circuit 120 will be turned on, and the switches SW2 of the operation units 1221 to 122X in the processing circuit 120 will be turned off. In this case, the transistors T1A and T2A will be turned off, and the current mirror CT of the operation units 1221 to 122X will be disabled. In this way, the control transistors CT of the operation units 1221 through 122X do not receive the weighting current I even though the nonvolatile memory units 1101 through 110X are already in the read state W1 To I WX 。
In some embodiments, the input signal SIG is received at the processing circuit 120 IN1 To SIG INX And before starting the operation, the operation node 100 will first enter the preparation mode so that the weight signal SIG WT1 To SIG WTX Is the current I of (2) WT1 To I WTX Parasitic capacitances on the paths of nonvolatile memory cells 1101-110X to processing circuit 120 may be pre-charged first.
For example, when the operation node 100 is in the standby mode, the nonvolatile memory units 1101 to 110X of the operation node 100 may be in the read state, the switch SW1 in the operation units 1221 to 122X of the processing circuit 120 may be turned off, and the switch SW2 in the operation units 1221 to 122X of the processing circuit 120 may be turned on. In this case, the current mirror CM of the operation units 1221 to 122X of the processing circuit 120 is enabled, and the weighting signal SIG WT1 To SIG WTX Is the current I of (2) WT1 To I WTX Parasitic capacitances between nonvolatile memory cells 1101-110X and processing circuit 120 are precharged. However, the method is thatMeanwhile, since the control transistors CT of the operation units 1221 to 122X have not received the input signal SIG yet IN To SIG INX Therefore, the control transistor CT is still turned off, and the operation node 100 does not operate in the standby mode.
In some embodiments, the nonvolatile memory cells 1101 to 110X and the processing circuit 120 are disposed on different chips and can be coupled by soldering micro bumps, so that the paths coupling the nonvolatile memory cells 1101 to 110X have larger parasitic capacitance and require longer charging time. However, if the nonvolatile memory cells 1101-110X and the processing circuit 120 are disposed on the same chip and coupled by on-chip interconnect structures, the charge time required for parasitic capacitance may be relatively short. That is, the duration of the preparation mode can be determined according to the requirements of the actual conditions.
After the ready mode, the computing node will enter the operational mode to perform the operation. When the operation node is in the operation mode, the nonvolatile memory units 1101 to 110X of the operation node 100 may be in a read state, the switches SW1 of the operation units 1221 to 122X of the processing circuit 120 may be turned off, and the switches SW2 of the operation units 1221 to 122X of the processing circuit 120 may be turned on. In addition, the control transistors CT of the operation units 1221 to 122X of the processing circuit 120 are turned on for a corresponding length of time according to the received input signal, and the weighting current I generated by the current mirror CM of the operation units 1221 to 122X W1 To I WX The capacitor C1 will be charged during the time the control transistor CT is turned on.
In some embodiments, the timing of performing the operation is predictable because the operation result signal generated by one operation node is used as an input signal by another operation node. In this case, when there is an operation node in the operation mode, the next operation node may first enter the standby mode in preparation for performing the next operation. For example, in fig. 1, when the operation node 100 of the first layer L1 is in the operation mode, the operation nodes of the second layer L2 can enter the preparation mode at the same time. Furthermore, in some embodiments, if the operation node 100 requires a longer time to charge the parasitic capacitance, it may take a longer time to lengthen the preparation mode. In this case, when the operation node 100 of the first layer L1 is in the operation mode, the operation node of the third layer L3 may also enter the standby mode at the same time. In this way, the operation node of the third layer L3 can take a longer time to charge the parasitic capacitance before the operation node of the third layer L3 starts operation.
Fig. 4 is a schematic diagram of a nonvolatile memory cell 1101 according to an embodiment of the present invention. In some embodiments, nonvolatile memory cells 1101-110X may have the same structure. In fig. 4, the nonvolatile memory cell 1101 may include a first select transistor 111, a floating gate transistor 112, a second select transistor 113, a control component 114, and a clear component 115.
The first selection transistor 111 has a first terminal, a second terminal and a control terminal, the first terminal of the first selection transistor 111 may be coupled to the source line SL, and the control terminal of the first selection transistor 111 may be coupled to the selection gate line SGL. The floating gate transistor 112 has a first end, a second end, and a floating gate end, and the first end of the floating gate transistor 112 may be coupled to the second end of the first selection transistor 111. The second selection transistor 113 has a first terminal, a second terminal, and a control terminal, the first terminal of the second selection transistor 113 may be coupled to the second terminal of the floating gate transistor 112, the second terminal of the second selection transistor 113 may be coupled to the bit line BL, and the control terminal of the second selection transistor 113 may be coupled to the word line WL.
The control element 114 has a first end and a second end, the first end of the control element 114 may be coupled to the floating gate end of the floating gate transistor 112, and the second end of the control element 114 may be coupled to the control line CL. The clearing element 115 has a first end and a second end, the first end of the clearing element 115 may be coupled to the floating gate end of the floating gate transistor 112, and the second end of the clearing element 115 may be coupled to the clearing line EL. In some embodiments, the control element 114 and the cleaning element 115 may be capacitive elements and may be implemented using transistors. In this case, the first end of the control element 114, the second end of the clearing element 115 and the floating gate end of the floating gate transistor 112 may be coupled via the same crystalline silicon layer, and the second end of the control element 114 and the second end of the clearing element 115 may be the source/drain ends of the two transistors implementing the control element 114 and the clearing element 115.
In addition, since the coupling area of the control element 114 is large, the voltage at the floating gate terminal will be dominated by the control element 114. That is, the floating gate terminal may be coupled to the voltage of the control line CL via the control component 114. Thus, the control component 114 can be employed to perform a write operation.
For example, in a write operation, the control line CL may be at a write voltage, the select gate line SGL and the word line WL may be at an operating voltage, and the bit line BL and the source line may be at a reference voltage. The write voltage may be greater than the operating voltage, and the operating voltage may be greater than the reference voltage. In this case, the first and second selection transistors 111 and 113 are turned on, so that the first and second terminals of the floating gate transistor 112 receive the reference voltage, and the floating gate terminal of the floating gate transistor 112 is coupled to the write voltage. Thus, a large voltage differential across the floating gate transistor 112 will cause Fowler-Nordheim tunneling (FN tunneling) electrons to be trapped by the floating gate of the floating gate transistor 112, thereby changing the writing state of the nonvolatile memory cell 1101.
In addition, in a read operation, the source line SL, the control line CL, and the clear line EL may be at a reference voltage, the select gate line SGL and the word line WL may be at an operating voltage, and the bit line BL may be precharged to a read voltage slightly greater than the reference voltage. In this case, the first and second select transistors 111 and 113 will be turned on, while the nonvolatile memory cell 1101 will induce a corresponding magnitude of read current according to its write state.
In general, the more electrons are trapped by floating gate transistor 112, the less current is drawn by floating gate transistor 112 during a read operation. Therefore, in the write operation, the number of times of applying the write voltage can be adjusted according to the weight value to be stored, and after each application of the write voltage, the nonvolatile memory cell 1101 is verified with the corresponding current value, and if the corresponding current value is not reached, the write voltage is continuously applied until the nonvolatile memory cell 110 reaches the desired write state.
That is, if the weight value to be stored in the nonvolatile memory cell 1101 is smaller, the nonvolatile memory cell 1101 may be applied with a write voltage more times, so that the nonvolatile memory cell 1101 can generate a smaller current in a read operation.
Furthermore, the coupling area of the erasing element 115 is relatively small, and thus can be used to erase the written state of the nonvolatile memory cell 1101. For example, in a erase operation, the first and second terminals of the floating gate transistor 112 may receive a reference voltage, and the erase line EL may be at an erase voltage similar to the write voltage. In this case, the high voltage applied to the erase line EL will be able to re-direct the electrons to tunnel and release the electrons trapped by the floating gate of the floating gate transistor 112 through the erase element 115.
Although fig. 4 illustrates an example of the nonvolatile memory 1101 of the present invention, the present invention is not limited thereto, and the nonvolatile memory units 1101 to 110X may be implemented by other structures in other embodiments of the present invention. For example, the nonvolatile memory cells 1101-110X may be implemented using other write-many (Multiple Time Programmable, MTP) memory cells or variable resistive memory (Resistive Random Access Memory, RRAM) cells. In addition, the weight signal SIG WT1 To SIG WTX The non-volatile transistor cells 1101 to 1101X may be transmitted in a row of voltage signals or current signals in accordance with structural characteristics thereof.
In summary, the near-memory computing system provided by the embodiments of the invention can directly couple the processing circuit with the memory unit and can receive the analog signal from the memory unit to perform the analog operation. Thus, the burden of accessing external memory and performing complex operations can be significantly reduced when executing artificial intelligence algorithms.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A near memory computing system, comprising:
each operation node is used for receiving a plurality of input signals and outputting operation result signals, and each operation node comprises:
a plurality of nonvolatile memory cells, each for storing a weight value in a write operation and outputting a weight signal according to the weight value in a read operation; and
The processing circuit is coupled to the plurality of nonvolatile memory units and is used for receiving the plurality of input signals and calculating the plurality of input signals and a plurality of weight signals generated by the plurality of nonvolatile memory units to generate the calculation result signals;
the processing circuit and the nonvolatile memory units are arranged on two different chips, and are directly coupled with each other through face-to-face welding or a plurality of through silicon holes between the two chips, and the nonvolatile memory units and the processing circuit are manufactured by the same or different processes.
2. A near memory computing system, comprising:
each operation node is used for receiving a plurality of input signals and outputting operation result signals, and each operation node comprises:
a plurality of nonvolatile memory cells, each for storing a weight value in a write operation and outputting a weight signal according to the weight value in a read operation; and
The processing circuit is coupled to the plurality of nonvolatile memory units and is used for receiving the plurality of input signals and calculating the plurality of input signals and a plurality of weight signals generated by the plurality of nonvolatile memory units to generate the calculation result signals;
the near memory operation system is formed on a system-in-chip, and the processing circuit is directly coupled with the nonvolatile memory units through a connection structure on the chip, and the nonvolatile memory units and the processing circuit are manufactured by the same or different processes.
3. The near memory computing system of claim 1 or 2, wherein the plurality of weight signals generated by the plurality of non-volatile memory cells are current signals, and the processing circuit comprises:
a plurality of operation units, each operation unit including:
a current mirror coupled to a corresponding nonvolatile memory cell of the plurality of nonvolatile memory cells and configured to copy a weight signal generated by the corresponding nonvolatile memory cell to generate a weight current; and
A control transistor having a first terminal for receiving the weighted current, a second terminal for outputting a weighted input signal, and a control terminal for receiving a corresponding input signal of the plurality of input signals.
4. The near memory computing system of claim 3, wherein the processing circuit further comprises:
a capacitor having a first terminal coupled to the second terminals of the control transistors of the operation units and a second terminal coupled to the first system voltage terminal.
5. The near memory computing system of claim 3, wherein the current mirror comprises:
a first transistor having a first terminal coupled to a second system voltage terminal, a second terminal coupled to the corresponding nonvolatile memory cell, and a control terminal;
a second transistor having a first terminal coupled to the second system voltage terminal, a second terminal coupled to the first terminal of the control transistor, and a control terminal coupled to the control terminal of the first transistor;
a first switch having a first terminal coupled to the second system voltage terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal for receiving a first control signal; and
The second switch has a first terminal coupled to the control terminal of the first transistor, a second terminal coupled to the second terminal of the first transistor, and a control terminal for receiving a second control signal.
6. The near memory computing system of claim 5, wherein when a first computing node of the plurality of computing nodes is in a standby mode:
the plurality of nonvolatile memory cells in the first operation node are in a read state;
a plurality of first switches of a plurality of operation units in a processing circuit of the first operation node are turned on; and
A plurality of second switches of the plurality of operation units in the processing circuit of the first operation node are turned off.
7. The near memory computing system of claim 6, wherein when the first compute node of the plurality of compute nodes is in a ready mode:
the plurality of non-volatile memory cells in the first operational node are in the read state; the plurality of first switches of the plurality of operation units in the processing circuit of the first operation node are turned off; and
The plurality of second switches of the plurality of operation units in the processing circuit of the first operation node are turned on.
8. The near memory computing system of claim 7, wherein when the first compute node of the plurality of compute nodes is in operational mode:
the plurality of non-volatile memory cells in the first operational node are in the read state; the plurality of first switches of the plurality of operation units in the processing circuit of the first operation node are turned off;
the plurality of second switches of the plurality of operation units in the processing circuit of the first operation node are turned on; and
The control end of each control transistor receives a corresponding input signal of the plurality of input signals in the plurality of operation units of the processing circuit of the first operation node.
9. The near memory computing system of claim 8, wherein:
the plurality of operation nodes belong to a first layer, a second layer or a third layer which are different;
the first operation node belongs to a first layer; and
When the first operation node is in the operation mode, the operation node belonging to the second layer or the third layer is in the standby mode.
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| US16/826,278 | 2020-03-22 |
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