CN111930311A - Storage method and device - Google Patents
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- CN111930311A CN111930311A CN202010790717.6A CN202010790717A CN111930311A CN 111930311 A CN111930311 A CN 111930311A CN 202010790717 A CN202010790717 A CN 202010790717A CN 111930311 A CN111930311 A CN 111930311A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0643—Management of files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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Abstract
The invention discloses a storage method and a storage device. Wherein, the method comprises the following steps: before the cache layer refreshes data to the persistence layer, the sizes of the multiple strips stored at the back end are obtained; determining a refresh priority of each data to be refreshed based on the stripe size of each stripe; and based on the back-brushing priority of each data to be back-brushed, back-brushing each data to be back-brushed to the back-end for storage according to the corresponding back-brushing priority. The invention solves the technical problem that in the prior art, in the process of flushing back data from a cache layer to a persistence layer, because IO processing of once reading is added in the flow of flushing back, the efficiency of flushing back is low when data of non-stripe alignment and non-full stripes are flushed back.
Description
Technical Field
The invention relates to the field of data storage, in particular to a storage method and a storage device.
Background
At present, in order to take performance and cost into consideration, a storage system generally adopts two layers of architectures, namely a cache layer and a data persistence layer. As shown in fig. 1, in order to provide high-performance read/write in a random IO (Input/Output) scenario, a main medium of the cache layer may be an SSD (Solid State Disk), for example, an NVME (Non-volatile Controller Interface) SSD, and data is written into the cache layer and then returned. In order to store large-capacity data and to reduce cost, a large-capacity and inexpensive medium such as a Hard Disk Drive (HDD) or a magnetic resonance (SMR) Disk is mainly used as the data persistent layer.
Based on the above structure, the cache layer flushes data back to the persistent layer according to the data of the write cache, and according to a certain data flushing policy, for example, the cache flushing processing policy of LRU (Least Recently Used) or LFU (Least Frequently Used) omits the data of the management unit corresponding to the flushing, but the above policy does not consider whether the storage persistent layer supported by the back end is an EC pool, if the storage persistent layer is an EC pool, since the data flushing process does not consider the stripe alignment and the stripe integer multiple flushing, based on the calculation requirement of the check data, the data of other columns needs to be read, the check data is calculated together with the data of the refresh and the write-back data, and the data of the flushing and the check data are written back, so that in the flow of the flushing back, the IO process of one more time reading is doubled, which results in the IO flow of the flushing back, resulting in inefficient back-brushing when data for non-swath aligned and non-full swaths are back-brushed.
For example, as shown in FIG. 2, dirty data is represented by filled boxes and blank data is represented by open boxes. Assume that EC pool employs 4+2 stripes, with a stripe depth of 4K, i.e., a stripe consisting of 4K data blocks and 24K test data. When the dirty data range is flushed back by the cache within 8-24K, the back-end EC pool is flushed back to two strips respectively, wherein the test data P and Q are newly generated, so that the data of 0-8K and 24-32K are required to be read out, and a new P, Q in the two strips is generated to be written down, so that the read amplification temperature is caused.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a storage method and a storage device, which are used for at least solving the technical problem that in the prior art, in the process of flushing data back to a persistence layer from a cache layer, because IO processing of reading once is added in a flow of flushing back, the efficiency of flushing back is low when data of non-stripe alignment and non-full stripes are flushed back.
According to an aspect of an embodiment of the present invention, there is provided a storage method including: before the cache layer refreshes data to the persistence layer, the sizes of the multiple strips stored at the back end are obtained; determining a refresh priority of each data to be refreshed based on the stripe size of each stripe; and based on the back-brushing priority of each data to be back-brushed, back-brushing each data to be back-brushed to the back-end for storage according to the corresponding back-brushing priority.
Optionally, the back-brushing priority is in order: stripe alignment and integer multiples of stripe, stripe misalignment partial data.
Optionally, the data comprises: and if the dirty data is not in stripe alignment and/or is not in integral multiple of the stripes, combining the clean data which is not eliminated after the back brushing is completed in the cache layer with the dirty data to form data in stripe alignment and/or in integral multiple of the stripes, and performing back brushing.
Optionally, in the case that the dirty data space of the cache layer is greater than the predetermined threshold, if the dirty data of the stripe alignment and/or the integer multiple of the stripe is not scanned, or the data composed by combining the clean data and the dirty data is not the stripe alignment and/or the integer multiple of the stripe, the dirty data of the non-stripe alignment and/or the integer multiple of the non-stripe is swiped back.
Optionally, the dirty data is converted into clean data after the dirty data is successfully flushed back, wherein the clean data is eliminated when the blank space of the cache layer is lower than a predetermined value.
According to another aspect of the embodiments of the present invention, there is also provided a storage apparatus, including: the obtaining module is used for obtaining the sizes of the plurality of strips stored at the back end before the cache layer flushes the data back to the persistence layer; the determining module is used for determining the back-brushing priority of each piece of data to be back-brushed based on the size of each strip; and the back-brushing module is used for back-brushing each data to be back-brushed to the back-end storage according to the corresponding back-brushing priority based on the back-brushing priority of each data to be back-brushed.
Optionally, the back-brushing priority is in order: stripe alignment and integer multiples of stripe, stripe misalignment partial data.
Optionally, the data comprises: dirty data and clean data, wherein the apparatus further comprises: and the merging module is used for merging the clean data which is not eliminated after the back brushing is finished in the cache layer with the dirty data to form data of the stripe alignment and/or the stripe integral multiple and performing the back brushing treatment if the dirty data is not the stripe alignment and/or the stripe integral multiple.
Optionally, the apparatus further comprises: the first sub-processing module is used for performing back-brushing on the dirty data which is not in the stripe alignment and/or is not an integer multiple of the stripe if the dirty data which is in the stripe alignment and/or is an integer multiple of the stripe is not scanned or the data which is formed by combining the clean data and the dirty data is not in the stripe alignment and/or is not an integer multiple of the stripe under the condition that the dirty data space of the cache layer is larger than a preset threshold value.
Optionally, the apparatus further comprises: and the second sub-processing module is used for converting the dirty data into clean data after the dirty data is successfully brushed back, wherein the clean data is eliminated under the condition that the blank space of the cache layer is lower than a preset value.
According to another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, which includes a stored program, wherein when the program runs, the apparatus on which the computer-readable storage medium is located is controlled to execute the storage method.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes the storage method described above.
In the embodiment of the present invention, before the cache layer flushes the data back to the persistence layer, the flushing back priority of each piece of data to be flushed back may be determined based on the obtained stripe size of each stripe stored at the back end, and each piece of data to be flushed back is flushed back to the back end for storage according to the corresponding flushing back priority based on the flushing back priority of each piece of data to be flushed back. It is easy to notice that, through adding the back-brushing priority strategy, the different data to be back-brushed are back-brushed to the back-end storage according to different back-brushing priorities, thereby achieving the purposes of reducing the reading amplification caused by the back-brushing of the non-full strip, reducing the IO flow of the back-brushing, improving the technical effect of the back-brushing efficiency, and further solving the technical problem of low back-brushing efficiency when the data of the non-full strip and the non-full strip are back-brushed due to the fact that the IO processing of reading for one time is increased in the flow of the back-brushing writing in the process of the cache layer back-brushing the data to the persistence layer in the prior art.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a two-layer architecture of a memory system according to the prior art;
FIG. 2 is a schematic diagram of a data refresh according to the prior art;
FIG. 3 is a flow chart of a storage method according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an alternative data refresh in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of another alternative data refresh in accordance with an embodiment of the present invention; and
FIG. 6 is a schematic diagram of a memory device according to an embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical names or technical terms appearing in the embodiments of the present invention are explained below as follows:
EC: error correction codes are a method of data protection that can segment data, extend, encode, and store redundant blocks of data in different locations, such as disks, storage nodes, or other geographic locations.
Dirty data: it may be that the write cache does not flush back to the data stored in the back-end.
Clean data: may be data that has been copied back to the backend storage.
Blank data: space that has not been written with data or that has originally been written with data is freed.
Example 1
In accordance with an embodiment of the present invention, there is provided a storage method, it being noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer-executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
Fig. 3 is a flow chart of a storage method according to an embodiment of the present invention, as shown in fig. 3, the method includes the following steps:
step S302, before the cache layer flushes the data back to the persistence layer, the stripe sizes of the plurality of stripes stored at the back end are obtained.
The caching layer in the above steps may adopt NVME SSD or SSD, but is not limited thereto. The persistent layer may employ an HDD disk or an SMR disk, but is not limited thereto. The back-end storage may refer to a back-end data persistence layer, which may be an EC pool, and therefore, when the data is flushed back to the persistence layer, the stripe alignment and the stripe integer multiple of the flushing back need to be considered.
Step S304, based on the stripe size of each stripe, determining the brushing-back priority of each data to be brushed-back.
The back-brushing priority in the above steps may be a priority order determined based on a new back-brushing priority policy, and the back-brushing priorities are, in order from high to low: stripe alignment and integer multiples of stripe, stripe misalignment partial data. The data to be brushed back can be data stored in the cache layer, and the data needs to be brushed back to the back-end storage.
And S306, based on the brushing priority of each data to be brushed back, brushing each data to be brushed back to the back end according to the corresponding brushing priority for storage.
In an optional embodiment, the stripe size of the EC stored at the back end is obtained before the cache flushes back, and in a common flushing processing policy, when data of one block or data of one object is flushed back, a new flushing-back priority policy is added. According to a common refresh processing strategy, when a certain data block or object data is refreshed, whether dirty data has data meeting stripe alignment and stripe integral multiple is judged, if the dirty data has the data meeting the stripe alignment and the stripe integral multiple, the data is refreshed preferentially, and the data of the aligned part is not refreshed temporarily.
For example, as shown in FIG. 4, dirty data is represented by filled boxes and blank data is represented by open boxes. Although the data which can be brushed back continuously is 8-32K, only the full stripe data of 16-32K can be brushed back by adopting a brushing back priority strategy, and 8-16K is not brushed back for a while.
In the above embodiment of the present invention, before the cache layer flushes data back to the persistence layer, the flushing priority of each piece of data to be flushed back may be determined based on the obtained stripe size of each stripe stored at the back end, and each piece of data to be flushed back may be flushed back to the back end for storage according to the corresponding flushing priority based on the flushing priority of each piece of data to be flushed back. It is easy to notice that, through adding the back-brushing priority strategy, the different data to be back-brushed are back-brushed to the back-end storage according to different back-brushing priorities, thereby achieving the purposes of reducing the reading amplification caused by the back-brushing of the non-full strip, reducing the IO flow of the back-brushing, improving the technical effect of the back-brushing efficiency, and further solving the technical problem of low back-brushing efficiency when the data of the non-full strip and the non-full strip are back-brushed due to the fact that the IO processing of reading for one time is increased in the flow of the back-brushing writing in the process of the cache layer back-brushing the data to the persistence layer in the prior art.
Optionally, in the foregoing embodiment of the present invention, the data includes: and if the dirty data is not in stripe alignment and/or is not in integral multiple of the stripes, combining the clean data which is not eliminated after the back brushing is completed in the cache layer with the dirty data to form data in stripe alignment and/or in integral multiple of the stripes, and performing back brushing.
In an alternative embodiment, when the constituent stripes are written to it and integer multiples of the stripes, if the dirty data portions do not meet the need for the flush-back priority, then the clean data portions can be added together to make up the stripe-aligned or integer multiples of the stripe data, so that it can be flushed back.
For example, as shown in FIG. 5, dirty data is represented by filled boxes, blank data is represented by open boxes, and clean data is represented by shaded boxes. Dirty data does not satisfy the conditions of stripe alignment and stripe integral multiple, clean data can be added to be made up into data back brushing which satisfies stripe alignment and stripe integral multiple, and therefore the problem of read amplification does not exist in the back end EC pool.
Optionally, in the foregoing embodiment of the present invention, in a case that the dirty data space of the cache layer is greater than the predetermined threshold, if the dirty data of the stripe alignment and/or the integer multiple of the stripe is not scanned, or the data composed by merging the clean data and the dirty data is not the stripe alignment and/or the integer multiple of the stripe, the dirty data of the non-stripe alignment and/or the integer multiple of the non-stripe is swiped back.
The predetermined threshold in the above steps may be used to represent that there are more dirty data cached in the cache layer, and the space for continuously caching the dirty data is small, which may affect the subsequent caching of the dirty data in the cache layer, and the specific value of the predetermined threshold may be set according to actual needs.
In an alternative embodiment, when the dirty data space of the cache layer is greater than the predetermined threshold, that is, the dirty data space is tight, if the dirty data satisfying the stripe alignment and the stripe integer multiple is not found, or the data after adding the clean data still does not satisfy the stripe alignment and the stripe integer multiple, the dirty data not satisfying the stripe alignment and the stripe integer multiple may be directly brushed back.
Optionally, in the foregoing embodiment of the present invention, the dirty data is converted into clean data after being successfully flushed back, where the clean data is eliminated when a blank space of the cache layer is lower than a predetermined value.
The predetermined value in the above step may be a value that is used to represent that the remaining space of the blank space of the cache layer is small, which may affect the subsequent data cache in the cache layer, and the specific value of the predetermined value may be set according to actual needs.
In an alternative embodiment, the dirty data can be converted into clean data after the dirty data is successfully brushed back, and the clean data can be recycled when the blank space is tight, that is, when the blank space is low, part of the clean data is directly eliminated, so that the read condition of the clean data can be improved before recycling, the dirty data of a subsequent non-full strip can be conveniently brushed back to a full strip.
Through the scheme, in order to reduce the read amplification problem introduced when cache back-brushing data reaches EC pool, a back-brushing priority strategy is added into a back-brushing strategy, the back-brushing of data with integral multiple of the stripe is preferentially performed, if dirty data is not aligned with the full stripe width, the dirty data can be integrated into full stripe back-brushing according to the clean data which is not eliminated after cache back-brushing, so that the read amplification caused by the non-full stripe back-brushing is further reduced, the IO flow of the back-brushing is reduced, and the back-brushing efficiency is improved.
Example 2
According to an embodiment of the present invention, a storage device is provided, where the storage device can execute the storage method in the foregoing embodiment, and the specific implementation schemes and the preferred application scenarios in this embodiment are the same as those in the foregoing embodiment, which are not described herein again.
Fig. 6 is a schematic diagram of a memory device according to an embodiment of the present invention, as shown in fig. 6, the device including:
an obtaining module 62, configured to obtain stripe sizes of multiple stripes stored at a back end before the cache layer flushes data back to the persistence layer;
a determining module 64, configured to determine a refresh priority of each data to be refreshed based on the stripe size of each stripe;
and the back-brushing module 66 is configured to back-brush each data to be back-brushed to the back-end storage according to the corresponding back-brushing priority based on the back-brushing priority of each data to be back-brushed.
Optionally, in the foregoing embodiment of the present invention, the data includes: dirty data and clean data, wherein the apparatus further comprises: and the merging module is used for merging the clean data which is not eliminated after the back brushing is finished in the cache layer with the dirty data to form data of the stripe alignment and/or the stripe integral multiple and performing the back brushing treatment if the dirty data is not the stripe alignment and/or the stripe integral multiple.
Optionally, in the above embodiment of the present invention, the apparatus further includes: the first sub-processing module is used for performing back-brushing on the dirty data which is not in the stripe alignment and/or is not an integer multiple of the stripe if the dirty data which is in the stripe alignment and/or is an integer multiple of the stripe is not scanned or the data which is formed by combining the clean data and the dirty data is not in the stripe alignment and/or is not an integer multiple of the stripe under the condition that the dirty data space of the cache layer is larger than a preset threshold value.
Optionally, in the above embodiment of the present invention, the apparatus further includes: and the second sub-processing module is used for converting the dirty data into clean data after the dirty data is successfully brushed back, wherein the clean data is eliminated under the condition that the blank space of the cache layer is lower than a preset value.
Example 3
According to an embodiment of the present invention, a computer-readable storage medium is provided, and the computer-readable storage medium includes a stored program, where the program, when executed, controls an apparatus in which the computer-readable storage medium is located to execute the storage method in the above-mentioned embodiment 1.
Example 4
According to an embodiment of the present invention, there is provided a processor configured to execute a program, where the program executes the storage method in embodiment 1.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (12)
1. A storage method, comprising:
before the cache layer refreshes data to the persistence layer, the sizes of the multiple strips stored at the back end are obtained;
determining a refresh priority of each data to be refreshed based on the stripe size of each stripe;
and based on the brushing priority of each data to be brushed back, brushing back each data to be brushed back to the back end according to the corresponding brushing priority for storage.
2. The method of claim 1, wherein the back-brushing priorities are, in order: stripe alignment and integer multiples of stripe, stripe misalignment partial data.
3. The method of claim 2, wherein the data comprises: and if the dirty data is not the stripe alignment and/or is not the integral multiple of the stripe, combining the clean data which is not eliminated after the back brushing is completed in the cache layer with the dirty data to form the data of the stripe alignment and/or the integral multiple of the stripe, and performing the back brushing processing.
4. The method of claim 3, wherein if the dirty data space of the cache layer is larger than a predetermined threshold, if the stripe alignment and/or integer multiple of the dirty data is not scanned, or the data combined by the clean data and the dirty data is not the stripe alignment and/or integer multiple of the stripe, then the dirty data of non-stripe alignment and/or integer multiple of the non-stripe is swiped back.
5. The method according to claim 3 or 4, wherein the dirty data is converted into clean data after the dirty data is successfully brushed, and wherein the clean data is subjected to a de-selection operation when the blank space of the cache layer is lower than a predetermined value.
6. A memory device, comprising:
the obtaining module is used for obtaining the sizes of the plurality of strips stored at the back end before the cache layer flushes the data back to the persistence layer;
the determining module is used for determining the back-brushing priority of each piece of data to be back-brushed based on the size of each strip;
and the back-brushing module is used for back-brushing each data to be back-brushed to the rear end for storage according to the corresponding back-brushing priority based on the back-brushing priority of each data to be back-brushed.
7. The apparatus of claim 6, wherein the back-brushing priorities are, in order: stripe alignment and integer multiples of stripe, stripe misalignment partial data.
8. The apparatus of claim 7, wherein the data comprises: dirty data and clean data, wherein the apparatus further comprises:
and the merging module is used for merging the clean data which is not eliminated after the back brushing is finished in the cache layer with the dirty data to form the data of the stripe alignment and/or the stripe integral multiple and performing the back brushing treatment if the dirty data is not the stripe alignment and/or the stripe integral multiple.
9. The apparatus of claim 8, further comprising: the first sub-processing module is used for performing back-brushing on the dirty data which is not in the stripe alignment and/or is not in the stripe integer multiple if the dirty data which is in the stripe alignment and/or is in the stripe integer multiple is not scanned or the data which is formed by combining the clean data and the dirty data is not in the stripe alignment and/or is not in the stripe integer multiple under the condition that the dirty data space of the cache layer is larger than a preset threshold value.
10. The apparatus of claim 8 or 9, further comprising: and the second sub-processing module is used for converting the dirty data into clean data after the dirty data is successfully brushed back, wherein the clean data is eliminated under the condition that the blank space of the cache layer is lower than a preset value.
11. A computer-readable storage medium, comprising a stored program, wherein the program, when executed, controls an apparatus in which the computer-readable storage medium is located to perform the storage method of any one of claims 1 to 5.
12. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the storage method according to any one of claims 1 to 5 when running.
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