CN111916459B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN111916459B
CN111916459B CN201911190047.8A CN201911190047A CN111916459B CN 111916459 B CN111916459 B CN 111916459B CN 201911190047 A CN201911190047 A CN 201911190047A CN 111916459 B CN111916459 B CN 111916459B
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layer
source layer
substrate
chip
source
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CN111916459A (en
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金镇河
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SK Hynix Inc
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SK Hynix Inc
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance

Abstract

A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device includes: forming a unit chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer connected to the source layer through the stacked structure; turning over the unit chip; exposing a rear surface of the source layer by removing the first substrate from the unit chip; performing surface treatment on the rear surface of the source layer to reduce the resistance of the source layer; forming a peripheral circuit chip, wherein the peripheral circuit chip comprises a second substrate and a circuit positioned on the second substrate; and bonding the cell chip including the source layer having the reduced resistance to the peripheral circuit chip.

Description

Method for manufacturing semiconductor device
Technical Field
Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a method of manufacturing a semiconductor device.
Background
The non-volatile memory device maintains the stored data regardless of the power on/off condition. Recently, an increase in integration density of a two-dimensional nonvolatile memory device in which memory cells are formed on a substrate in a single layer has been limited. Accordingly, three-dimensional nonvolatile memory devices in which memory cells are stacked in a vertical direction on a substrate have been proposed.
The three-dimensional nonvolatile memory device may include interlayer insulating layers and gates alternately stacked with each other and a channel layer passing through the interlayer insulating layers and the gates, and the memory cells are stacked along the channel layer. Various structures and fabrication methods have been developed to improve the operational reliability of three-dimensional nonvolatile memory devices.
Disclosure of Invention
According to one embodiment, a method of manufacturing a semiconductor device may include: forming a unit chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer connected to the source layer through the stacked structure; turning over the unit chip; exposing a rear surface of the source layer by removing the first substrate from the unit chip; performing surface treatment on the rear surface of the source layer to reduce the resistance of the source layer; forming a peripheral circuit chip, wherein the peripheral circuit chip comprises a second substrate and a circuit positioned on the second substrate; and bonding the cell chip including the source layer having the reduced resistance to the peripheral circuit chip.
According to one embodiment, a method of manufacturing a semiconductor device may include: forming a unit chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer connected to the source layer through the stacked structure; turning over the unit chip; exposing a rear surface of the source layer by removing the first substrate from the unit chip; irradiating the source layer with a laser beam incident on a rear surface of the source layer; patterning the source layer irradiated with the laser beam; forming a peripheral circuit chip, wherein the peripheral circuit chip comprises a second substrate and a circuit positioned on the second substrate; and bonding the unit chip including the patterned source layer to the peripheral circuit chip.
According to one embodiment, a method of manufacturing a semiconductor device may include: forming a unit chip including a first substrate, a patterned source layer on the first substrate, a stacked structure on the patterned source layer, and a channel layer connected to the patterned source layer through the stacked structure; turning over the unit chip; exposing the patterned source layer by removing the first substrate from the unit chip; irradiating the patterned source layer with a laser beam incident on a rear surface of the patterned source layer; forming a peripheral circuit chip, wherein the peripheral circuit chip comprises a second substrate and a circuit positioned on the second substrate; and bonding a unit chip including the patterned source layer irradiated with the laser beam to the peripheral circuit chip.
Drawings
Fig. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment;
fig. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment;
fig. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment;
fig. 4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment;
fig. 5 and 6 are block diagrams illustrating a configuration of a memory system according to one embodiment of the present disclosure; and
fig. 7 and 8 are block diagrams illustrating a configuration of a computing system according to one embodiment of the present disclosure.
Detailed Description
Hereinafter, various embodiments will be described with reference to the accompanying drawings. Embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of examples of the embodiments to those skilled in the art.
It should also be noted that in this specification, "connected/coupled" means that one component is not only directly coupled to another component, but also indirectly coupled to another component through intervening components. In the description, when an element is referred to as being "comprising" or "comprises" a component, it does not exclude other components, and may further comprise other components, unless the context specifically indicates the contrary.
Various embodiments of the present disclosure may provide a method of manufacturing a semiconductor device having an easy manufacturing process, a stable structure, and improved characteristics.
Fig. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment.
Referring to fig. 1, a semiconductor device according to an embodiment may include a unit CHIP c_chip and a peripheral circuit CHIP p_chip bonded to the unit CHIP c_chip. The cell CHIP c_chip may be located above the peripheral circuit CHIP p_chip. On the other hand, the peripheral circuit CHIP p_chip may be located above the cell CHIP c_chip.
The cell CHIP c_chip may include a first stacked structure ST1, a second stacked structure ST2, interconnection structures (131 to 134 and 141 to 143), a first bonding structure 150, a channel structure 160, a source contact structure 170, and a first interlayer insulating layer 180.
The first stacked structure ST1 may include first conductive layers 110 and first insulating layers 120 alternately stacked with each other. The second stacked structure ST2 may include the second conductive layers 111 and the second insulating layers 121 alternately stacked with each other. The first conductive layer 110 and the second conductive layer 111 may be gates such as a selection transistor and a memory cell, and may include polysilicon, tungsten, metal, and the like. The first insulating layer 120 and the second insulating layer 121 may insulate the stacked gates from each other, and include an insulating material such as oxide or nitride.
A portion of the first stacked structure ST1 may include a first sacrificial layer 113 instead of the first conductive layer 110. In a portion of the first stacked structure ST1, the first sacrificial layers 113 and the first insulating layers 120 may be alternately stacked with each other. Similarly, in a portion of the second stacked structure ST2, the second sacrificial layers 114 and the second insulating layers 121 may be alternately stacked with each other. The first sacrificial layer 113 and the second sacrificial layer 114 may include a dielectric material such as nitride.
The first stacked structure ST1 may include a cell region where the memory string is located and a contact region where the interconnect structure is connected. The second stacked structure ST2 may include a cell region and a contact region. The contact region of each of the first and second stacked structures ST1 and ST2 may have a stepped structure.
The first and second laminated structures ST1 and ST2 may be vertically laminated to each other. For example, the first stacked structure ST1 may be located above the second stacked structure ST2. In addition, the cell region of the first stacked structure ST1 and the cell region of the second stacked structure ST2 may overlap each other in the stacking direction, and the contact region of the first stacked structure ST1 and the contact region of the second stacked structure ST2 may overlap each other in the stacking direction.
The source layer 100 may be positioned on the first stacked structure ST 1. The source layer 100 may be a polysilicon layer. The source layers 100 may be patterned and the insulating layer 182 may fill the space between adjacent source layers 100. The insulating layer 182 may be located at a position corresponding to the contact region of the first and second stacked structures ST1 and ST2.
The source layer 100 may have a reduced resistance due to the surface treatment. For example, the source layer 100 may be a polysilicon layer having an increased grain size. The surface treatment may be laser irradiation, dopant implantation or heat treatment.
The dopant may be an N-type impurity or a P-type impurity. The source layer 100 may include an N-type impurity or a P-type impurity according to an erase operation method. When the semiconductor device performs an erase operation by supplying holes using the source layer 100, the source layer 100 may include P-type impurities. When the semiconductor device performs an erase operation by supplying holes using a Gate Induced Drain (GIDL) current, the source layer 100 may include N-type impurities.
The channel structure 160 may penetrate the first and second stacked structures ST1 and ST2. The channel structure 160 may be coupled to the source layer 100 and protrude into the source layer 100. The channel structure 160 may include a channel layer and a memory layer surrounding sidewalls of the channel layer. In addition, the channel layer may include a semiconductor material such as silicon (Si), germanium (Ge), or the like. The memory layer may include at least one of a tunnel insulating layer, a data storage layer, and a charge blocking layer. The data storage layer may include a floating gate, a charge trapping material, silicon, nitride, nanodots, a variable resistance material, and a phase change material. In addition, the channel structure 160 may further include a gap-filling insulating layer formed in the channel layer and an epitaxial semiconductor layer coupling the channel layer and the source layer 100.
The source contact structure 170 may penetrate the first and second stacked structures ST1 and ST2 and be coupled to the source layer 100. The source contact structure 170 may protrude into the source layer 100 at a greater depth than the channel structure 160. In addition, the source contact structure 170 may have a larger diameter than the channel structure 160.
The source contact structure 170 may penetrate the first conductive layer 110, the first insulating layer 120, the second conductive layer 111, and the second insulating layer 121, or may penetrate the first sacrificial layer 113, the first insulating layer 120, the second sacrificial layer 114, and the second insulating layer 121. When the first sacrificial layer 113 is replaced with the first conductive layer 110, some portions of the first sacrificial layer 113 may remain. When the second sacrificial layer 114 is replaced with the second conductive layer 111, some portions of the second sacrificial layer 114 may remain.
The source contact structure 170 may include a contact plug including a conductive material such as polysilicon, tungsten, or metal. In addition, the source contact structure 170 may further include an insulating spacer surrounding a sidewall of the contact plug, and the insulating spacer may include an insulating material such as oxide or nitride.
The interconnection structures (131 to 134 and 141 to 143) may include the first, second, third, and fourth contact plugs 131, 132, 133, and 134, and the first, second, and third wirings 141, 142, and 143. The interconnection structures (131 to 134 and 141 to 143) may be formed in the first interlayer insulating layer 180. In fig. 1, the first interlayer insulating layer 180 may be illustrated as a single layer. However, the first interlayer insulating layer 180 may include insulating layers stacked one on another.
The first contact plugs 131 may be coupled to the first conductive layer 110 or the second conductive layer 111 stacked one on another, respectively. The second contact plug 132 may be coupled to the first contact plug 131, the channel structure 160, or the source contact structure 170. The second contact plug 132 may electrically couple the first contact plug 131 and the first wiring 141. The third contact plug 133 may be coupled to the first wiring 141 and electrically couple the first wiring 141 and the second wiring 142. The fourth contact plug 134 may be coupled to the second wiring 142 and electrically couple the second wiring 142 and the third wiring 143.
The first bonding structure 150 may electrically couple the cell CHIP c_chip to the peripheral circuit CHIP p_chip. The first bonding structure 150 may be in the form of a contact plug or a wire. The first bonding structure 150 may be electrically coupled to the third wiring 143.
The peripheral circuit CHIP p_chip may include a circuit for operating a memory string included in the cell CHIP c_chip. The peripheral circuit CHIP p_chip may include a transistor TR, a circuit, a capacitor, a resistor, and the like. The peripheral circuit CHIP p_chip may include the substrate 200, the transistor TR, the interconnection structures (231 to 234 and 241 to 243), the second bonding structure 250, and the second interlayer insulating layer 280.
The transistor TR may include a gate 220 and a gate insulating layer 210. The gate insulating layer 210 may be interposed between the substrate 200 and the gate electrode 220. Although not shown in fig. 1, the transistor TR may further include a junction in the substrate 200.
The interconnection structures (231 to 234 and 241 to 243) may include fifth, sixth, seventh and eighth contact plugs 231, 232, 233 and 234, and fourth, fifth and sixth wirings 241, 242 and 243. The interconnection structures (231 to 234 and 241 to 243) may be formed in the second interlayer insulating layer 280. In fig. 1, the second interlayer insulating layer 280 may be illustrated as a single layer. However, the second interlayer insulating layer 280 may include insulating layers stacked one on another.
The fifth contact plug 231 may be coupled to the gate 220 or a junction of the transistor TR. The fourth wiring 241 may be electrically coupled to the fifth contact plug 231. The sixth contact plug 232 may electrically couple the fourth wiring 241 and the fifth wiring 242. The seventh contact plug 233 may electrically couple the fifth wiring 242 and the sixth wiring 243. The eighth contact plug 234 may electrically couple the sixth wiring 243 and the seventh wiring 244.
The second bonding structure 250 may electrically couple the cell CHIP c_chip to the peripheral circuit CHIP p_chip. The second bonding structure 250 may be in the form of a contact plug or a wire. The second bonding structure 250 may be electrically coupled to the seventh wire 244. The second bonding structure 250 may be bonded to the first bonding structure 150 of the unit CHIP c_chip. Accordingly, the cell CHIP c_chip and the peripheral circuit CHIP p_chip may be electrically coupled to each other through the first bonding structure 150 and the second bonding structure 250. For example, the cell CHIP c_chip and the peripheral circuit CHIP p_chip may be coupled to each other by bonding the first bonding structure 150 and the second bonding structure 250 to each other and bonding the first interlayer insulating layer 180 and the second interlayer insulating layer 280 to each other. Thus, the first and second stacked structures ST1 and ST2 may be located between the substrate 200 and the source layer 100.
According to the above structure, the unit CHIP c_chip and the peripheral circuit CHIP p_chip may be separately manufactured and then bonded to each other. In addition, since the source layer 100 has an increased grain size, the resistance of the source layer 100 may be reduced. Therefore, source bounce (source bounce) during the operation of the semiconductor device can be reduced.
Fig. 2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment.
Referring to fig. 2A, a cell CHIP c_chip may be formed. The cell CHIP c_chip includes a first substrate 10, a source layer 12, a stacked structure ST, and a channel layer 25. The cell CHIP c_chip may further include insulating layers 11 and 27, a spacer 28, an interlayer insulating layer 13, an interconnection structure 14, and a first bonding structure 15.
A method of forming the cell CHIP c_chip will be described below.
First, after forming the insulating layer 11 on the first substrate 10, the source layer 12 may be formed on the insulating layer 11. The insulating layer 11 may include an oxide layer or a nitride layer. The source layer 12 may be a polysilicon layer.
A stacked structure ST may be formed on the source layer 12. The laminated structure ST may include the first material layers 23 and the second material layers 22 alternately laminated with each other. The first material layer 23 may be provided to form gates of memory cells, select transistors, and the like. A second material layer 22 may be provided to insulate the stacked gates from each other. The first material layer 23 may include a material having a high etching selectivity with respect to the second material layer 22. For example, the first material layer 23 may be a sacrificial layer including nitride or the like, and the second material layer 22 may be an insulating layer including oxide or the like. Alternatively, the first material layer 23 may be a conductive layer including polysilicon, tungsten, or the like, and the second material layer 22 may be an insulating layer including oxide or the like. In another example, each of the first material layers 23 may be a conductive layer including doped polysilicon, and each of the second material layers 22 may be a sacrificial layer including undoped polysilicon.
After forming the opening through the laminated structure ST, a channel structure may be formed in the opening. Each of the channel structures may include a channel layer 25, a memory layer 24 surrounding the channel layer 25, and a gap-filling insulating layer 26 in the channel layer 25. Fig. 2A schematically shows how the channel layer 25 and the source layer 12 are coupled to each other. However, the channel layer 25 may protrude into the source layer 12, or may be coupled to the source layer 12 through an epitaxial semiconductor layer.
After forming the opening through the stacked structure ST, the source contact structure 29 may be formed in the opening. Each of the source contact structures 29 may include a contact plug, and may further include an insulating spacer surrounding a sidewall of the contact plug. The source contact structure 29 may protrude into the source layer 12.
After the insulating layer 27 is formed on the laminated structure ST, a slit may be formed through the insulating layer 27 and the laminated structure ST. The first material layer 23 or the second material layer 22 may be replaced by the third material layer 21. For example, when the first material layer 23 is a sacrificial layer and the second material layer 22 is an insulating layer, the first material layer 23 may be replaced with a conductive layer. In another example, when the first material layer 23 is a conductive layer and the second material layer 22 is an insulating layer, the first material layer 23 may be silicided. In another example, when the first material layer 23 is a conductive layer and the second material layer 22 is a sacrificial layer, the second material layer 22 may be replaced with an insulating layer. Fig. 2A shows that the first material layer 23 is replaced by a conductive layer. The first material layer 23 may remain in a portion of the laminated structure ST.
After the spacers 28 are formed on the inner walls of the slits, the interlayer insulating layer 13 may be formed in the slits. The interlayer insulating layer 13 may fill the slit and be formed on the laminated structure ST. However, instead of filling the interlayer insulating layer 13 in the slit, a conductive plug may be formed in the slit. In addition, the interlayer insulating layer 13 may include a plurality of insulating layers and include an interconnection structure 14. Interconnect structure 14 may be electrically coupled to channel layer 25 and source contact structure 29.
Another interconnect structure may be further formed, and a first bonding structure 15 electrically coupled to the interconnect structure may be formed.
In the previously described embodiment, the stacked structure ST may be formed on the source layer 12. However, the stacked structure ST may be formed on the source sacrificial layer. The source sacrificial layer may be replaced by the source layer 12 through a slit. In addition, in the previously described embodiment, the channel structure, the source contact structure 29, and the third material layer 21 are described as being formed in a sequential manner. However, they may be formed in a different order.
Referring to fig. 2B, the first substrate 10 may be positioned above the stacked structure ST by flipping the unit CHIP c_chip. In other words, the rear surface of the first substrate 10 may be exposed.
The rear surface RF of the source layer 12 may be exposed by removing the first substrate 10. For example, after exposing the insulating layer 11 by removing the first substrate 10, the source layer 12 may be exposed by removing the insulating layer 11. The first substrate 10 may be removed by a polishing method. The insulating layer 11 may be removed by a wet etching process.
The rear surface RF of the source layer 12 may be surface treated. The rear surface RF of the source layer 12 may be surface-treated by laser irradiation, dopant implantation, or heat treatment after dopant implantation. Thereby, the source layer 12A having reduced resistance can be formed. When the source layer 12 includes a polysilicon layer, the grain size of the polysilicon layer may be increased due to the surface treatment process. In other words, the surface-treated source layer 12A may have a larger grain size than the source layer 12 formed by the deposition process. In addition, the grain size may be increased to the level of single crystals depending on the conditions of the laser irradiation process.
Referring to fig. 2C, a peripheral circuit CHIP p_chip may be formed. The peripheral circuit CHIP p_chip may include the second substrate 30 and peripheral circuits. First, a peripheral circuit may be formed on the second substrate 30. For example, the transistor TR may include a gate electrode 32 and a gate insulating layer 31. An interlayer insulating layer 33 and an interconnection structure 34 may be formed. Interconnect structure 34 may be electrically coupled to gate 32 of transistor TR.
Another interconnect structure may be further formed. A second bond structure 35 electrically coupled to the interconnect structure may be formed.
Referring to fig. 2D, the cell CHIP c_chip and the peripheral circuit CHIP p_chip may be bonded to each other. The cell CHIP c_chip and the peripheral circuit CHIP p_chip may be bonded such that the stacked structure ST may be located between the source layer 12A and the second substrate 30. For example, the unit CHIP c_chip and the peripheral circuit CHIP p_chip may be bonded such that the first bonding structure 15 of the unit CHIP c_chip and the second bonding structure 35 of the peripheral circuit CHIP p_chip may contact each other. Thereby, the unit CHIP c_chip and the peripheral circuit CHIP p_chip can be electrically coupled to each other.
According to the above-described manufacturing method, since the first substrate 10 is removed after the flip-CHIP c_chip, the rear surface RF of the source layer 12 can be easily exposed. Since the surface treatment is performed on the rear surface RF of the source layer 12, the process can be more simplified than in the case where the surface treatment is performed on the entire surface of the source layer 12 on which the stacked structure ST is formed. In addition, since the rear surface RF of the source layer 12 is subjected to surface treatment, the source layer 12A having reduced resistance can be formed.
Fig. 3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment.
Referring to fig. 3A, a cell CHIP c_chip may be formed. The cell CHIP c_chip may include a first substrate 40, an insulating layer 41, a source layer 42, a stacked structure ST, a channel structure 45, an interlayer insulating layer 46, and an interconnection structure 47. In addition, the laminated structure ST may include conductive layers 43 and insulating layers 44 alternately laminated with each other.
Since the method of forming the unit CHIP c_chip is similar to or the same as the method described above with reference to fig. 2A, any repetitive description thereof will be omitted.
Referring to fig. 3B, after the unit CHIP c_chip is flipped, the first substrate 40 and the insulating layer 41 may be removed. Thereby, the rear surface RF of the source layer 42 can be exposed. By performing surface treatment on the source layer 42, the resistance of the source layer 42 can be reduced.
For example, a laser may be incident on the source layer 42 to irradiate the source layer. The polysilicon layer may be melted by laser irradiation and then may be cooled. In some embodiments, the polysilicon layer may be instantaneously melted by laser irradiation and then may be cooled. Thereby, the polysilicon layer may be recrystallized and its grain size may be increased. Accordingly, the source layer 42A having an increased grain size can be formed.
In another example, dopants may be implanted into the back surface RF of the source layer 42. For example, after the dopant is implanted into the source layer 42 using an ion implantation process, a heat treatment process may be performed thereon. The source layer 42 may have conductivity by a dopant, and the dopant may be activated by a heat treatment process.
The process conditions including time and temperature of the surface treatment process may be controlled according to the thickness or material of the source layer 42.
Referring to fig. 3C, the surface-treated source layer 42A may be patterned. The plurality of source layers 42B may be formed by etching the source layer 42A. An insulating layer 48 may be formed between adjacent source layers 42B.
Although not shown in fig. 3C, the cell CHIP c_chip including the patterned source layer 42B and the peripheral circuit CHIP may be bonded to each other.
According to the above process, the patterning process may be performed by reducing the resistance of the source layer 42. Accordingly, the entire rear surface RF of the source layer 42 may be surface-treated. In addition, a separate mask may not be used to limit the surface treatment area.
Fig. 4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to one embodiment.
Referring to fig. 4A, a cell CHIP c_chip may be formed. The cell CHIP c_chip may include a first substrate 50, an insulating layer 51, a patterned source layer 52, a stacked structure ST, a channel structure 55, an interlayer insulating layer 56, and an interconnection structure 57. In addition, the laminated structure ST may include conductive layers 53 and insulating layers 54 alternately laminated with each other.
When the cell CHIP c_chip is formed, the source layer 52 may be patterned. For example, after the insulating layer 51 is formed on the first substrate 50, the source layer 52 may be formed on the insulating layer 51. After a plurality of source layers 52 may be formed by patterning the source layers 52, an insulating layer 58 may be formed between adjacent source layers 52. A stacked structure ST may be formed on the patterned source layer 52.
For example, after the insulating layer 51 is formed on the first substrate 50, a source sacrificial layer may be formed on the insulating layer 51. After patterning the source sacrificial layers, an insulating layer 58 may be formed between adjacent source sacrificial layers. After the stacked structure ST and the channel structure 55 are formed on the patterned source sacrificial layer, the source sacrificial layer may be replaced with the source layer 52.
Since the method of forming the unit CHIP c_chip is similar to or the same as the method described above with reference to fig. 2A, any repetitive description thereof will be omitted.
Referring to fig. 4B, the cell CHIP c_chip including the patterned source layer 52 may be inverted. After the insulating layer 51 is exposed by removing the first substrate 50, the rear surface RF of the patterned source layer 52 may be exposed by removing the insulating layer 51.
By performing surface treatment on the rear surface RF of the patterned source layer 52, the resistance of the patterned source layer 52 can be reduced.
For example, a laser beam may be irradiated on the rear surface RF of the patterned source layer 52. By instantaneously melting the polysilicon layer and cooling it, the grain size can be increased. Thereby, the source layer 52A having an increased grain size can be formed.
In another example, dopants may be implanted into the back surface RF of the patterned source layer 52. For example, after the dopants are implanted into the patterned source layer 52 using an ion implantation process, a heat treatment process may be performed thereon. The patterned source layer 52 may be conductive by a dopant, and the dopant may be activated by a heat treatment process. Dopants may be implanted into insulating layer 58 as well as patterned source layer 52. However, the dopant implanted into insulating layer 58 does not affect the characteristics of the semiconductor device. Thus, a separate mask for dopant implantation need not be added.
Although not shown in fig. 4B, the cell CHIP c_chip including the surface-treated source layer 52B and the peripheral circuit CHIP may be bonded to each other.
According to the above process, when the cell CHIP c_chip is formed, the source layer 52 may be patterned. Accordingly, the patterned source layer 52 may be exposed by removing the first substrate 50, and the surface treatment may be performed on the rear surface RF of the source layer 52 without a separate mask.
FIG. 5 is a block diagram illustrating a memory system 1000 according to one embodiment.
As shown in fig. 5, a memory system 1000 according to an embodiment may include a memory device 1200 and a controller 1100.
Memory device 1200 may be used to store various types of data such as text, graphics, and software code. The memory device 1200 may be a non-volatile memory device. In addition, the memory device 1200 may include the above configuration described with reference to fig. 1 to 4B, and may be manufactured by the method described with reference to fig. 1 to 4B. Since the memory device 1200 is configured and manufactured in the same manner as described above, a detailed description thereof will be omitted.
The controller 1100 may be coupled to a host and the memory device 1200 and configured to access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control read operations, write operations, erase operations, and background operations of the memory device 1200.
The controller 1100 may include a Random Access Memory (RAM) 1110, a Central Processing Unit (CPU) 1120, a host interface 1130, error Correction Code (ECC) circuits 1140, and a memory interface 1150.
RAM 1110 may serve as an operation memory for CPU 1120, a cache memory between memory device 1200 and a host, a buffer memory between memory device 1200 and a host, and the like. For reference, the RAM 1110 may be replaced with a Static Random Access Memory (SRAM), a Read Only Memory (ROM), or the like.
The CPU 1120 may control the overall operation of the controller 1100. For example, CPU 1120 may operate firmware such as a Flash Translation Layer (FTL) stored in RAM 1110.
Host interface 1130 may be connected to a host interface. For example, the controller 1100 may communicate with a host through at least one of various interface protocols such as: universal Serial Bus (USB) protocols, multimedia card (MMC) protocols, peripheral Component Interconnect (PCI) protocols, PCI-express (PCI-E) protocols, advanced Technology Attachment (ATA) protocols, serial ATA protocols, parallel ATA protocols, small computer interface (SCSI) protocols, enhanced Small Disk Interface (ESDI) protocols, and Integrated Drive Electronics (IDE) protocols, proprietary protocols, etc.
The ECC circuit 1140 may detect and correct errors in data read from the memory device 1200 using Error Correction Codes (ECC).
The memory interface 1150 may interface with the memory device 1200. For example, the memory interface 1150 may include a NAND interface or a NOR interface.
For reference, the controller 1100 may further include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data to be transferred from the host interface 1130 to an external device or data to be transferred from the memory interface 1150 to the memory device 1200. The controller 1100 may further include a ROM storing code data for interfacing with a host.
Since the memory system 1000 according to an embodiment may include the memory device 1200 having improved integration density and characteristics, the memory system 1000 may also have improved integration density and characteristics accordingly.
Fig. 6 is a block diagram illustrating a configuration of a memory system 1000' according to one embodiment of the present disclosure. Hereinafter, any repetitive detailed description of the components already mentioned above will be omitted.
Referring to fig. 6, a memory system 1000 'according to an embodiment may include a memory device 1200' and a controller 1100. The controller 1100 may include RAM 1110, CPU 1120, host interface 1130, ECC circuit 1140, and memory interface 1150.
The memory device 1200' may be a non-volatile memory device. In addition, the memory device 1200' may include the above configuration described with reference to fig. 1 to 4B, and may be manufactured by the method described with reference to fig. 1 to 4B. Since the memory device 1200' is configured and manufactured in the same manner as described above, a detailed description thereof will be omitted.
Further, the memory device 1200' may be a multi-chip package including a plurality of memory chips. The plurality of memory chips may be divided into a plurality of groups, which may communicate with the controller 1100 through the first through kth channels CH1 through CHk, respectively. In addition, the memory chips included in a single group may be adapted to communicate with the controller 1100 through a common channel. For reference, the memory system 1000' may be modified such that each memory chip is coupled to a respective single channel.
Since the memory system 1000' according to the embodiment may include the memory device 1200' having improved integration and characteristics, the integration and characteristics of the memory system 1000' may also be improved. In addition, since the memory device 1200 'is formed as a multi-chip package, the data storage capacity and the driving speed of the memory system 1000' can be further increased.
Fig. 7 is a block diagram illustrating a configuration of a computing system 2000 in accordance with an embodiment of the present disclosure. Hereinafter, any repetitive detailed description of the components already mentioned above will be omitted.
As shown in fig. 7, computing system 2000 may include a memory device 2100, a CPU 2200, a Random Access Memory (RAM) 2300, a user interface 2400, a power supply 2500, and a system bus 2600.
The memory device 2100 may store data provided via the user interface 2400, data processed by the CPU 2200, and the like. The memory device 2100 may be electrically coupled to the CPU 2200, RAM 2300, user interface 2400, and power supply 2500 through the system bus 2600. For example, the memory device 2100 may be coupled to the system bus 2600 via a controller (not shown) or directly to the system bus 2600. When the memory device 2100 is directly coupled to the system bus 2600. The functions of the controller may be performed by the CPU 2200 and the RAM 2300.
The memory device 2100 may be a non-volatile memory. In addition, the memory device 2100 may include the above configuration described with reference to fig. 1 to 4B, and may be manufactured by the method described with reference to fig. 1 to 4B. Since the memory device 2100 is configured and manufactured in the same manner as described above, a detailed description thereof will be omitted.
As described above with reference to fig. 6, the memory device 2100 may be a multi-chip package configured with a plurality of memory chips.
The computing system 2000 having the above-described configuration may be provided as one of various elements such as a computer, a Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a network tablet, a wireless telephone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a game console, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting/receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, and the like.
As described above, since the computing system 2000 according to an embodiment may include the memory device 2100 with improved integration and characteristics, characteristics of the computing system 2000 may also be improved.
FIG. 8 is a block diagram illustrating a computing system 3000 according to one embodiment.
As shown in fig. 8, a computing system 3000 according to an embodiment may include software layers with an operating system 3200, applications 3100, a file system 3300, and a conversion layer 3400. Computing system 3000 may include a layer of hardware, such as memory device 3500.
The operating system 3200 may manage the software and hardware resources of the computing system 3000. The operating system 3200 may control the execution of programs by the central processing unit. Application 3100 may include various application programs executed by computing system 3000. The application 3100 may be a utility program executed by the operating system 3200.
File system 3300 may refer to a logical structure configured to manage data and files present in computing system 3000. File system 3300 may organize and store files or data in memory device 3500 according to given rules. The file system 3300 may be determined from the operating system 3200 used in the computing system 3000. For example, when operating system 3200 is a Microsoft Windows-based system, file system 3300 may be a File Allocation Table (FAT) or a NT file system (NTFS). Further, the operating system 3200 is a Unix/Linux system, and the file system 3300 may be an extended file system (EXT), a Unix File System (UFS), a Journal File System (JFS), or the like.
Fig. 8 shows operating system 3200, applications 3100, and file system 3300 in separate blocks. However, applications 3100 and file system 3300 may be included in operating system 3200.
In response to a request from file system 3300, translation layer 3400 may translate the address into an appropriate form for memory device 3500. For example, the translation layer 3400 may translate logical addresses generated by the file system 3300 to physical addresses of the memory devices 3500. Mapping information of logical addresses and physical addresses may be stored in an address translation table. For example, the conversion layer 3400 may be a flash conversion layer (FTL), a universal flash link layer (ULL), or the like.
Memory device 3500 may be a non-volatile memory. In addition, the memory device 3500 may include the above configuration described with reference to fig. 1 to 4B, and may be manufactured by the method described with reference to fig. 1 to 4B. Since the memory device 3500 is configured and manufactured in the same manner as described above, a detailed description thereof will be omitted.
The computing system 3000 having the above-described configuration may be divided into an operating system layer operating in an upper layer region and a controller layer operating in a lower layer region. Application 3100, operating system 3200, and file system 3300 may be included in the operating system layer, and may be driven by the operating memory of computing system 3000. The conversion layer 3400 may be included in an operating system layer or a controller layer.
As described above, since the computing system 3000 according to the embodiment may include the memory device 3500 having improved integration density and characteristics, characteristics of the computing system 3000 may also be improved.
According to various embodiments, a semiconductor device having a stable structure and improved reliability may be provided. In addition, the semiconductor device can be manufactured at low cost with a simple process.
Examples of embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some cases, it will be apparent to one of ordinary skill in the art from the filing date of this patent document that features, characteristics, and/or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically indicated otherwise. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.
Cross Reference to Related Applications
The present application claims priority from korean patent application No.10-2019-0053217 filed in the korean intellectual property office on 5/7 of 2019, the entire disclosure of which is incorporated herein by reference.

Claims (17)

1. A method of manufacturing a semiconductor device, the method comprising the steps of:
forming a unit chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer;
turning over the unit chip;
exposing a rear surface of the source layer by removing the first substrate from the unit chip;
performing a surface treatment on the rear surface of the source layer to reduce the resistance of the source layer;
forming a peripheral circuit chip comprising a second substrate and a circuit on the second substrate; and
the unit chip including the source layer having the reduced resistance is bonded to the peripheral circuit chip.
2. The method of claim 1, wherein the source layer comprises a polysilicon layer and a grain size of the polysilicon layer increases as a result of the surface treatment.
3. The method according to claim 1, wherein the surface treatment is performed on the source layer by irradiating the source layer with a laser beam incident on the source layer.
4. The method of claim 1, wherein performing the surface treatment on the source layer comprises:
implanting dopants into the source layer; and
performing a heat treatment on the source layer into which the dopant is implanted.
5. The method of claim 4, wherein the dopant comprises an N-type impurity or a P-type impurity.
6. The method of claim 1, wherein the unit chip and the peripheral circuit chip are bonded such that the stacked structure is located between the source layer and the second substrate.
7. The method of claim 1, wherein the unit chip further comprises an insulating layer interposed between the first substrate and the source layer.
8. The method of claim 7, wherein exposing the rear surface of the source layer comprises:
exposing the insulating layer by removing the first substrate; and
the source layer is exposed by removing the insulating layer.
9. The method of claim 8, wherein the insulating layer is removed by a wet etching process.
10. The method of claim 1, further comprising the step of: after the surface treatment is performed on the rear surface of the source layer, the source layer is patterned.
11. The method of claim 1, wherein forming the unit chip comprises:
forming the source electrode layer on the first substrate;
patterning the source layer; and
the stacked structure is formed on the patterned source layer.
12. The method of claim 1, wherein the unit chip is formed such that the stacked structure is located on a patterned source layer.
13. The method of claim 12, wherein the surface treatment is performed on a rear surface of the patterned source layer.
14. A method of manufacturing a semiconductor device, the method comprising the steps of:
forming a unit chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer;
turning over the unit chip;
exposing a rear surface of the source layer by removing the first substrate from the unit chip;
irradiating the source layer with a laser beam incident on the rear surface of the source layer;
patterning the source layer irradiated with the laser beam;
forming a peripheral circuit chip comprising a second substrate and a circuit on the second substrate; and
the unit chip including the patterned source layer is bonded to the peripheral circuit chip.
15. The method of claim 14, wherein the source layer comprises a polysilicon layer and a grain size of the polysilicon layer increases due to laser irradiation.
16. A method of manufacturing a semiconductor device, the method comprising the steps of:
forming a unit chip including a first substrate, a patterned source layer on the first substrate, a stacked structure on the patterned source layer, and a channel layer passing through the stacked structure and coupled to the patterned source layer;
turning over the unit chip;
exposing the patterned source layer by removing the first substrate from the unit chip;
irradiating the patterned source layer with a laser beam incident on a rear surface of the patterned source layer;
forming a peripheral circuit chip comprising a second substrate and a circuit on the second substrate; and
the unit chip including the patterned source layer irradiated with the laser beam is bonded to the peripheral circuit chip.
17. The method of claim 16, wherein the source layer comprises a polysilicon layer and a grain size of the polysilicon layer increases due to laser irradiation.
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