CN111916393B - Method for manufacturing semiconductor device - Google Patents
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- CN111916393B CN111916393B CN202010802312.XA CN202010802312A CN111916393B CN 111916393 B CN111916393 B CN 111916393B CN 202010802312 A CN202010802312 A CN 202010802312A CN 111916393 B CN111916393 B CN 111916393B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
The invention provides a method for preparing a semiconductor device, which comprises adjusting a hydrogen passivation process to a first passivation layer, forming a second passivation layer on the first passivation layer, patterning the second passivation layer and the first passivation layer, when the hydrogen passivation process is carried out, the top metal interconnection layer is covered by the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can fully restrain the thermal strain caused by the fact that the top metal interconnection layer is mismatched due to the difference of the thermal expansion coefficients in the temperature rising and falling process of the hydrogen passivation process, the top metal interconnection layer is prevented from generating the hill-shaped defect, the insecure electric connection between the top metal interconnection layer and a packaging lead is avoided, the inner cavity caused by the hill-shaped defect is prevented, the tensile stress between the top metal interconnection layer and the lower conductive through hole is avoided, the resistance integrity of the interconnection structure is guaranteed to the maximum extent, and the yield and the reliability of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor preparation, in particular to a preparation method of a semiconductor device.
Background
In the preparation process of the semiconductor device, a whole set of working procedures iterate a circuit on the surface of a substrate through hundreds of processing steps, a semiconductor device is formed on the substrate in the former working procedure, a plurality of metal interconnection layers are formed in the latter working procedure, then a passivation layer is grown on the top metal interconnection layer to serve as a protection layer, and finally a pad area is etched in the passivation layer at the position interconnected with the outside.
Because aluminum has good conductivity, adhesion and ductility, most of the current metal interconnection technologies adopt aluminum interconnection technologies. Because aluminum has an electromigration phenomenon, after a pad area is etched, a hydrogen passivation process is required to be performed, and the hydrogen passivation process can repair defects in each thin film layer, reduce contact resistance of a metal layer, and repair interface state defects such as damage caused by movable ion charges. However, when the hydrogen passivation process is performed, because the thermal expansion coefficient of the top metal interconnection layer is mismatched with the passivation layer to cause an interfacial stress difference (the thermal expansion coefficient of the aluminum material is usually several tens times of that of the medium), a lateral compressive stress in the interfacial stress difference presses the top metal interconnection layer in a cooling process, so that a pad region in the top metal interconnection layer, which does not cover the passivation layer, is pressed upwards to release the stress, the top metal interconnection layer made of the aluminum material is in a polycrystalline phase, and the Hillock Defects (Hillock Defects) are easily formed in the pad region due to non-uniform volume change. Fig. 1a is a schematic diagram of a pad region of a top metal interconnection layer, a hillock defect is a black dot in fig. 1a, and fig. 1b is a three-dimensional diagram of a single hillock defect under an atomic force microscope, as can be seen from fig. 1a and fig. 1b, the hillock defect may cause poor appearance, and a serious hillock defect may also cause weak electrical connection between the top metal interconnection layer and a package lead, thereby affecting yield and reliability of a device.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which aims to solve the problem that a hillock defect is easily generated on a top metal interconnection layer after a hydrogen passivation process is performed on the conventional semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, which comprises, after forming a top metal interconnection layer on a front structure of the semiconductor device:
forming a first passivation layer on the top metal interconnection layer;
forming a second passivation layer on the first passivation layer;
performing a hydrogen passivation process; and the number of the first and second groups,
and patterning the second passivation layer and the first passivation layer to expose at least part of the top metal interconnection layer.
Optionally, the top metal interconnection layer includes a metal layer, and the metal layer is made of aluminum or an aluminum-copper alloy.
Optionally, the top metal interconnection layer further includes a first blocking layer and a second blocking layer, the first blocking layer is located above the second blocking layer, and the metal layer is located between the first blocking layer and the second blocking layer.
Optionally, the material of the first barrier layer and the second barrier layer includes titanium and/or titanium nitride.
Optionally, the reaction temperature of the hydrogen passivation process is 400-450 ℃, and the reaction time is 30-60 minutes.
Optionally, the first passivation layer is a laminated structure of an oxygen-rich silicon layer and a non-doped silicon glass layer, wherein the oxygen-rich silicon layer is formed by a plasma enhanced chemical vapor deposition process, and the non-doped silicon glass layer is formed by a high-density plasma chemical vapor deposition process.
Optionally, the material of the second passivation layer includes silicon nitride, and is formed by using a plasma enhanced chemical vapor deposition process.
Optionally, a dielectric layer is further formed between the front structure of the semiconductor device and the top metal interconnection layer, and the dielectric layer is a laminated structure of an oxygen-rich silicon layer and a non-doped silicon glass layer, wherein the oxygen-rich silicon layer is formed by adopting a plasma enhanced chemical vapor deposition process, and the non-doped silicon glass layer is formed by adopting a high-density plasma chemical vapor deposition process.
Optionally, after performing the hydrogen passivation process and before forming the second passivation layer on the first passivation layer, the method further includes:
and flattening the first passivation layer, wherein the sum of the thickness of the flattened first passivation layer and the thickness of the second passivation layer is greater than the thickness of the top metal interconnection layer.
Optionally, the semiconductor device includes a metal oxide field effect transistor.
The preparation method of the semiconductor device provided by the invention has the following beneficial effects:
1) after a hydrogen passivation process is adjusted to a first passivation layer to form a second passivation layer, before the second passivation layer and the first passivation layer are patterned, when the hydrogen passivation process is carried out, a top metal interconnection layer is covered by the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can fully inhibit thermal strain caused by stress mismatch due to difference of thermal expansion coefficients of the top metal interconnection layer in the temperature rising and falling process of the hydrogen passivation process, prevent the top metal interconnection layer from generating a hill-shaped defect, avoid the unstable electric connection between the top metal interconnection layer and a packaging lead wire, prevent an inner cavity caused by the hill-shaped defect, avoid tensile stress between the top metal interconnection layer and a lower conductive through hole, furthest ensure the resistance integrity of an interconnection structure, and improve the yield and the reliability of a device;
2) patterning the second passivation layer and the first passivation layer is needed subsequently, and excessive interface state defects can not be introduced;
3) when the reaction temperature of the hydrogen passivation process is 400-450 ℃, hydrogen can be quickly and effectively diffused to the surface of the substrate to reach the concentration which is approximately equal to the surface of the passivation layer, and the efficiency of the hydrogen passivation process is improved.
Drawings
FIG. 1a is a schematic diagram of a pad region of a top metal interconnect layer;
FIG. 1b is a three-dimensional view of a single hillock defect in an atomic force microscope;
FIGS. 2a to 2c are schematic structural diagrams of corresponding steps of a method for manufacturing a semiconductor device, wherein FIG. 2c is a schematic structural diagram of the semiconductor device;
FIGS. 3a to 3d are deformation charts of stress deformation of the top metal interconnection layer under 4 different conditions, depicted by contour lines in the z direction;
FIGS. 4 a-4 b are contour plots of all log normal distribution parameter combinations corresponding to total volume and total surface area of hilly defects at reaction temperatures of 400 ℃ and 440 ℃, respectively, for hydrogen passivation;
FIGS. 5a and 5b are schematic diagrams of the change in hydrogen concentration from the passivation layer to the substrate surface with reaction time at reaction temperatures of 440 ℃ and 400 ℃;
fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 7a to 7d are schematic structural diagrams corresponding to respective steps of a method for manufacturing a mosfet according to an embodiment of the present invention, where fig. 7d is a schematic structural diagram of a mosfet;
fig. 8a to 8b are photographs of a pad area of a top metal interconnection layer detected by a high power optical microscope under six process conditions, wherein the reaction temperature of fig. 8a is 440 ℃, and the reaction temperature of fig. 8b is 400 ℃;
wherein the reference numerals are:
100-a substrate; 200-a dielectric layer; 300-top metal interconnect layer; 401 — a first passivation layer; 402-a second passivation layer; 400-a passivation layer; 500-opening;
101-a substrate; 111-a silicon oxide layer; 112-stacked film layers; 201-a dielectric layer; 301-top metal interconnect layer; 411-first passivation layer; 412-a second passivation layer; 410-a passivation layer; 510-an opening;
a G-gate structure; an S-source region; and a D-drain region.
Detailed Description
Fig. 2c is a schematic structural diagram of a semiconductor device. As shown in fig. 2c, the semiconductor device includes a substrate 100, a dielectric layer 200, a top metal interconnection layer 300 and a passivation layer 400, wherein the passivation layer 400 includes a first passivation layer 401 and a second passivation layer 402, and the second passivation layer 402 covers the first passivation layer 401. The passivation layer 400 has an opening 500 therein, the opening 500 exposes a portion of the top metal interconnection layer 300, and the exposed portion of the top metal interconnection layer 300 serves as a pad region. Other film layers may be formed between the dielectric layer 200 and the substrate 100 to form device structures such as a gate structure, and the dielectric layer 200 may include device structures such as a metal interconnection layer or a conductive via, which are not illustrated herein.
Fig. 2a to 2c are schematic structural views of respective steps of a manufacturing method of a semiconductor device. The preparation method of the semiconductor device comprises the following steps: as shown in fig. 2a, a dielectric layer 200 and a top metal interconnection layer 300 are formed on the substrate 100; etching the top metal interconnection layer 300 to make the top metal interconnection layer 300 have a set pattern; as shown in fig. 2b, a first passivation layer 401 and a second passivation layer 402 are sequentially formed on the top metal interconnection layer 300; as shown in fig. 2c, the first passivation layer 401 and the second passivation layer 402 are etched to form an opening 500, and a portion of the top metal interconnection layer 300 exposed by the opening 500 is used as a pad region.
And then, executing a hydrogen passivation process, wherein the hydrogen passivation process is realized by placing the wafer in the figure 2c into a reaction cavity, increasing the temperature of the reaction cavity and introducing hydrogen or mixed gas of the hydrogen and carrier gas into the reaction cavity. Hydrogen diffuses from the top surface of the device through the top metal interconnection layer 300 and the dielectric layer 200 to the interface between the gate oxide layer and the substrate 100, increasing the temperature can increase the diffusion effect of hydrogen, but during cooling the hillock defects caused by the body phase transition generated by the stress release of the top metal interconnection layer 300 are more. The hillock defects can be reduced by adjusting the temperature increase and decrease rate, the hydrogen introduction, the stop time, and the doping of the hydrogen with an inert gas.
When the hydrogen passivation process starts, the temperature of each film layer in the device rises simultaneously, and when the temperature drops to the ambient temperature after the hydrogen passivation process ends, thermal stress is generated due to different thermal expansion coefficients of each film layer in the device, so that the pad region of the top metal interconnection layer 300 deforms.
Setting the thermal expansion of the metal layers of the top metal interconnect layer to linear thermal expansion, the relationship between the thermal strain epsilon and the linear thermal expansion coefficient alpha is generally represented by the following formula:
the strain between the top metal interconnection layer and the passivation layer due to the mismatch of the thermal expansion coefficients is as follows:
for each phase of uniform film material, the bulk strain can be approximately 3 times the line strain, and the stress of the thermal strain on the top metal interconnection layer is:
wherein alpha is1，α2The thermal expansion coefficients of the top metal interconnection layer and the passivation layer respectively,
for temperature difference, E is Young's modulus and v is Poisson's ratio
In practical applications, the dielectric layer, the top metal interconnection layer, and the passivation layer in the device are usually formed by stacking about 10 film layers, the pad area of the top metal interconnection layer is not constrained, and the stress equation (formula 3) can only be solved in a numerical manner, specifically, a Finite Element Method (Finite Element Method) is used. The simulated film structure comprises a dielectric layer, a top metal interconnection layer (metal layer in table 1) and a passivation layer on a front structure of a semiconductor device, the simulated conditions comprise that a pad area of the top metal interconnection layer is subjected to or not subjected to thermal stress change and corresponding volume thermal strain in the temperature rising and reducing process, and the simulated parameters are listed in table 1.
Table 1: material and characteristics of each film layer
In the hydrogen passivation process, the semiconductor device is heated in a reaction cavity to a set temperature, and then cooled to room temperature (such as 23 ℃) after reaching thermal stability, and the stress distribution and deformation after stabilization are simulated. The simulation is carried out on four conditions by combining practical application:
1) performing a hydrogen passivation process at 400 ℃ before the passivation layer is etched;
2) performing a hydrogen passivation process at 440 ℃ before the passivation layer is etched;
3) performing a hydrogen passivation process at 400 ℃ after the passivation layer is etched;
4) a hydrogen passivation process is performed at 440 c after the passivation layer etch.
The stress deformation of the top metal interconnect layer is depicted by the z-direction contour lines and the results are shown in fig. 3a, fig. 3b, fig. 3c and fig. 3d, respectively.
As can be seen by comparing fig. 3a, 3b, 3c and 3d, a hydrogen passivation process is performed before the passivation layer is etched, the top metal interconnection layer is constrained by the upper passivation layer and the lower dielectric layer, and the thermal expansion deformation in the z direction is less than 0.03 μm; and performing a hydrogen passivation process after the passivation layer is etched, wherein the thermal expansion coefficient of the top metal interconnection layer is far greater than that of the medium, and the pad area is not constrained, so that the pad area of the top metal interconnection layer extends above the pad area under the action of thermal stress, the maximum value of the thermal expansion deformation in the z direction is 0.5 μm, which is equivalent to the maximum value of the thermal expansion deformation in the z direction being 0.5 μm, and the volume strain of the top metal interconnection layer under each condition is listed in table 2.
Table 2: the top metal interconnection layer is under the thermal expansion body strain under the restrained and unrestrained conditions
| Annealing station, temperature | Volume of thermal expansion strain (m)3) |
| Before etching of the passivation layer, the temperature is 400 DEG C | 1.681×10-17 |
| 440 ℃ before the passivation layer is etched | 1.871×10-17 |
| After the passivation layer is etched, the temperature is 400 DEG C | 2.753×10-16 |
| Etching the passivation layer at 440 deg.C | 3.035×10-16 |
As can be seen from table 2, the thermal expansion bulk strain of the top metal interconnection layer increases with the temperature increase, and the bulk strain of the top metal interconnection layer increases by 16-17 times when the hydrogen passivation process is performed after the passivation layer is etched compared with the hydrogen passivation process performed before the passivation layer is etched.
Because the formation of the hill-shaped defects is the process of releasing and converting the deformation energy of the film thermal expansion body, in order to further compare the consistency of the simulation result and the measured data of the production line, the quantity, the size and the distribution of the hill-shaped defects are supposed to be restricted by two conditions:
1) the sum of the hilly defect volumes is equal to the thermal expansion strain volume of the top metal interconnection layer;
2) the sum of the surface energies of the hilly defects is equal to the thermal expansion elastic strain energy of the top metal interconnection layer;
wherein the surface energy of the hillock defects is equal to the product of the metal surface energy coefficient and the total surface area of the hillock defects.
Based on the actually measured morphology and distribution rule of the hilly defects, the following assumptions are made on the sizes and the distribution of the hilly defects:
1) the shape of the hilly defect is a regular hexagon columnar structure, and the ratio of the height (length in the z direction) to the side length of the regular hexagon is about 0.02: 1;
2) the thalamic defect size distribution follows a log normal distribution.
Firstly, the volume and the area of the hill defect corresponding to the expected value and the standard deviation are calculated by using a numerical integration algorithm. Fig. 4a and 4b provide all lognormal distribution parameter combinations corresponding to total volume (solid line) and total surface area (dashed line) of hilly defects at reaction temperatures of 400 c and 440 c, respectively, for hydrogen passivation. As can be seen from fig. 4a and 4b, the solid line and the dotted line have an intersection, and the distribution of the log normal corresponding to the intersection satisfies both constraints of the total volume and the total surface energy, thereby determining the hill defect distribution of the reaction temperature corresponding to the intersection.
From the intersection point, the lognormal distribution parameters can be determined, and the expected value and standard deviation of the hill defect distribution are obtained: 400 ℃ below zero: the expected value is 1.93 μm, and the standard deviation is 4.86 μm; 440 ℃, and the temperature is: the expected value is 2.76 μm and the standard deviation is 3.15 μm. It can be seen that the expected value of the hillock defects at the reaction temperature of 440 ℃ is about 1.4 times that of the hillock defects at the reaction temperature of 400 ℃ and the number of hillock defects is reduced by half, which is consistent with the actual measurement result.
Further, another important parameter of the hydrogen passivation process is the diffusion and reaction of hydrogen in the semiconductor device, which reaches the region to be repaired in the semiconductor device through three stages in the reaction chamber:
the first stage is as follows: convective mass transport in the gas;
and a second stage: adsorption and dissolution of the surface of the semiconductor device;
and a third stage: diffusion within a semiconductor device.
In the first stage, the mass transfer flux F is transmitted through the boundary layer perpendicularly to the surface of the semiconductor device1(unit: number of molecules/cm)2s) is:
F1＝hg(Cgb-Cgsyrf) (4)
wherein h isgIs the mass transfer coefficient (unit: cm/s), CgbIs the gas concentration (unit: molecule number/cm) of the main flow area3Or mole number/cm3)，CgsyrfIs the boundary layer edge gas concentration (unit: number of molecules/cm)3Or mole number/cm3)。
In the second stage, the solubility C of gas molecules at the gas-solid interface0Is as follows;
C0＝βCgsurf (5)
wherein beta is the solubility coefficient of gas molecules in solid, and the solubility of hydrogen in silicon dioxide is 3.5 multiplied by 10 respectively at 400 ℃ and 440 DEG C17Mole number/cm3And 2.8X 1017Mole number/cm3。
Mass transfer flux F of diffusion of the medium layer in the third stage2(unit: number of molecules/cm)2s) is;
wherein C is the concentration of hydrogen in the medium (unit: number of molecules/cm)3Or mole number/cm3) And D is a diffusion coefficient (unit: cm2/s)。
Considering the concentration as a function of time, the diffusion of C as a function of reaction time t can be expressed as:
for the diffusion process of a gas in a solid, the diffusion coefficient D is related to the reaction temperature T and can be expressed as:
wherein D is0Is a pre-exponential factor, EaThe activation energy (unit: eV) required for the diffusion of gas molecules in a solid, and k is the Boltzmann constant.
The boundary conditions and initial conditions were:
1)C＝C1，x＝0，t≥0
2)C＝C2，x＝L，t≥0
3)C＝f(x)，0<x<L，t＝0
the concentration distribution of gas molecules in the solid is:
wherein L is the depth of the passivation layer to the bottom of the well region in the substrate, C1And C2N is the amount of substance (unit: mole) in terms of the concentration of hydrogen at the upper surface of the passivation layer and at the bottom of the well region.
The diffusion coefficient of hydrogen in gas phase is 10-1cm2/s～100cm2S, and a diffusion coefficient in solids of 10-6cm2/s～10-8cm2In the interval/s, it can be assumed that the diffusion of hydrogen in the solid during the hydrogen passivation process is a bottleneck step. 0.153-0.18 mu mThe back process of the logic process adopts aluminum material (or copper-aluminum alloy) as the metal interconnection layer, the number of the top metal interconnection layer is usually 3-5, and the distance from the corresponding passivation layer to the top surface of the semiconductor device is about 2.5-4.0 μm. The diffusion coefficient of hydrogen in solid aluminum is slightly larger than that in a medium, and the minimum diffusion system and the medium layer with the maximum thickness are used as setting conditions to ensure the sufficiency and effectiveness of the conclusion.
The concentration of hydrogen in the top metal interconnection layer and the dielectric layer is 0 before the hydrogen passivation process is started, and the concentration of hydrogen in the solid interface of the passivation layer is the solubility of hydrogen in silicon oxide. The reaction time of the hydrogen passivation process is typically 30 minutes to 60 minutes. For two representative reaction temperatures: the results are expressed by the ratio of the hydrogen concentration at a certain point of the dielectric layer to the solid interface concentration of the passivation layer, and fig. 5a and 5b show the change of the hydrogen concentration from the passivation layer to the substrate surface with the reaction time at the reaction temperature of 440 ℃ and 400 ℃ respectively, wherein the five time periods in the figure are 0.001s, 0.01s, 0.1s, 1.0s, 10.0s and 100.0s respectively. As can be seen from fig. 5a and 5b, the diffusion speed of hydrogen in the dielectric layer is very fast, and at 10s, the concentration of hydrogen on the surface of the substrate reaches 90% of the concentration of the solid interface of the passivation layer; the reaction temperature is 400 ℃ and 440 ℃, and the concentration of hydrogen on the surface of the substrate reaches 96 percent and 95 percent respectively when the reaction time is 100 s. At a reaction temperature of 400 ℃, the solubility of hydrogen in the dielectric layer is 25% higher than that at the reaction temperature of 440 ℃, so that at the reaction temperature of 400 ℃, the absolute value of the hydrogen concentration at the surface of the substrate is higher than that at the reaction temperature of 440 ℃.
In summary, the following conclusion is obtained through the influence of the thermal strain of the top metal interconnection layer-dielectric layer on the formation of the hillock defects and the thermal diffusion simulation in the hydrogen passivation process:
1) the pad area of the top metal interconnection layer has minimum thermal strain under the condition of being affected by the top metal interconnection layer, so that the hill defects can be restrained to the maximum extent, and the thickness of the medium covering the top metal interconnection layer is larger than or equal to that of the top metal interconnection layer, namely, the top metal interconnection layer is affected by the maximum factor affecting the hill defects;
2) the reaction temperature is 400-450 ℃, and the hydrogen can effectively diffuse to the surface of the substrate within 120s to reach the concentration which is approximately equal to the surface of the passivation layer.
Based on the above, in the method for manufacturing the semiconductor device provided by the invention, after the hydrogen passivation process is adjusted to the second passivation layer formed on the first passivation layer, and before the second passivation layer and the first passivation layer are patterned, when the hydrogen passivation process is carried out, the top metal interconnection layer is covered by the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can fully restrain the thermal strain caused by the fact that the top metal interconnection layer is mismatched due to the difference of the thermal expansion coefficients in the temperature rising and falling process of the hydrogen passivation process, the top metal interconnection layer is prevented from generating the hill-shaped defect, the insecure electric connection between the top metal interconnection layer and a packaging lead is avoided, the inner cavity caused by the hill-shaped defect is prevented, the tensile stress between the top metal interconnection layer and the lower conductive through hole is avoided, the resistance integrity of the interconnection structure is guaranteed to the maximum extent, and the yield and the reliability of the device are improved.
Furthermore, the second passivation layer and the first passivation layer only need to be patterned subsequently, and excessive interface state defects can not be introduced.
Furthermore, when the reaction temperature is 400-450 ℃, the hydrogen can be quickly and effectively diffused to the surface of the substrate to reach the concentration which is approximately equal to the surface of the passivation layer, and the efficiency of the hydrogen passivation process is improved.
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. As shown in fig. 6, the method for manufacturing a semiconductor device according to this embodiment, after forming a top metal interconnection layer on a front structure of the semiconductor device, includes:
step S100: forming a first passivation layer on the top metal interconnection layer;
step S200: forming a second passivation layer on the first passivation layer;
step S300: performing a hydrogen passivation process; and the number of the first and second groups,
step S400: and patterning the second passivation layer and the first passivation layer to expose at least part of the top metal interconnection layer.
Fig. 7a to 7d are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing a mosfet according to this embodiment. Next, this embodiment will describe in detail a method for manufacturing the semiconductor device with reference to fig. 7a to 7d, and the semiconductor device is a mosfet shown in fig. 7 d. However, it should be understood that the semiconductor device in the present invention is not limited to the mosfet, and may be other semiconductor devices.
Specifically, referring to fig. 7a, the process for forming the front-end structure of the semiconductor device includes:
a substrate 101, such as a silicon substrate, is provided, which substrate 101 may also be made of other materials, such as germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs) or silicon carbide (SiC) materials, etc. A plurality of active regions are formed in the substrate 101 by ion implantation (e.g., arsenic ion or phosphorus ion implantation), and the active regions include a source region S, a drain region D, and a channel region between the source region S and the drain region D, and adjacent active regions are separated by a shallow trench isolation structure (not shown). Of course, other suitable components of the integrated circuit device and interconnect structures (not shown) connecting the integrated circuit device may also be formed in the substrate 101.
Next, a silicon oxide layer 111 is grown on the substrate 100 by a process such as thermal oxidation, and the silicon oxide layer 111 is a gate silicon oxide layer.
Subsequently, a gate structure G is formed on the silicon oxide layer 111 by a process such as Chemical Vapor Deposition (CVD). The gate structure G may be a composite structure film composed of polysilicon and a dielectric. In the process of manufacturing the gate structure G, the silicon oxide layer 111 is etched in a self-aligned manner with respect to the gate structure G, so that the silicon oxide layer 111 is only located between the gate structure G and the substrate 100.
After the gate structure G is formed, a metallization process is required. Specifically, a stacked film layer 112 is formed on the gate structure G, the stacked film layer 112 is a stacked structure formed by a plurality of metal interconnection layers and a plurality of dielectric film layers, and the gate structure G, the source region S and the drain region D are led out by the plurality of metal interconnection layers. In practical cases, the semiconductor device may have four, five, eight, ten to tens of metal interconnection layers, which are not illustrated one by one here.
Thus, the preparation of the front structure of the semiconductor device is completed.
Next, with reference to fig. 7a, a dielectric layer 201 and a top metal interconnection layer 301 are formed on the front structure (on the stacked film layer 112) of the semiconductor device, and a conductive via is formed in the dielectric layer 201 to electrically connect the top metal interconnection layer 301 with the metal interconnection layer therebelow. It should be understood that the metal interconnect layer and the top metal interconnect layer 301 are both patterned film layers.
In this embodiment, the dielectric layer 201 is a stacked structure of a silicon oxide rich layer (SRO) and a non-doped silicon glass layer (USG), wherein the silicon oxide rich layer is formed by a plasma enhanced chemical vapor deposition process, and the non-doped silicon glass layer is formed by a high density plasma chemical vapor deposition process. Further, the silicon oxide rich layer (SRO) has a thickness of
The thickness of the undoped silicate glass layer is
The top metal interconnect layer 301 includes a metal layer made of aluminum or aluminum copper alloy (0.5% copper). Optionally, the top metal interconnection layer 301 further includes a first barrier layer and a second barrier layer, the first barrier layer is located above the second barrier layer, and the metal layer is located above the first barrier layer and the second barrier layerAnd the second barrier layer. In this embodiment, the first barrier layer and the second barrier layer are stacked layers of a titanium layer and a silicon nitride layer, wherein the titanium layer has a thickness of
The thickness of the silicon nitride layer is
But should not be limited thereto, the material of the first barrier layer and the second barrier layer may include titanium and/or titanium nitride, and the first barrier layer and the second barrier layer may block aluminum or copper diffusion in the metal layer.
Next, as shown in fig. 7b, step S100 is performed to form a first passivation layer 411 on the top metal interconnection layer 301. In this embodiment, the first passivation layer 411 is a stacked structure of a silicon oxide rich layer and a non-doped silicate glass layer, wherein the silicon oxide rich layer is formed by a plasma enhanced chemical vapor deposition process, and the non-doped silicate glass layer is formed by a high-density plasma chemical vapor deposition process.
Next, referring to fig. 7c, in step S200, the first passivation layer 411 is planarized by, for example, a grinding process to thin the first passivation layer 411. Then, a second passivation layer 412 is formed on the first passivation layer 411, and the first passivation layer 411 and the second passivation layer 412 together form a passivation layer 410. In this embodiment, the material of the second passivation layer 412 includes silicon nitride, and is formed by a plasma enhanced chemical vapor deposition process. Further, the second passivation layer has a thickness of
In this embodiment, the sum of the thickness of the first passivation layer 411 and the thickness of the second passivation layer 412 after planarization is greater than the thickness of the top metal interconnection layer 301, so as to provide a better constraint force for the top metal interconnection layer 301.
Then, step S300 is executed to execute a hydrogen passivation process, specifically, the substrate 101 is placed in a reaction chamber of a hydrogen passivation apparatus, the reaction chamber may be first evacuated and heated, and then a reaction gas is introduced into the reaction chamber to perform the hydrogen passivation process; or inert gas can be introduced into the reaction chamber and the temperature is raised, and then reaction gas is introduced into the reaction chamber to carry out the hydrogen passivation process. Hydrogen atoms in the hydrogen can diffuse inwards from the surface of the device and reach a gate silicon oxide layer, a source region, a drain region or a channel region of the device to passivate dangling bonds, repair interface state defects and repair damage caused by an ion implantation process, so that the drain current-gate voltage performance can be improved, namely, the on-state current is increased, the drain current is reduced, and the subthreshold current characteristic is improved.
It will be appreciated that the reactant gas may be pure hydrogen (ideally), and that the hydrogen concentration in the reaction chamber can be ensured even at low reactant gas flow rates. Certainly, when the reaction gas is pure hydrogen, the cost is correspondingly increased, as an alternative embodiment, the reaction gas may also be a mixed gas of hydrogen and an inert gas, the inert gas may be nitrogen and/or argon, and the inert gas may be used as a protective gas for the reaction to expel oxygen, so as to improve the repairing effect of the interface state defect.
Further, when a hydrogen passivation process is performed, the top metal interconnection layer 301 is covered by the first passivation layer 411 and the second passivation layer 412, the first passivation layer 411 and the second passivation layer 412 can sufficiently restrain the thermal strain of the top metal interconnection layer 301 in the temperature rise and fall process of the hydrogen passivation process, so that the top metal interconnection layer 301 is prevented from generating a hill-shaped defect, the problem that the electrical connection between the top metal interconnection layer 301 and a packaging lead is not firm is avoided, an inner cavity caused by the hill-shaped defect is prevented, the tensile stress between the top metal interconnection layer 301 and a conductive via hole below the top metal interconnection layer is avoided, the resistance integrity of an interconnection structure is guaranteed to the maximum extent, and the yield and the reliability of a device are improved.
In this embodiment, the reaction temperature of the hydrogen passivation process is 400 to 450 ℃, and in this temperature range, hydrogen can be rapidly and effectively diffused to the surface of the substrate 101 to reach a concentration substantially equal to that of the surface of the first passivation layer 411, so as to improve the efficiency of the hydrogen passivation process, and the reaction time of the hydrogen passivation process is 30 to 60 minutes, which is shorter than that of the prior art, and the reaction temperature is not too high, so as to reduce energy consumption.
Then, referring to fig. 7d, step S400 is performed to pattern the passivation layer 410. Specifically, the second passivation layer 412 and the first passivation layer 411 are sequentially etched to form a plurality of openings 510 in the passivation layer 410, a portion of the top-layer metal interconnection layer 301 exposed by the openings 510 is used as a pad region, and in a subsequent process, the pad region of the top-layer metal interconnection layer 301 may be connected to an external circuit by using a lead.
It can be seen that after the hydrogen passivation process, only the second passivation layer 412 and the first passivation layer 411 need to be patterned subsequently, and excessive interface state defects are not introduced.
In order to further verify that the preparation method of the semiconductor device can improve the hillock defects of the bonding pad region of the top metal interconnection layer, the invention designs a plurality of groups of control experiments.
Performing a hydrogen passivation process on the semiconductor device under three different process conditions, the three different process conditions being: 1) after the passivation layer is patterned, the reaction temperature is 440 ℃; 2) before the first passivation layer is planarized, the reaction temperature is 440 ℃; 3) after the formation of the second passivation layer and before the patterning of the passivation layer, the reaction temperatures were 440 deg.c, respectively. After the hydrogen passivation process, the electrical test results of the semiconductor device are shown in table 3 below (only the test result at 440 ℃, the electrical parameters at 400 ℃ are consistent with 440 ℃, which is omitted here, and the batch difference is normal fluctuation and much smaller than the set specification).
Table 3: comparison of electrical parameters of semiconductor devices after performing a hydrogen passivation process under three different process conditions
Therefore, compared with the process condition 1), the process condition 2) and the process condition 3), the leakage current and the through hole resistance of the semiconductor device obtained are reduced, the power loss of the device in the on and off states is reduced, the heat emission of the device is reduced, and the efficiency and the reliability are improved.
Fig. 8a to 8b are photographs of the pad area of the top metal interconnection layer detected by a high power optical microscope under six process conditions (the reaction temperature of fig. 8a is 440 ℃, and the reaction temperature of fig. 8b is 400 ℃). Comparing fig. 8a and 8b, the semiconductor device obtained under the process condition 1) generates hillock defects, the density of hillock defects generated at the reaction temperature of 400 ℃ is about 2 times that generated at the reaction temperature of 440 ℃, but the average size of the hillock defects is reduced by 50%. The hillock defects of the semiconductor device obtained under the process conditions 2) and 3) are basically eliminated, and meanwhile, the electrical parameter test of the device before delivery is consistent with the existing process.
In summary, in the method for manufacturing a semiconductor device according to the present invention, after the hydrogen passivation process is adjusted to the first passivation layer to form the second passivation layer, and before the second passivation layer and the first passivation layer are patterned, when a hydrogen passivation process is carried out, the top metal interconnection layer is covered by the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can fully restrain thermal strain caused by stress mismatch due to the difference of thermal expansion coefficients of the top metal interconnection layer in the temperature rising and falling process of the hydrogen passivation process, prevent the top metal interconnection layer from generating a hill-shaped defect, avoid the insecure electrical connection between the top metal interconnection layer and a packaging lead, prevent an inner cavity caused by the hill-shaped defect, avoid the tensile stress between the top metal interconnection layer and a lower conductive through hole, furthest ensure the resistance integrity of the interconnection structure, and improve the yield and the reliability of a device; furthermore, the second passivation layer and the first passivation layer only need to be patterned subsequently, and excessive interface state defects can not be introduced; furthermore, when the reaction temperature is 400-450 ℃, the hydrogen can be quickly and effectively diffused to the surface of the substrate to reach the concentration which is approximately equal to the surface of the passivation layer, and the efficiency of the hydrogen passivation process is improved.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A method for manufacturing a semiconductor device is characterized in that after a top metal interconnection layer is formed on a front structure of the semiconductor device, the method comprises the following steps:
forming a first passivation layer on the top metal interconnection layer;
forming a second passivation layer on the first passivation layer;
in the hydrogen passivation process, by modeling and simulating the stress distribution and deformation of the semiconductor device, the reaction temperature is deduced by combining two constraint conditions that the sum of the volume of the hill-shaped defect is equal to the thermal expansion elastic strain of the top metal interconnection layer and the sum of the surface energy of the hill-shaped defect is equal to the thermal expansion elastic strain energy of the top metal interconnection layer; deducing reaction time through the influence of thermal strain of the top metal interconnection layer-dielectric layer on the formation of the hill-shaped defect and the thermal diffusion simulation in the hydrogen passivation process; executing a hydrogen passivation process according to the reaction temperature and the reaction time obtained by simulation; the reaction temperature of the hydrogen passivation process is 400-450 ℃, and the reaction time is 30-60 minutes; and the number of the first and second groups,
patterning the second passivation layer and the first passivation layer to expose at least a portion of the top metal interconnection layer;
the semiconductor device comprises a metal oxide field effect transistor;
a dielectric layer is also formed between the front structure of the semiconductor device and the top metal interconnection layer, and the dielectric layer is a laminated structure of a silicon-rich silicon oxide layer and a non-doped silicon glass layer, wherein the silicon-rich silicon oxide layer is formed by adopting a plasma enhanced chemical vapor deposition process and has the thickness of
The non-doped silicon glass layer is formed by adopting a high-density plasma chemical vapor deposition process and has the thickness of
2. The method for manufacturing a semiconductor device according to claim 1, wherein the top metal interconnection layer comprises a metal layer, and the material of the metal layer is aluminum or an aluminum copper alloy.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the top metal interconnect layer further comprises a first barrier layer and a second barrier layer, the first barrier layer is located above the second barrier layer, and the metal layer is located between the first barrier layer and the second barrier layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the material of each of the first barrier layer and the second barrier layer comprises titanium and/or titanium nitride.
5. The method according to claim 1, wherein the first passivation layer is a stacked structure of a silicon-rich silicon oxide layer and a non-doped silicon glass layer, wherein the silicon-rich silicon oxide layer is formed by a plasma-enhanced chemical vapor deposition process, and the non-doped silicon glass layer is formed by a high-density plasma chemical vapor deposition process.
6. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the second passivation layer includes silicon nitride, and is formed using a plasma enhanced chemical vapor deposition process.
7. The method for manufacturing a semiconductor device according to claim 1, further comprising, before forming the second passivation layer on the first passivation layer:
and flattening the first passivation layer, wherein the sum of the thickness of the first passivation layer after being flattened and the thickness of the second passivation layer is greater than the thickness of the top metal interconnection layer.
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| US20050153519A1 (en) * | 2004-01-08 | 2005-07-14 | Taiwan Semiconductor Manufacturing Co. | Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities |
| US20060208289A1 (en) * | 2005-03-17 | 2006-09-21 | Fujitsu Limited | MOS image sensor |
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