CN111916128B - Method and system for relieving write interference of phase change memory - Google Patents
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Abstract
The invention provides a method and a system for relieving write interference of a phase change memory, which are characterized in that whether write-in data can be compressed or not is judged on a word line level, the data which can be compressed is subjected to sparse processing and is written into a physical memory, and the data which cannot be compressed is directly written into the physical memory; on the bit line level, the use priority of the error correction pointer is set, the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling, so that the safe and dispersed placement of data in a physical memory can be realized, the write interference errors are reduced as much as possible, and the ECP utilization rate is effectively improved with smaller energy consumption.
Description
Technical Field
The disclosure belongs to the technical field of nonvolatile memories, and relates to a method and a system for relieving write interference of a phase change memory.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
In the field of Non-Volatile Memory (NVM), Phase Change Memory (PCM) technology is an important research topic. PCM relies primarily on a phase change material for programming, i.e. Ge2Sb2Te5(abbreviated as GST). The difference in resistance values between PCM cells is very large when the programmed region of GST is in the fully crystalline state and the fully molten state, and thus it can be seen that the difference in resistance values between PCM cells of different programmed region states (crystalline or amorphous) is large enough to represent binary codes '1' and '0', respectively.
However, PCM is known to the inventors to be insufficient in data storage reliability. Being a high density main memory, PCM faces serious write disturb problems at the 20nm technology node. Write disturb refers to PCM cells being affected by heat dissipation from neighboring cells and changing the stored value, resulting in data storage errors. The heat dissipation temperature of the SET operation is low, and the neighbor units cannot be influenced, so that only the write interference caused by the RESET operation is considered. When a PCM cell x is undergoing a RESET operation, the heater is required to provide a temperature above the melting point of GST (about 600 ℃), during which heat is inevitably dissipated to surrounding cells at a temperature above the crystallization point of GST (about 300 ℃) but below the melting point. If the neighbor cell y stores '0' (amorphous state) and there is no read/write operation for the cell, then the cell y may be affected by the heat dissipation of the neighbor cell x, and change from the amorphous state to the crystalline state (because the heat dissipation temperature of the neighbor cell x is sufficient to reach the crystallization point of GST), i.e., the stored value changes from '0' to '1', thereby generating a write disturb error. The conditions under which write disturb occurs can be concluded by a summary as follows: (1) PCM cell y stores '0' (amorphous state) and is in an idle state (no read-write operation); (2) the neighbor cell x of cell y is doing the RESET operation. The write disturb may cause more cell programming errors, reducing the reliability of data storage, and further affecting the normal operation of the program. Write disturb errors have become a non-negligible problem in high density PCM technology.
In recent years, academic and industrial fields have paid close attention to this problem. A simple solution to write disturb is to increase the memory cell pitch so that the neighbor cells receive less heat, but this can severely reduce memory density and defeat the purpose of building high density main memory. Another common solution is to Verify and Correct the strategy (Verify and Correct, VnC), i.e. after programming is completed, compare it with the expected result, Verify it and if not Correct it (RESET operation). VnC are highly susceptible to causing cascaded RESET operations, resulting in a large performance overhead.
Disclosure of Invention
The present disclosure provides a method and a system for alleviating Write interference of a phase change memory, and the present disclosure can solve the Write interference (Write disturb) problem faced by a high-density phase change memory on the premise of ensuring that the overall performance of the memory is not affected basically.
According to some embodiments, the following technical scheme is adopted in the disclosure:
a method of mitigating write disturb for a phase change memory, comprising the steps of:
on the word line level, judging whether the written data can be compressed or not, performing sparse processing on the data which can be compressed, writing the data into a physical memory, and directly writing the data which cannot be compressed;
on the bit line level, the use priority of the error correction pointer is set, the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling.
In the scheme, the frequent pattern compression algorithm is improved to compress the original data, a sparse storage strategy of the compressed data is introduced, scheduling local sharing of the error correction pointer is realized, safe and scattered placement of the data in a physical memory can be realized, write interference errors are reduced as much as possible, the utilization rate of the error correction pointer is effectively improved with smaller energy consumption, and the efficiency is improved.
As an alternative embodiment, at the word line level, with a word length of 64 bits as the minimum compression unit, the matching pattern is increased and the compression object is extended from integer to general data.
As an alternative embodiment, the specific process of determining whether the write data can be compressed includes: if the written data is matched with a preset data mode, the compression mark position 1 of the data line is compressed and the written data is compressed according to a corresponding mode, namely the prefix and the effective data are combined; if the written data can not be compressed, the compression mark position 0 of the data line is written into the physical memory together with the original data.
As an alternative embodiment, in the process of writing to the physical memory, the data line and the compressed flag bit after the thinning process are written to the physical memory at the same time.
As an alternative implementation, when data is read from a physical memory, and when data is read, if a compression flag bit of a data line is 0, the original data is directly read;
if the compression mark bit of the data line is 1, performing reverse processing of sparse and compression in sequence, and reading out the original data.
Further, the sparse reverse processing comprises data exchange based on interval bits, the compressed reverse processing comprises removing '1' of data line complement to obtain compressed data, and the compressed data is decompressed according to a preset data matching mode to obtain original data.
As an alternative embodiment, during scheduling, a specific process of each data row and its neighbor row sharing the associated private error correction pointer includes: detecting the use condition of the error correction pointer of the line, if the error correction pointer is sufficient, using the error correction pointer of the line to correct errors, and recording the position and the correct value of the error unit in the line and the line;
if the resource of the error correction pointer of the row is used up, whether the previous neighbor row and the next neighbor row have idle error correction pointers or not is detected in sequence, if yes, the previous neighbor row and the next neighbor row are used, and if not, the verification and correction strategy is used for error correction.
A system to mitigate phase change memory write disturb, comprising:
the sparse compression module is configured to judge whether the written data can be compressed or not at a word line level, perform sparse processing on the data which can be compressed, write the data into a physical memory, and directly write the data which cannot be compressed;
and the error correction pointer sharing module is configured to set the use priority of the error correction pointer at the bit line level, the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling.
A computer readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to perform a method of mitigating write disturb in a phase change memory.
A terminal device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions adapted to be loaded by a processor and for performing the method for mitigating write disturb in a phase change memory.
Compared with the prior art, the beneficial effect of this disclosure is:
according to the method, on the word line level, whether the written data can be compressed or not is judged firstly, the data which can be compressed is subjected to sparse processing, and then the data which can not be compressed is written into a physical memory, and the data which can not be compressed can be directly written. Through the sparse storage of the written data, the safe and scattered placement of the data in the physical memory is realized, and the write interference errors are reduced as much as possible.
The disclosure proposes an ECP local sharing strategy at the bit line level, namely, a certain data row and a neighbor row share respective private ECP, and simultaneously, the use priority of the ECP is set, and the current row unit is superior to the neighbor row unit. By means of local sharing of ECP error correction resources, the ECP utilization rate is effectively improved with smaller energy consumption.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure.
Fig. 1 is a frequent pattern coding table of MFPC of the present embodiment;
FIG. 2 is a flow chart of compressed data sparse storage based on a frequent pattern compression improvement algorithm of the present embodiment;
fig. 3 is a compressed data read flow diagram of the present implementation based on a frequent pattern compression improvement algorithm.
The specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
Aiming at high-density PCM, the embodiment improves FPC on a word line layer surface to compress original data, and proposes a sparse storage strategy aiming at the compressed data; improvements are made to the scheduling usage of ECPs at the bit line level, proposing an ECP local sharing strategy. The strategy is mainly used for relieving PCM write interference errors, namely, the occurrence frequency of an interference-prone data mode '00' is reduced as much as possible, and the reliability of data storage is improved while the density of a memory is ensured.
Mainly comprises the following aspects: (1) on the word line level, whether the written data can be compressed or not is judged firstly, the data which can be compressed is subjected to sparse processing, and then the data is written into a physical memory, and the data which cannot be compressed can be directly written. Through the sparse storage of the written data, the safe and scattered placement of the data in the physical memory is realized, and the write interference errors are reduced as much as possible. (2) At the bit line level, an ECP local sharing strategy is provided, namely, a certain data row and the neighbor row share respective private ECP, and meanwhile, the use priority of the ECP is set, and the current row unit is superior to the neighbor row unit. By means of local sharing of ECP error correction resources, the ECP utilization rate is effectively improved with smaller energy consumption.
That is, the PCM write disturb mitigation scheme of this embodiment includes two levels, i.e., a word line and a bit line, on the word line level, the FPC is Modified to more efficiently compress the original data (MFPC), and a sparse storage policy (sparse Store, SS) for the compressed data is proposed; on the bitline level, improvements are made to the scheduling usage of ECPs, proposing a Local Sharing of ECPs (LS-ECP). The following description is made in detail from the word line level and the bit line level, respectively.
First, the word line level:
at present, the word length of a computer is mainly 64 bits, the FPC algorithm takes the word length of 32 bits as the minimum compression unit, only 8 matching modes (adopting 3-bit prefix) exist, and a compression object is integer and has larger limitation. The present embodiment proposes an improved algorithm (MFPC) based on FPC, increases the matching Pattern to 16 types (using a 4-bit prefix) with a word length of 64 bits as a minimum Compression unit, and extends the Compression target from integer to general data. Since the purpose of this embodiment is to alleviate the write disturb error, that is, to reduce the frequency of occurrence of the data pattern "00" that is susceptible to disturb as much as possible, the MFPC only compresses data containing more consecutive "0" s, and does not need to implement complete coverage of the data pattern.
If the written data matches one of the data patterns of the MFPC, the compression flag position 1 of the data line is marked and the written data is compressed according to the corresponding pattern, i.e. the prefix and the valid data are combined. If the written data can not be compressed, the compression mark position 0 of the data line is written into the physical memory together with the original data. The frequent pattern coding table for MFPCs is shown in FIG. 1, where one cell of the original data portion represents 16-bit data, italicized ' 0 ' represents 16-bit all-0 data, and italicized ' d0’、‘d1’、‘d2’、‘d3' means general data consisting of ' 0 ' and ' 1 ' or only ' 1 ', and is generally not the same.
The key to the secure placement of data in a physical memory row is to store as few valid data storage cells as possible, and to separate valid data storage cells as many as unused cells (where no error correction is required when write disturb occurs in unused cells). Since there is no unused cell in the data line that cannot be compressed and sparse storage cannot be performed, this embodiment proposes a sparse storage policy (SS) for compressed data. As shown in fig. 2, the SS policy only processes data lines and does not include compression flag bits. Firstly, complementing '1' after compressing data until the total length reaches 64 bits, and then performing sparse processing on the whole data line, wherein the core algorithm is as follows:
wherein lineSize represents the data line size, index represents the position of a certain bit of data in the data line, the initial value is 1, the increment step is 2, and is smaller than lineSize/2, and exchangeData represents the data of exchanging the index position and the (lineSize-1) -index position. After the thinning process is completed, the data line and the compression flag bit (already set to 1) are written into the physical memory.
As shown in fig. 3, when a read operation is performed on data, if the compression flag bit of a data line is 0, the original data is directly read out. If the compression flag bit of the data line is 1, the inverse processing of the sparseness and the compression, i.e., the compaction and the decompression, needs to be performed in sequence. The core algorithm of sparseness is based on data exchange of spacer bits and thus still applies to compact processing. After the compact processing is completed, removing '1' supplemented by the data line to obtain compressed data; and decompressing the compressed data according to a data matching mode in the MFPC to finally obtain the original data.
As a typical implementation, a specific policy may be written as:
the input parameters include: data line L, physical line M, data line size lineSize, compression flag bit flag.
When L is written in M, if L can be MFPC compressed, flag is set to 1, L1Mfpc (L), and compresses L to obtain a compressed data line L1；
At L1Then 1 is supplemented until the total size reaches lineSize, L is obtained2；
The following is performed in a loop:
(index＝1；index<lineSize/2；index+＝2)；
to L2Performing sparse processing to obtain L3；
L3＝exchangeData(index，(lineSize-1)-index)
The flag is compared with L3And writing the data into M.
If L cannot be MFPC compressed, flag is set to 0, and flag and L are written into M.
When L needs to be read from M, flag and L are read from M3；
If the flag is 1, circularly executing:
index＝1；index<lineSize/2；index+＝2；
to L3Compact processing to obtain L2：
L2＝exchangeData(index，(lineSize-1)-index)
Remove L2To get L1；
L＝MFPC(L1)；
To L1Decompressing to obtain an original data line L;
if flag is not 1, L is L3.
At the bit line level
The fixed number of ECP error correction entries for a data row, which can only be used by the row, may result in unbalanced use of ECP resources. The use cases of the private ECP resources of the data line can be divided into 3 types: (1) if the number of the write interference errors of the row is larger than the ECP error correction entry, the ECP resources of the row are insufficient; (2) the error number of the row is just equal to the ECP error correction number, and the ECP resources of the row are fully utilized; (3) the error number of the row is less than the ECP error correction entry, the ECP can completely eliminate the write disturbance error of the row, but the ECP of the row is not fully utilized, and the waste of error correction resources is caused. It can be seen that some rows have insufficient ECP resources to completely eliminate the write disturb, while some rows have idle ECP resources but are idle.
In order to reasonably and fully utilize the ECP error correction resources, this embodiment proposes a Local Sharing of ECP (LS-ECP), that is, a certain data row and its two neighboring rows share their own private ECP. The LS-ECP respectively represents three states of the row where the error unit is located, namely the current row, the previous neighbor row and the next neighbor row by 00, 10 and 11.
When LS-ECP is used for correcting a certain error unit, firstly, the using condition of the ECP of the line is detected, if the ECP is sufficient, the ECP of the line is used for error correction, the error unit corresponds to three record items, and an error correction triple { the line where the error unit is located, the position of the unit in the line and the correct value } is formed. If the ECP resources of the current row are used up, whether idle ECPs exist in the previous neighbor row and the next neighbor row or not is detected in sequence, if yes, the idle ECPs exist in the previous neighbor row and the next neighbor row, and if not, VnC is used for error correction.
Two row marking bits are added on the basis of each row of private ECP by the LS-ECP, so that any data row can share the ECP with two neighbor rows thereof, and the full utilization of error correction resources is realized.
As a typical embodiment, the implementation flow includes:
the input parameters include: physical row M, neighbor rows M-1 and M +1, ECP
If the ECP resources of the physical row M are sufficient, row is set to 00, addr is the position in the cell row, and value is the correct value, i.e. an error correction triplet is constructed.
The ECP stores the error cell information
Otherwise, judging that the ECP resource of the M-1 is sufficient, and if the ECP resource is sufficient, setting:
calculating row as 10, addr as the position in the cell line, and value as the correct value, namely constructing an error correction triple;
or, judging that the ECP resource of the M +1 is sufficient, and if the ECP resource is sufficient, setting:
determining row as 11, addr as the position in the cell line, and value as the correct value, namely constructing an error correction triple;
otherwise, error correction is utilized VnC.
The following product examples are also provided:
a system to mitigate phase change memory write disturb, comprising:
the sparse compression module is configured to judge whether the written data can be compressed or not at a word line level, perform sparse processing on the data which can be compressed, write the data into a physical memory, and directly write the data which cannot be compressed;
and the error correction pointer sharing module is configured to set the use priority of the error correction pointer at the bit line level, the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling.
A computer readable storage medium having stored therein a plurality of instructions adapted to be loaded by a processor of a terminal device and to perform a method of mitigating write disturb in a phase change memory.
A terminal device comprising a processor and a computer readable storage medium, the processor being configured to implement instructions; the computer readable storage medium is used for storing a plurality of instructions adapted to be loaded by a processor and executing the method for mitigating write disturb in a phase change memory.
As will be appreciated by one of skill in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (9)
1. A method for relieving write interference of a phase change memory is characterized by comprising the following steps: the method comprises the following steps:
on the word line level, judging whether the written data can be compressed or not, performing sparse processing on the compressible data, writing the data into the phase change memory, and directly writing the data which cannot be compressed;
setting the use priority of an error correction pointer on a bit line level, wherein the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling;
during scheduling, the specific process of sharing the private error correction pointer with each data row and its neighbor row includes: detecting the use condition of the error correction pointer of the line, if the error correction pointer is sufficient, using the error correction pointer of the line to correct errors, and recording the position and the correct value of the error unit in the line and the line;
if the resource of the error correction pointer of the row is used up, whether the previous neighbor row and the next neighbor row have idle error correction pointers or not is detected in sequence, if yes, the previous neighbor row and the next neighbor row are used, and if not, the verification and correction strategy is used for error correction.
2. The method of mitigating write disturb for a phase change memory as recited in claim 1, wherein: at the word line level, the matching pattern is increased to 16 with a word length of 64 bits as the minimum compression unit.
3. The method of mitigating write disturb for a phase change memory as recited in claim 1, wherein: the specific process of judging whether the write data can be compressed includes: if the written data is matched with a preset data mode, the compression mark position 1 of the data line is compressed and the written data is compressed according to a corresponding mode, namely the prefix and the effective data are combined; if the written data can not be compressed, the compression mark position 0 of the data line is written into the phase change memory together with the original data.
4. The method of mitigating write disturb for a phase change memory as recited in claim 1, wherein: and in the process of writing the compressed data into the phase change memory, simultaneously writing the data line and the compressed mark bit which are subjected to sparse processing into the phase change memory.
5. A method of mitigating write disturb in a phase change memory as claimed in claim 1 or 4, wherein: when reading data from the phase change memory, when reading the data, if the compression mark bit of the data line is 0, directly reading the original data;
if the compression mark bit of the data line is 1, performing reverse processing of sparse and compression in sequence, and reading out the original data.
6. The method of mitigating write disturb for a phase change memory as recited in claim 5, wherein: the sparse reverse processing comprises data exchange based on interval bits, the compressed reverse processing comprises removing '1' supplemented by data lines to obtain compressed data, and the compressed data is decompressed according to a preset data matching mode to obtain original data.
7. A system for mitigating write disturb in a phase change memory, comprising: the method comprises the following steps:
the sparse compression module is configured to judge whether the write-in data can be compressed or not at the word line level, carry out sparse processing on the compressible data, write the data into the phase change memory and directly write the data which cannot be compressed;
the error correction pointer sharing module is configured to set the use priority of the error correction pointer on a bit line level, the unit of the current row is superior to the unit of the neighbor row, and each data row and the neighbor row share the belonged private error correction pointer during scheduling;
during scheduling, the specific process of sharing the private error correction pointer with each data row and its neighbor row includes: detecting the use condition of the error correction pointer of the line, if the error correction pointer is sufficient, using the error correction pointer of the line to correct errors, and recording the position and the correct value of the error unit in the line and the line;
if the resource of the error correction pointer of the row is used up, whether the previous neighbor row and the next neighbor row have idle error correction pointers or not is detected in sequence, if yes, the previous neighbor row and the next neighbor row are used, and if not, the verification and correction strategy is used for error correction.
8. A computer-readable storage medium characterized by: a plurality of instructions stored therein, the instructions being adapted to be loaded by a processor of a terminal device and to perform a method of mitigating write disturb in a phase change memory as claimed in any one of claims 1 to 6.
9. A terminal device is characterized in that: the system comprises a processor and a computer readable storage medium, wherein the processor is used for realizing instructions; the computer readable storage medium is used for storing a plurality of instructions, the instructions are suitable for being loaded by a processor and executing the method for alleviating write disturbance of the phase change memory according to any one of claims 1-6.
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