CN111914978A - ESD device on RFID chip - Google Patents

Abstract

Electrostatic discharge can have destructive consequences for electronic devices, which is one of the main causes of failure of integrated circuits. With the continuous development of integrated circuit technology, the feature size of CMOS circuits is continuously reduced, the gate oxide thickness of transistors is thinner and thinner, the area scale of chips is larger and larger, the current and voltage that MOS transistors can bear are smaller and smaller, and the peripheral use environment is not changed, so how to further optimize the anti-ESD performance of circuits, how to make the effective area of the whole chip as small as possible, and how to meet the requirements for ESD performance reliability without adding additional process steps become the main consideration of IC designers.

Description

ESD device on RFID chip

Technical Field

The invention belongs to the technical field of integrated circuits, in particular to the field of design of EEPROM memories and RFID chips.

Background

RFID refers to radio frequency identification, which is a communication technology that can identify a specific target and read and write related data through a radio signal without establishing physical or optical contact between an identification system and the specific target. The RFID can be used as a unique identity card of each object, and is also a basis for identifying, communicating and interconnecting each object in the Internet of things. In recent years, with the development of technologies such as large-scale integrated circuits, network communication, and information security, the RFID technology is in a commercial application stage. Due to the characteristics of high-speed moving object identification, multi-label simultaneous identification, non-contact identification and the like, the RFID technology shows great development potential and application space. The application fields of the RFID are as follows: logistics, retail, anti-counterfeiting, transportation, identification card identification, medical, food, automotive, and the like.

The working frequency is the most important technical index of the RFID, and the frequency band of the RFID is internationally recognized and divided: low frequency, high frequency, ultra high frequency, microwave. The high-frequency RFID is the most mature application at present, the ultrahigh-frequency RFID has the best functional index, and has the advantages of longer reading distance, high-speed moving object identification, high identification speed, long service life, high reliability and the like. With the maturity of the ultra-high frequency RFID manufacturing technology, the cost thereof is rapidly decreasing, and the market of the ultra-high frequency RFID is rapidly increasing, which will become the mainstream in the future.

In chip design, reliability is an important index. ESD (electrostatic discharge) is one of the most serious failure mechanisms in CMOS circuits, and even causes self-burning of the circuits, which seriously affects the reliability of the chips.

Electrostatic discharge can have destructive consequences for electronic devices, which is one of the main causes of failure of integrated circuits. With the continuous development of integrated circuit technology, the feature size of CMOS circuits is continuously reduced, the gate oxide thickness of transistors is thinner and thinner, the area scale of chips is larger and larger, the current and voltage that MOS transistors can bear are smaller and smaller, and the peripheral use environment is not changed, so how to further optimize the anti-ESD performance of circuits, how to make the effective area of the whole chip as small as possible, and how to meet the requirements for ESD performance reliability without adding additional process steps become the main consideration of IC designers.

The design purpose of the ESD protection circuit is to prevent the working circuit from being damaged due to the fact that the working circuit becomes an ESD discharge path, and ensure that ESD generated between any two chip pins has a proper low-resistance bypass to introduce ESD current into a power line. The low resistance bypass circuit is required not only to absorb the ESD current, but also to clamp the voltage of the operating circuit to prevent the operating circuit from being damaged due to voltage overload. The anti-static structure is non-operational during normal operation of the circuit, which results in the ESD protection circuit also needing to have good operational stability, to respond quickly when ESD occurs, while protecting the circuit, the anti-static structure itself cannot be damaged, the negative effects of the anti-static structure (e.g., input delay, must be within acceptable limits, and prevent the anti-static structure from latching up.

Most of the ESD current comes from outside the circuit, so ESD protection circuits are typically designed next to the PAD, inside the I/O circuit. A typical I/O circuit consists of two parts, an output driver and an input receiver. Common ESD protection devices include resistors, diodes, bipolar transistors, MOS transistors, thyristors, and the like. Because the MOS transistor has good compatibility with CMOS process, the MOS transistor is often used to construct a protection circuit

Disclosure of Invention

The invention provides an ESD device on an RFID chip, which is based on the principle that the sealing ring participates in ESD discharge: when ESD occurs, the ESD current can be quickly and effectively led into the ground wire due to the characteristics of the sealing ring, and the important function of protecting the chip and improving the reliability is achieved. The invention is characterized in that the sealring increases the width of the ground wire of the ESD discharge path and reduces the resistance of the ground wire; the ground wire of the peripheral ESD protection is separated from the internal wiring; the ESD performance of the circuit is enhanced without increasing the chip area.

Drawings

Fig. 1 is a circuit diagram of an ESD device on an RFID chip.

Fig. 2 is a schematic diagram of layout design of the ESD device of the present invention.

Detailed Description

The preferred embodiment is described in detail below with reference to fig. 1 and 2.

As shown in fig. 1, the ESD protection circuit is composed of an ESD primary protection device, a resistor, and an ESD secondary protection device.

As shown in FIG. 2, the ESD device of the present invention is proposed, since ESD is introduced into the chip through the PAD, all devices in I/O directly connected to the PAD need to establish a low-resistance bypass of ESD in parallel. The invention provides an ESD device, the ground wires of PADs are connected through the sealring, when external ESD occurs, because the sealring wiring width is wider and the resistance is small, ESD current can be quickly led into the ground wires and then distributed to pins of a chip through voltage wires, and the influence of the ESD is reduced. Particularly, the I/O circuit, i.e., the output driver and input receiver connected to the PAD, must ensure that a low-resistance path is formed in parallel with the protection circuit to bypass the ESD current and clamp the protection circuit voltage immediately and effectively when ESD occurs. And when the two parts work normally, the normal work of the circuit is not influenced.

While the present invention has been described in detail with respect to the preferred embodiments thereof, it will be apparent that various modifications and alternatives thereto will become apparent to those skilled in the art upon reading the foregoing description. The above description and drawings are only examples of the practice of the invention, and it should be understood that the above description is not to be taken as limiting the invention.

Claims (4)

1. The invention provides an ESD device on an RFID chip, which is based on the principle that the sealing ring participates in ESD discharge: when ESD occurs, the ESD current can be quickly and effectively led into the ground wire due to the characteristics of the sealing ring, and the important function of protecting the chip and improving the reliability is achieved.

2. The ESD apparatus of claim 1, wherein the sealring increases a ground width of the ESD discharge path and decreases a ground resistance.

3. The ESD apparatus of claim 1, wherein the sealring separates a ground line of the peripheral ESD protection from the internal trace.

4. The ESD apparatus of claim 1, wherein the sealring enhances ESD performance of the circuit without increasing chip area.

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