CN111913829B - Data reading method, memory controller and memory device - Google Patents

Data reading method, memory controller and memory device Download PDF

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Publication number
CN111913829B
CN111913829B CN201910388319.9A CN201910388319A CN111913829B CN 111913829 B CN111913829 B CN 111913829B CN 201910388319 A CN201910388319 A CN 201910388319A CN 111913829 B CN111913829 B CN 111913829B
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codeword
read
syndrome
target
soft information
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CN111913829A (en
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萧又华
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Shenzhen Daxin Electronic Technology Co ltd
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Shenzhen Daxin Electronic Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a data reading method, a memory controller and a memory device. The method comprises the following steps: reading the target entity page by using a preset reading voltage corresponding to the reading operation to obtain a reading codeword syndrome of the reading codeword; reading the target entity page again by using the first adjustment reading voltage to obtain a first adjustment codeword syndrome of the first adjustment codeword; generating respective soft information of a plurality of target storage units of the target entity page according to the read code word and the first adjustment code word; identifying a target confidence table according to the size relative relation among the syndromes so as to search the confidence degrees of the target storage units from the target confidence table; and executing the adjusted preset decoding operation according to the plurality of soft information and the plurality of confidence levels to obtain effective code words, thereby completing the reading operation.

Description

Data reading method, memory controller and memory device
Technical Field
The present invention relates to a data reading method, and more particularly, to a data reading method and a memory controller suitable for a memory device provided with a rewritable nonvolatile memory module and a memory controller thereof.
Background
In general, when an iterative decoding operation (e.g., a low density parity check code decoding operation) performed on a codeword read from a physical face of a rewritable nonvolatile memory module fails, a memory controller of a memory device attempts to correct a log likelihood ratio table corresponding to the iterative decoding operation based on verification data (e.g., known data previously stored to the rewritable nonvolatile memory module) to re-perform the iterative decoding operation on the read codeword using the corrected log likelihood ratio table.
However, since the conventional method requires additional preparation of known verification data (i.e., storing the known verification data into a plurality of word lines of the rewritable nonvolatile memory module), the conventional method uses the spare space of the rewritable nonvolatile memory module to store the verification data, thereby reducing the remaining usable space of the rewritable nonvolatile memory module, which in turn results in a reduction in the operation efficiency of the memory device due to the reduced remaining usable space (since many management operations of the memory device may require the use of the remaining usable space).
In addition, another conventional method performs a read retry operation by using the adjusted read voltage corresponding to the preset read voltage when decoding fails, so as to re-read the physical page originally read. Then, a decoding operation is performed on the adjusted codeword read out via the adjusted read voltage to attempt to obtain a valid codeword that is successfully decoded. However, in the above-mentioned conventional method, if the read retry operation fails (i.e., a valid codeword cannot be obtained through a decoding operation performed on the codeword read by the adjusted read voltage), the conventional method discards the adjusted codeword that has been obtained, and performs another read retry operation of a different adjusted read voltage on the physical page again. That is, the conventional method may reduce the efficiency of data reading because a plurality of read retry operations are performed. In particular, the adjustment code word obtained by the above-mentioned read retry operation is not used to improve the decoding capability of the memory device, which results in waste of operation resources.
Therefore, how to use other ways to replace the conventional log likelihood ratio table corresponding to the iterative decoding operation without preparing the verification data and to use the mechanism of the read retry operation to improve the defects of the conventional method, enhance the performance of the decoding operation and increase the data reading efficiency of the rewritable nonvolatile memory module is one of the subjects studied by the skilled in the art.
Disclosure of Invention
The invention provides a data reading method, a storage controller and a storage device, which can read a target entity page for a plurality of times by utilizing different reading voltages under the condition that verified data is not required to be prepared, so as to correspondingly obtain a plurality of codewords and a plurality of syndromes corresponding to the codewords. And then, generating respective soft information of a plurality of target storage units of the target entity page according to the relative relation among the plurality of syndromes and the plurality of codewords so as to find out a plurality of confidence levels of the plurality of target storage units from a confidence table corresponding to the relative relation and the target entity page, and further executing an adjusted iterative decoding operation according to the plurality of confidence levels, so as to strengthen decoding capability and improve reading operation efficiency.
An embodiment of the invention provides a data reading method suitable for a memory device configured with a rewritable nonvolatile memory module. The rewritable non-volatile memory module has a plurality of word lines, wherein each word line of the plurality of word lines is coupled to a plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a plurality of physical pages, and each physical page of the plurality of physical pages is to be programmed to a bit value. The method comprises the following steps: selecting a target entity page of a target word line to perform a read operation on a target codeword stored by the target entity page, wherein a plurality of target storage units of the target entity page are used for respectively storing a plurality of target bit values of the target codeword; reading the target entity page using a preset read voltage corresponding to the target entity page to obtain a read codeword corresponding to the target entity page, and performing a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read codeword is stored in a codeword buffer and a first one of the plurality of read codeword syndromes is stored in a syndrome buffer; in response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are not all zero, re-reading the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, and performing the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the first adjusted codeword is stored in the codeword buffer and the first of the plurality of first adjusted codeword syndromes is stored in the syndrome buffer; generating soft information for each of the plurality of target memory cells from a plurality of codewords in the codeword buffer corresponding to the read operation in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero; identifying a target confidence table corresponding to the size relative relation from a plurality of confidence tables corresponding to the target entity page according to the size relative relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the size relative relation of a plurality of patterns, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information patterns; searching the respective confidence degrees of the plurality of target storage units from the target confidence table according to the plurality of soft information of the plurality of target storage units; and substituting a plurality of confidence levels of the plurality of target memory cells for a plurality of log likelihood ratio values corresponding to the plurality of target memory cells in the preset decoding operation, and performing the adjusted preset decoding operation with the substituted plurality of log likelihood ratio values on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and completing the reading operation.
An embodiment of the present invention provides a memory controller for controlling a memory device configured with a rewritable nonvolatile memory module. The memory controller includes: the memory device comprises a connection interface circuit, a memory interface control circuit, a read auxiliary circuit unit, an error checking and correcting circuit and a processor. The connection interface circuit is used for being coupled to the host system. The memory interface control circuit is configured to be coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is configured to be programmed to a bit value. The processor is coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correcting circuit. The processor is used for selecting a target entity page of a target word line to execute a reading operation on a target code word stored in the target entity page, wherein a plurality of target storage units of the target entity page are used for respectively storing a plurality of target bit values of the target code word. The processor is further configured to read the target physical page using a preset read voltage corresponding to the target physical page to obtain a read codeword corresponding to the target physical page, wherein the error checking and correcting circuit is configured to perform a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read auxiliary circuit unit is configured to store the read codeword in a codeword buffer and store a first one of the plurality of read codeword syndromes in a syndrome buffer. In response to determining that the plurality of bit values of the last one of the plurality of read codeword syndromes are not all zero, the processor is further configured to re-read the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, wherein the error checking and correcting circuit is further configured to perform the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the read assisting circuit unit is further configured to store the first adjusted codeword in the codeword buffer and store a first one of the plurality of first adjusted codeword syndromes in the syndrome buffer. In response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero, the read assist circuit is further configured to generate soft information for each of the plurality of target memory cells based on a plurality of codewords in the codeword buffer corresponding to the read operation. Then, the reading auxiliary circuit unit is further configured to identify a target confidence table corresponding to the size relative relation from a plurality of confidence tables corresponding to the target entity page according to the size relative relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the size relative relation of a plurality of aspects, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information aspects. The read assist circuit unit is further configured to search the respective confidence levels of the plurality of target storage units from the target confidence table according to a plurality of soft information of the plurality of target storage units, replace a plurality of log likelihood ratio values of the plurality of target storage units corresponding to the plurality of target storage units in the preset decoding operation with the plurality of confidence levels of the plurality of target storage units, and perform the adjusted preset decoding operation with the replaced plurality of log likelihood ratio values on the plurality of soft information to obtain valid codewords corresponding to the target entity page, and complete the read operation.
An embodiment of the invention provides a memory device. The memory device includes a rewritable non-volatile memory module, a memory interface control circuit, and a processor. The rewritable nonvolatile memory module has a plurality of word lines, wherein each word line of the plurality of word lines is coupled to a plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a plurality of physical pages, and each physical page of the plurality of physical pages is to be programmed to a bit value. The memory interface control circuit is coupled to the rewritable nonvolatile memory module. The processor is coupled to the memory interface control circuit, wherein the processor loads and executes the read-assist program code module to implement a data reading method. The data reading method comprises the following steps: selecting a target entity page of a target word line to perform a read operation on a target codeword stored by the target entity page, wherein a plurality of target storage units of the target entity page are used for respectively storing a plurality of target bit values of the target codeword; reading the target entity page using a preset read voltage corresponding to the target entity page to obtain a read codeword corresponding to the target entity page, and performing a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read codeword is stored in a codeword buffer and a first one of the plurality of read codeword syndromes is stored in a syndrome buffer; in response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are not all zero, re-reading the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, and performing the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the first adjusted codeword is stored in the codeword buffer and the first of the plurality of first adjusted codeword syndromes is stored in the syndrome buffer; generating soft information for each of the plurality of target memory cells from a plurality of codewords in the codeword buffer corresponding to the read operation in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero; identifying a target confidence table corresponding to the size relative relation from a plurality of confidence tables corresponding to the target entity page according to the size relative relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the size relative relation of a plurality of patterns, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information patterns; searching the respective confidence degrees of the plurality of target storage units from the target confidence table according to the plurality of soft information of the plurality of target storage units; and substituting a plurality of confidence levels of the plurality of target memory cells for a plurality of log likelihood ratio values corresponding to the plurality of target memory cells in the preset decoding operation, and performing the adjusted preset decoding operation with the substituted plurality of log likelihood ratio values on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and completing the reading operation.
Based on the above, the data reading method, the memory controller and the memory device according to the embodiments of the present invention can obtain a plurality of codewords corresponding to a target physical page by using a preset read operation (using a preset read voltage) and a read retry operation (using a first adjusted read voltage) performed on the target physical page without preparing verified data, and perform a preset decoding operation on the plurality of codewords to obtain a plurality of corresponding syndromes. And then, in response to a failure of the read retry operation (the syndrome of the codeword of the read retry operation is not zero), generating respective soft information of a plurality of target storage units of the target entity page according to the relative relationship between the syndromes and the codewords, so as to find out a plurality of confidence levels of the plurality of target storage units from a confidence table corresponding to the relative relationship and the target entity page, and further executing the adjusted iterative decoding operation according to the plurality of confidence levels. Therefore, the effective code word of the target entity page can be decoded through the adjusted iterative decoding operation with strong decoding capability, so that the correct effective code word can be obtained after the reading retry operation fails, the correctness and the reliability of the data read from the target word line are improved, the negative effect of the failure of the reading retry operation is reduced, the overall time for obtaining the effective code word by the reading operation is saved, and the overall efficiency of the data reading operation is further improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
Fig. 2 is a flowchart of a data reading method according to an embodiment of the present invention.
FIG. 3A is a schematic diagram of a plurality of converted read voltages and a plurality of memory states corresponding to a plurality of physical pages of a first read voltage pattern (1/2/4) according to an embodiment of the invention.
FIG. 3B is a schematic diagram of a plurality of converted read voltages and a plurality of memory states corresponding to a plurality of physical pages of a second read voltage pattern (2/3/2) according to an embodiment of the present invention.
FIG. 4A is a diagram illustrating the size versus relationship of the plurality of syndromes according to the first falling aspect of the present invention.
FIG. 4B is a diagram illustrating the size versus relationship of the plurality of syndromes according to the first rising aspect according to an embodiment of the present invention.
FIG. 4C is a diagram illustrating the relative sizes of the syndromes according to the embodiment of the invention.
FIG. 5A is a diagram illustrating the size versus relationship of the plurality of syndromes according to the second falling aspect of the present invention.
FIG. 5B is a diagram illustrating the size versus relationship of the plurality of syndromes according to the second rising aspect of the present invention.
FIG. 5C is a diagram illustrating the relative sizes of the plurality of syndromes according to the present invention.
FIG. 6A is a diagram illustrating a plurality of preset confidence levels of a target physical page with 1 transition read voltage and a set corresponding to a first falling pattern according to an embodiment of the present invention.
FIG. 6B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a first falling pattern and a target physical page having 2 converted read voltages according to an embodiment of the present invention.
FIG. 6C is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a first falling pattern and a target physical page having 3 converted read voltages according to an embodiment of the present invention.
FIG. 6D is a diagram illustrating a plurality of preset confidence levels for setting the target physical page corresponding to the first falling pattern and having 4 converted read voltages according to an embodiment of the present invention.
FIG. 6E is a diagram illustrating a plurality of confidence tables corresponding to a first drop pattern of a plurality of target entity pages according to one embodiment of the present invention.
FIG. 7A is a diagram illustrating a plurality of preset confidence levels of a target physical page with 1 transition read voltage and a set corresponding to a first rising pattern according to an embodiment of the present invention.
FIG. 7B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to the first rising pattern and a target physical page having 2 transition read voltages according to an embodiment of the present invention.
FIG. 7C is a diagram illustrating a plurality of confidence tables corresponding to a first rising pattern of a plurality of target entity pages according to an embodiment of the invention.
FIG. 8A is a diagram illustrating a set corresponding horizontal pattern and a plurality of predetermined confidence levels for a target physical page with 1 transition read voltage according to an embodiment of the present invention.
FIG. 8B is a diagram illustrating a set of corresponding horizontal aspects and a plurality of predetermined confidence levels for a target physical page with 2 converted read voltages according to an embodiment of the present invention.
FIG. 8C is a diagram illustrating a plurality of confidence tables for corresponding horizontal aspects of a plurality of target entity pages according to one embodiment of the present invention.
FIG. 9A is a diagram illustrating a plurality of preset confidence levels of the target physical page corresponding to the second falling pattern and having 1 transition read voltage according to an embodiment of the present invention.
Fig. 9B to 9D are schematic diagrams showing setting of a plurality of preset confidence levels corresponding to the second falling pattern and the target physical page with 2 converted read voltages according to an embodiment of the present invention.
FIG. 9E is a diagram illustrating a plurality of confidence tables corresponding to a second drop-down pattern of a plurality of target entity pages according to one embodiment of the present invention.
FIG. 10 is a diagram illustrating a plurality of confidence tables corresponding to a second rising pattern of a plurality of target entity pages according to an embodiment of the present invention.
FIG. 11A is a diagram illustrating setting of a plurality of predetermined confidence levels corresponding to a page of a target entity having 1 transition read voltage according to an embodiment of the present invention.
FIG. 11B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a page of a target entity having 1 transition read voltage according to another embodiment of the present invention.
FIG. 11C is a diagram illustrating a plurality of confidence tables corresponding to the hook status patterns of the plurality of target entity pages according to an embodiment of the present invention.
Fig. 12A is a schematic diagram illustrating calculating offset number differences according to an embodiment of the present invention.
FIG. 12B is a diagram illustrating a statistics table for recording offset number differences and sums of offset number differences according to an embodiment of the present invention.
FIG. 13 is a schematic diagram illustrating a plurality of read voltage sets sorted by offset number difference sum according to an embodiment of the present invention.
[ Symbolic description ]
10: Host system
20: Storage device
110. 211: Processor and method for controlling the same
120: Host memory
130: Data transmission interface circuit
210: Memory controller
212: Data management circuit
213: Memory interface control circuit
214: Error checking and correcting circuit
215: Read-assist circuit unit
2151: Soft information management circuit
2152: Confidence list management circuit
218: Buffer memory
219: Power management circuit
220: Rewritable nonvolatile memory module
230: Connection interface circuit
S21, S22, S23, S24, S25, S26, S27: flow steps of data reading method
V (1) 1～V(1)7、V(i)1～V(i)7: reading voltage
L: bit value of lower entity page
M: bit value of middle entity page
U: bit value of upper entity page
G1 to G8, R61 to R63: threshold voltage distribution region/Gray code pattern
SL1, SL2, SL3: storage state of lower entity page
SM1, SM2, SM3, SM4: storage state of middle entity page
SU1, SU2, SU3, SU4, SU5: storage state of upper physical page
411、412、421、422、431、432、441、442、451、452、461、462、511、512、513、521、522、523、531、532、533、541、542、543、551、552、553、561、562、563： Check seed
600. 700, 800, 900, 1000, 1100, 1200, 1210, 1300: Watch (watch)
C(1)G1G2、C(1)G2G3、C(1)G3G4、C(1)G4G5、C(1)G5G6、C(1)G6G7、C(1)G7G8、C(1)G2G1、C(1)G3G2、C(1)G4G3、C(1)G5G4、C(1)G6G5、C(1)G7G6、C(1)G8G7： Offset count value
D (1) 1～D(1)7、D(2)1～D(2)7、D(X)1～D(X)7: offset number difference
SD (1) to SD (X): sum of offset number difference
Detailed Description
In this embodiment, the memory device includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a memory device controller (also referred to as a memory controller or a memory control circuit). In addition, the storage device is used with a host system so that the host system can write data to or read data from the storage device.
FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.
Referring to fig. 1, a Host System (Host System) 10 includes a Processor (Processor) 110, a Host Memory (Host Memory) 120, and a data transmission interface Circuit (DATA TRANSFER INTERFACE Circuit) 130. In the present embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other by a System Bus (System Bus).
The memory device 20 includes a memory controller (Storage Controller) 210, a Rewritable nonvolatile memory module (Rewritable Non-Volatile Memory Module) 220, and a connection interface circuit (Connection Interface Circuit) 230. The memory controller 210 includes a processor 211, a data management Circuit (DATA MANAGEMENT Circuit) 212, and a memory interface control Circuit (Memory Interface Control Circuit) 213.
In the present embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform the data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.
In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10. The number of data transmission interface circuits 130 may be one or more. The motherboard may be coupled to the memory device 20 via a wired or wireless connection via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid state disk (Solid STATE DRIVE, SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) or the like based on various wireless Communication technologies. In addition, the motherboard may also be coupled to various I/O devices such as a global positioning system (Global Positioning System, GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.
In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component connection interface (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express) standard. And, the data transmission interface circuit 130 and the connection interface circuit 230 use the rapid nonvolatile memory interface standard (Non-Volatile Memory express, NVMe) protocol to transmit data.
However, it should be understood that the present invention is not limited thereto, and the data transmission interface circuit 130 and the connection interface circuit 230 may also be a parallel advanced technology attachment (PARALLEL ADVANCED Technology Attachment, PATA) standard, an Institute of electrical and Electronics engineers (Institute of ELECTRICAL AND Electronic Engineers, IEEE) 1394 standard, a serial advanced technology attachment (SERIAL ADVANCED Technology Attachment, SATA) standard, a universal serial bus (Universal Serial Bus, USB) standard, an SD interface standard, a Ultra-high-speed generation (Ultra HIGH SPEED-I, UHS-I) interface standard, a Ultra-high-speed second-generation (Ultra HIGH SPEED-II, UHS-II) interface standard, a Memory Stick (MS) interface standard, a Multi-chip package (Multi-CHIP PACKAGE) interface standard, a multimedia Memory card (Multi MEDIA CARD, MMC) interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an emp interface standard, a CF interface standard, an integrated drive Electronics (INTEGRATED DEVICE Electronics, IDE) standard, or other suitable standards. In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.
In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present example embodiment, the host memory 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), or the like. However, it should be understood that the present invention is not limited thereto and that host memory 120 may be other suitable memory.
The memory controller 210 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to the instructions of the host system 10.
In more detail, the processor 211 in the memory controller 210 is hardware with operation capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 has a plurality of control instructions, and when the memory device 20 is operated, the control instructions are executed to perform operations such as writing, reading and erasing data.
It should be noted that, in the present embodiment, the Processor 110 and the Processor 211 are, for example, a central processing unit (Central Processing Unit, CPU), a Microprocessor (micro-Processor), or other programmable processing units (micro Processor), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), a programmable controller, an Application SPECIFIC INTEGRATED Circuits (ASIC), a programmable logic device (Programmable Logic Device, PLD), or other similar circuit elements, which are not limited to the present invention.
In one embodiment, the memory controller 210 also has read-only memory (not shown) and random access memory (not shown). In particular, the rom has a boot code (boot code), and when the memory controller 210 is enabled, the processor 211 executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 220 into the ram of the memory controller 210. The processor 211 then runs the control commands to perform data writing, reading and erasing operations. In another embodiment, the control instructions of the processor 211 may also be stored in a program code format in a specific area of the rewritable nonvolatile memory module 220, for example, in a physical storage unit dedicated to storing system data in the rewritable nonvolatile memory module 220.
In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the components of the memory controller 210 may also be considered operations performed by the memory controller 210.
The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to receive the instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., write operations are performed according to write instructions from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (data may be read from one or more memory units in the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.
The memory interface control circuit 213 is used for receiving the instruction of the processor 211, and performs a write (also called Programming) operation, a read operation or an erase operation on the rewritable nonvolatile memory module 220 in cooperation with the data management circuit 212.
For example, the processor 211 may execute a sequence of write instructions to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 may execute a sequence of read instructions to instruct the memory interface control circuit 213 to read data from one or more physical units (also referred to as target physical units) of the rewritable nonvolatile memory module 220 that correspond to the read instructions; the processor 211 may execute an erase command sequence to instruct the memory interface control circuit 213 to perform an erase operation on the rewritable nonvolatile memory module 220. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the rewritable nonvolatile memory module 220 to perform corresponding writing, reading, and erasing operations. In one embodiment, the processor 211 may also issue other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable nonvolatile memory module 220.
In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format acceptable to the rewritable nonvolatile memory module 220 by the memory interface control circuit 213. Specifically, if the processor 211 is to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the instruction sequences may include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing a plurality of preset read voltage values of a preset read voltage set for a read operation or a read assist operation, or performing a garbage collection procedure, etc.). These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
The rewritable nonvolatile memory module 220 is coupled to the memory controller 210 (memory interface control circuit 213) and is used for storing data written by the host system 10. The rewritable nonvolatile memory module 220 may be a single-level memory cell (SINGLE LEVEL CELL, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a Multi-level memory cell (Multi LEVEL CELL, MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a three-level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a four-level memory cell (Quadruple LEVEL CELL, QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), a three-dimensional NAND type flash memory module (3D NAND flash memory module) or a vertical NAND type flash memory module (VERTICAL NAND FLASH memory module), or other flash memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module 220 are arranged in an array.
In this embodiment, the rewritable nonvolatile memory module 220 has a plurality of word lines, wherein each word line of the plurality of word lines is coupled to a plurality of memory cells. Multiple memory cells on the same word line may constitute one or more physical programming units. In addition, a plurality of physical program units may constitute one physical unit (physical block or physical erase unit). In the embodiment, a third-level memory cell (TRIPLE LEVEL CELL, TLC) NAND type flash memory module is taken as an example, that is, in the following embodiments, a memory cell capable of storing 3 bit values is taken as a physical programming unit (that is, in each programming operation, a programming voltage is applied to one physical programming unit and then one physical programming unit to program data), where each memory cell can be divided into a Lower physical page (Lower PHYSICAL PAGE), a middle physical page (MIDDLE PHYSICAL PAGE) and an Upper physical page (Upper PHYSICAL PAGE) each capable of storing one bit value.
In the present embodiment, the memory cell is the minimum unit for writing (programming) data. The physical cells are the smallest unit of erase, i.e., each physical cell contains the smallest number of memory cells that are erased together.
The following embodiments take a third-level memory cell type flash memory module as an example, and perform a read assist operation (the read assist operation is performed on a plurality of memory cells included in a specific word line). The data reading method used for the reading auxiliary operation is also described as follows. However, the read assist operation and the data reading method provided by the embodiments of the present invention can also be applied to other types of flash memory modules.
The memory controller 210 may configure a plurality of logic units for the rewritable nonvolatile memory module 220. The host system 10 accesses user data stored in a plurality of physical units through the configured logic unit. Here, each logical unit may be composed of one or more logical addresses. For example, the Logical unit may be a Logical Block (Logical Block), a Logical Page (Logical Page), or a Logical Sector (Logical Sector). A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical program units, or one or more physical erase units. In this embodiment, the logic unit is a logic block, and the logic subunit is a logic page. Each logic unit has a plurality of logic subunits.
In addition, the memory controller 210 establishes a Logical To physical address mapping table (Logical To PHYSICAL ADDRESS MAPPING table) and a physical To Logical address mapping table (Physical To Logical ADDRESS MAPPING table) To record address mapping relationships between Logical units (e.g., logical blocks, logical pages or Logical sectors) and physical units (e.g., physical erase units, physical program units, physical sectors) allocated To the rewritable nonvolatile memory module 220. In other words, the storage controller 210 may look up the physical unit mapped by a logical unit through the logical-to-physical address mapping table, and the storage controller 210 may look up the logical unit mapped by a physical unit through the physical-to-logical address mapping table. However, the technical concept related to mapping between the logic unit and the physical unit is a common technical means for those skilled in the art and is not a technical scheme to be described in the present invention, and is not repeated here.
In the present embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error checking and correcting circuit 214 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the processor 211 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 220. Then, when the processor 211 reads data from the rewritable nonvolatile memory module 220, the error correction code and/or the error check code corresponding to the data are read at the same time, and the error check and correction circuit 214 performs an error check and correction procedure on the read data according to the error correction code and/or the error check code. In addition, after the error checking and correcting process, if the read data is successfully decoded, the error checking and correcting circuit 214 may return the number of error bits to the processor 211.
In the present embodiment, the error checking and correcting circuit 214 performs an iterative decoding operation (also referred to as an LDPC iterative decoding operation) using a low-density parity-check (LDPC) algorithm. Specifically, after receiving the codeword to be decoded (also referred to as a target codeword or an original codeword), the error checking and correcting circuit 214 starts performing iterative decoding operation on the received codeword, identifies a plurality of Soft information (Soft information) of the received codeword, queries a corresponding log likelihood ratio (Log Likelihood Ratio, LLR) table (also referred to as an LLR table) according to the plurality of Soft information to obtain a plurality of log likelihood ratio values corresponding to the plurality of Soft information, and performs a round of iterative decoding operation on the codeword via the log likelihood ratio values and the Soft information corresponding to the codeword. The iterative decoding operation performed on the codeword via the log likelihood ratio value and Soft information corresponding to the codeword may also be referred to as a Soft decoding (Soft decoding) operation. It should be noted that the iterative decoding operation performed on a Hard bit codeword via a plurality of predetermined log likelihood ratio values of the Hard bit codeword to a corresponding Hard bit codeword may be referred to as a Hard decoding (Hard decoding) operation.
In this embodiment, each time the error checking and correcting circuit 214 completes a round of iterative decoding operations performed on one of the codewords, the error checking and correcting circuit 214 can obtain the decoded codeword corresponding to the codeword and the syndrome corresponding to the decoded codeword. The error checking and correcting circuit 214 may determine whether the iterative decoding operation currently performed is a decoding success or a decoding failure according to the syndrome.
If decoding fails, the error checking and correcting circuit 214 may determine whether to perform one or more subsequent iterative operations again according to the counted total number of iterative decoding operations performed on the codeword and a preset iteration threshold. If the total number of iterations is greater than the iteration threshold, the error checking and correction circuit 214 determines that a predetermined decoding operation (the predetermined decoding operation may include one or more iterative decoding operations) of the codeword fails, and outputs a decoded codeword obtained last and a corresponding syndrome; if the total number is not greater than the predetermined iteration threshold, the error checking and correcting circuit 214 performs a new iteration decoding operation again by using the obtained decoded codeword and the corresponding syndrome. The manufacturer can set the threshold value of the iteration times according to the requirement, and the invention is not limited to the threshold value.
At the end of each (every round of) iterative decoding operation, error checking and correction circuit 214 calculates a syndrome for the decoded codeword that was last obtained before to determine whether the iterative decoding operation was successful at this time. If the decoding is successful (the codeword generated after the decoding is correct, i.e., a valid codeword), ending the iterative operation of this time and also ending the preset decoding operation of this codeword; if the decoding fails (the codeword generated after decoding is an error, that is, an invalid codeword), if the total number of times is not greater than the preset iteration number threshold value, the present iteration operation is ended and a new (next) iteration operation is restarted.
In more detail, in each iterative decoding operation, the error checking and correcting circuit 214 determines whether the bit values of the syndrome corresponding to the decoded codeword are all zero. If the bit values of the syndrome are all zero (i.e., "0"), the error checking and correcting circuit 214 determines that the decoded codeword is correct, completes the iterative decoding operation of this time, completes the preset decoding operation corresponding to the codeword, and outputs the decoded codeword as a valid codeword, thereby completing the reading operation corresponding to the original codeword.
Conversely, if the bit values of the syndrome are not all zero (i.e., have one or more bit values of "1"), the error checking and correcting circuit 214 determines that the decoded codeword is erroneous, and ends the iterative decoding operation and the predetermined decoding operation of the codeword.
In this embodiment, the error checking and correcting circuit 214 further identifies the size of each syndrome according to the total number of bit values "1" of each syndrome (also referred to as the first bit value total; the first bit value is "1"). In other words, the error checking and correction circuit 214 identifies the syndrome having the larger total number of first bit values as the larger syndrome. In one embodiment, the error checking and correcting circuit 214 identifies the total number of bit values "1" (the total number of first bit values) of each of the plurality of syndromes in the syndrome buffer to find the smallest syndrome having the smallest total number of first bit values. The syndrome buffer may be programmed in the buffer memory 218 or in the buffer memory of the read assist circuit 215 or the error checking and correction circuit 214.
It should be noted that the above description is only for explaining the correspondence between the original codeword, the decoded codeword and the corresponding syndrome, and other details about the iterative decoding operation of the low density parity check code algorithm, the original codeword, the syndrome and the decoded codeword are not the technical solution of the present invention, and are not repeated here.
In one embodiment, the memory controller 210 further includes a buffer memory 218 and a power management circuit 219. The buffer memory is coupled to the processor 211 and is used for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data (e.g., log likelihood ratio table, confidence table) for managing the memory device 20, so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 218. The power management circuit 219 is coupled to the processor 211 and is used to control the power of the memory device 20.
In the present embodiment, the read assist circuit unit 215 includes a soft information management circuit 2151 and a confidence table management circuit 2152. The read assist circuit unit 215 is used to perform a read assist operation on a specific physical page of a plurality of word lines. More specifically, the processor 211 may select one of a plurality of word lines (also referred to as a target word line) belonging to a plurality of physical cells of the rewritable nonvolatile memory module 220 at a specific point in time, and instruct the read assist circuit unit 215 to perform a read assist operation on this target word line.
For example, the specific points in time include, but are not limited to: (1) upon failure of the decoding operation; (2) When a word line with a poor physical state (for example, a word line with a large number of erasures, a large number of reads, a long time of redundancy (redundancy time), or a large number of error bits) is read; (3) When the number of error bits of data read from a word line exceeds a threshold value of the number of error bits; (4) when performing a general read operation on the target word line.
For convenience of explanation, the present invention may utilize the results of the read retry operation (READ RETRY operations) and the corresponding technical means and benefits, the following embodiment assumes that the target physical page of the target word line is selected by the memory controller 210 to perform a general read operation and correspondingly perform a subsequent read retry operation. It should be noted that the selected target word line has stored data, i.e., has been programmed with data. In this embodiment, the stored data is not known data or verification data preset by the manufacturer or the system. For example, the stored data is user data.
In this embodiment, the read assist circuit unit 215 may perform a normal read operation or a read retry operation on a target physical page of a target word line to obtain the storage states of the target physical pages of a plurality of target memory cells of the target word line by using a preset read voltage (also referred to as a preset transition read voltage) corresponding to the normal read operation. The preset read voltage of a physical page is a preset transition read voltage for distinguishing the memory states of a plurality of memory cells of the physical page. Generally, the ideal preset transition read voltage will be at the boundary of multiple threshold voltage distributions for all memory cells of the physical page.
The read assist circuit unit 215 may perform a read retry operation on the target physical page to obtain another storage state of the target physical page of each of the plurality of target storage units of the target word line by using an adjusted read voltage (also referred to as an adjusted transition read voltage) corresponding to the preset read voltage. The adjusting read voltage and the preset read voltage have a voltage difference. The adjusted read voltage may be pre-designed according to a read retry index code of a read retry operation and the preset read voltage. The adjusted read voltage may also be generated according to a preset voltage deviation value and the preset voltage, where the adjusted read voltage may be the preset read voltage minus the preset voltage deviation value or plus the preset voltage deviation value. The following describes the concept of the memory state of each physical page and the corresponding converted read voltage.
In the present embodiment, as described above, the target word line stores data. Specifically, the plurality of memory cells of each word line may have one or more physical pages (each storing a bit value), and each memory cell is programmed to store a bit value corresponding to one of a different plurality of Gray Code (Gray Code) patterns, and the total number of Gray Code patterns is P, where the total number of bit values stored by each Gray Code pattern is equal to the total number of physical pages possessed by each memory cell. P is a first predetermined positive integer greater than 2, and the value of P is predetermined according to the type of the rewritable nonvolatile memory module 220. For example, if the rewritable non-volatile memory module 220 is an MLC, p=4, and the total number of bit values stored for each gray code pattern would be equal to 2; if the rewritable non-volatile memory module 220 is SLC, p=2, and the total number of bit values stored in each gray code pattern is equal to 1; if the rewritable nonvolatile memory module 220 is QLC, p=16, and the total number of bit values stored in each gray code pattern is equal to 4.
For the sake of unified explanation, the third-level memory cell type flash memory module is taken as an example in this embodiment, and the plurality of memory cells of the target word line may store bit values corresponding to 8 gray code patterns (p=8), respectively, and the total number of bit values stored in each gray code pattern may be equal to 3. Details of the gray code patterns are described below with reference to fig. 3A.
FIG. 3A is a schematic diagram showing the threshold voltage distribution of the first read voltage pattern (1/2/4) and the corresponding Gray code pattern according to an embodiment of the present invention. Since this embodiment is described by taking the rewritable nonvolatile memory module 220 as an example of the third-level memory cell NAND type flash memory module, P is equal to 8 (i.e., 2 3). Each memory cell of the third-level memory cell NAND type flash memory module has three physical pages to store bit data, respectively, and each memory cell includes a Lower physical page (Lower PHYSICAL PAGE, L), a middle physical page (MIDDLE PHYSICAL PAGE, M), and an Upper physical page (Upper PHYSICAL PAGE, U), each of which can store one bit value. It is assumed that the processor 211 reads a plurality of memory cells (a plurality of target memory cells) of a target word line of the third-level memory cell NAND-type flash memory module via a plurality of converted read voltages V (i) 1～V(i)7 of the preset read voltage set V (i), and thereby identifies different bit values (bit values respectively corresponding to different gray code patterns) stored by the plurality of memory cells. The gate voltage in each memory cell can be divided into 8 gray code patterns according to the converted read voltage V (i) 1～V(i)7 in the predetermined read voltage set V (i), such as 8 gray code patterns of "L:1M:1U:1", "L:1M:1U:0", "L:1M:0U:1", "L:0M:0U:0", "L:0M:1U:0" and "L:0M:1U:1" "(L: representing the bit value of the lower physical page);" M: representing the bit value of the middle physical page); "U: representing the bit value of the upper physical page"). The 8 gray code patterns may also be denoted as "111", "110", "100", "101", "001", "000", "010" and "011",8 bit value combinations, where the ordering of the bit values in each bit value combination is based on the order of the lower, middle and upper physical pages. That is, by respectively applying the read voltages V (i) 1～V(i)7 of different voltage values of the read voltage group V (i) to one memory cell of the target word line, the processor 211 can respectively determine that the bit value (also referred to as bit data or read bit value) stored in the memory cell corresponds to one of the different gray code patterns ("111", "110", "100", "101", "001", "000", "010" and "011") (i.e., read the read bit value from one memory cell of the target word line by using the preset read voltage group V (i)) according to determining whether the channel of the memory cell is turned on.
In this embodiment, the threshold voltage distribution of the word line is divided into a plurality of threshold voltage distribution areas according to the corresponding converted read voltages. The plurality of threshold voltage distribution areas and the plurality of Gray code patterns are in one-to-one mapping relation. Referring to fig. 3A, the threshold voltage distribution area G1 corresponds to the gray code pattern "111"; the threshold voltage distribution region G2 corresponds to Gray code pattern "110"; the threshold voltage distribution region G3 corresponds to Gray code pattern "100"; the threshold voltage distribution region G4 corresponds to Gray code pattern "101"; the threshold voltage distribution region G5 corresponds to Gray code pattern "001"; the threshold voltage distribution region G6 corresponds to Gray code pattern "000"; the threshold voltage distribution region G7 corresponds to Gray code pattern "010"; the threshold voltage distribution region G8 corresponds to the gray code pattern "011". In addition, in the present embodiment, if the gray code pattern corresponding to the memory state of a memory cell is "011", the memory cell can be regarded as belonging to the threshold voltage distribution area G8, or the threshold voltage distribution of the memory cell can be regarded as belonging to the threshold voltage distribution area G8.
It should be noted that, according to the total number of the multiple gray code patterns (in this example, 8) that the memory cells of the rewritable nonvolatile memory module 220 may have, the processor 211 may determine the total number of the multiple converted read voltages of the preset read voltage set, wherein the total number of the multiple converted read voltages of the preset read voltage set is one less than the total number of the multiple gray code patterns (in this example, 7, i.e., P-1=8-1=7). In addition, the total number of the plurality of threshold voltage distribution areas is also equal to the total number of the plurality of gray code patterns.
In more detail, the storage states (also called gray codes) corresponding to one gray code pattern stored in one memory cell can be sequentially combined by the storage State (SL) of the lower physical page, the storage State (SM) of the lower physical page, and the storage State (SU) of the upper physical page of the memory cell (as shown by the arrows in fig. 3A).
In the present embodiment, the conversion read voltage V (i) 4 is used to distinguish the storage states SL1 ("1") and SL2 ("0") of the lower physical page; converting the read voltages V (i) 2 and V (i) 6 to distinguish the storage states SM1 ("1"), SM2 ("0"), and SM3 ("1") of the middle physical page; the transition read voltage V (i) 1、V(i)3、V(i)5、V(i)7 is used to distinguish between the storage states SU1 ("1"), SU2 ("0"), SU3 ("1"), SU4 ("0") and SU5 ("1") of the upper physical page.
In this embodiment, the threshold voltage distribution of the word line is divided into a plurality of threshold voltage distribution areas according to the corresponding converted read voltages. The plurality of threshold voltage distribution areas and the plurality of Gray code patterns are in one-to-one mapping relation. Referring to fig. 3A, the threshold voltage distribution area G1 corresponds to the gray code pattern "111"; the threshold voltage distribution region G2 corresponds to Gray code pattern "110"; the threshold voltage distribution region G3 corresponds to Gray code pattern "100"; the threshold voltage distribution region G4 corresponds to Gray code pattern "101"; the threshold voltage distribution region G5 corresponds to Gray code pattern "001"; the threshold voltage distribution region G6 corresponds to Gray code pattern "000"; the threshold voltage distribution region G7 corresponds to Gray code pattern "010"; the threshold voltage distribution region G8 corresponds to the gray code pattern "011". In addition, in the present embodiment, if the gray code pattern corresponding to the memory state of a memory cell is "011", the memory cell can be regarded as belonging to the threshold voltage distribution area G8, or the threshold voltage distribution of the memory cell can be regarded as belonging to the threshold voltage distribution area G8.
The processor 211 (or the reading auxiliary circuit unit 215) may sequentially read the word lines by using the converted read voltages corresponding to the lower physical page, the middle physical page and the upper physical page in the preset read voltage set, so as to obtain the storage states of the lower physical page, the middle physical page and the upper physical page of the plurality of storage units of the word lines, and further obtain gray codes of the plurality of storage units. For example, assume that the processor 211 (or the read assist circuit unit 215) reads a word line using a preset set of read voltages V (i) to obtain a plurality of gray codes for a plurality of memory cells of the word line. The processor 211 (or the read assist circuit unit 215) first identifies that the storage state of the lower physical page of all the storage units is the storage state SL1 or the storage state SL2 by using the transition read voltage V (i) 4; then, the processor 211 (or the read-assist circuit unit 215) further recognizes that the storage state of the middle physical page of the memory cells is the storage state SM1, the storage state SM2 or the storage state SM3 by using the converted read voltage V (i) 2、V(i)6; then, the processor 211 (or the read assist circuit unit 215) further recognizes that the storage state of the upper physical page of the storage units is the storage state SU1, the storage state SU2, the storage state SU3, the storage state SU4 or the storage state SU5 by using the transition read voltage V (i) 1、V(i)3、V(i)5、V(i)7. In this way, the processor 211 (or the reading auxiliary circuit unit 215) can identify the storage states of the lower physical page, the middle physical page and the upper physical page of all the storage units, and further identify the gray codes stored in all the storage units.
In addition, the rewritable nonvolatile memory module 220 having the characteristics of the above-mentioned plurality of physical pages and the corresponding converted read voltage number can also be regarded as the rewritable nonvolatile memory module 220 (third-level memory cell NAND type flash memory module) having the first read voltage pattern (1/2/4). The "1/2/4" corresponds to the total number of converted read voltages possessed by the "lower physical page/middle physical page/upper physical page", respectively. The present invention is not limited to the rewritable nonvolatile memory module 220 with the first read voltage, and the data reading method, the memory controller and the memory device provided by the present invention are also applicable to the rewritable nonvolatile memory module 220 with other read voltage. The following description is made with reference to fig. 3B.
FIG. 3B is a schematic diagram illustrating the threshold voltage distribution of the second read voltage pattern (2/3/2) and the corresponding Gray code pattern according to an embodiment of the present invention. Referring to FIG. 3B, for the rewritable nonvolatile memory module 220 (the third-level memory cell NAND type flash memory module) with the second read voltage pattern (2/3/2), the read voltages V (i) 1 and V (i) 5 are used to distinguish the memory states SL1 ("1"), SL2 ("0") and SL3 ("1") of the lower physical page; the read voltages V (i) 2、V(i)4 and V (i) 6 are used to distinguish the storage states SM1 ("1"), SM2 ("0"), SM3 ("1") and SM4 ("0") of the middle physical page; the read voltages V (i) 3 and V (i) 7 are used to distinguish between the storage states SU1 ("1"), SU2 ("0") and SU3 ("1") of the upper physical page. The "2/3/2" corresponds to the total number of converted read voltages possessed by the "lower physical page/middle physical page/upper physical page", respectively.
The gate voltages in each memory cell of the rewritable nonvolatile memory module 220 of the second read voltage pattern (2/3/2) can be divided into 8 gray code patterns according to the converted read voltage V (i) 1～V(i)7 in the preset read voltage group V (i), such as 8 gray code patterns of "L:1M:1U:1", "L:0M:0U:0", "L:0M:1U:0", "L:1M: 0" and "L:1M:0U: 1"). The 8 gray code patterns may also be expressed as "111", "110", "100", "101", "001", "000", "010" and "011",8 bit value combinations, where the ordering of the bit values in each bit value combination is based on the order of the memory states of the lower, middle and upper physical pages of the memory cell.
In addition, referring to fig. 3B, the threshold voltage distribution area G1 corresponds to the gray code pattern "111"; the threshold voltage distribution region G2 corresponds to gray code pattern "011"; the threshold voltage distribution region G3 corresponds to Gray code pattern "001"; the threshold voltage distribution region G4 corresponds to Gray code pattern "000"; the threshold voltage distribution region G5 corresponds to Gray code pattern "010"; the threshold voltage distribution region G6 corresponds to Gray code pattern "110"; the threshold voltage distribution region G7 corresponds to Gray code pattern "100"; the threshold voltage distribution region G8 corresponds to the gray code pattern "101". In addition, in the present embodiment, if the gray code pattern corresponding to the memory state of a memory cell is "011", the memory cell can be regarded as belonging to the threshold voltage distribution area G8, or the threshold voltage distribution of the memory cell can be regarded as belonging to the threshold voltage distribution area G2.
In this embodiment, the threshold voltage distribution of the physical page of the plurality of memory cells of the word line may deviate from the predetermined threshold voltage distribution. Due to the shift of the threshold voltage distribution, the preset transition read voltage, which originally corresponds to the preset threshold voltages of the plurality of physical pages, is no longer suitable for distinguishing the storage states of the corresponding physical pages. In other words, in this case, the plurality of read bit values (also referred to as read codewords) stored in the plurality of memory cells of the physical page that are originally read and identified are distorted, and the corresponding decoding operation is failed. At this time, the processor 211 performs a read retry operation to read the physical page using an adjusted read voltage different from a preset read voltage and obtain a plurality of read bit values (also referred to as an adjusted codeword) of the physical page, and tries to decode the adjusted codeword. If the decoding operation corresponding to the adjustment codeword fails (e.g., the decoding operation corresponding to the adjustment codeword), the read assist circuit 215 may identify soft information and corresponding confidence levels of the plurality of memory cells of the physical page using the read codeword and the adjustment codeword and a plurality of syndromes corresponding to the read codeword and the adjustment codeword, and the error checking and correcting circuit 214 may perform a predetermined decoding operation (low density parity check code decoding operation) through the respective confidence levels and soft information of the plurality of memory cells. The following will explain in detail with reference to fig. 2.
Fig. 2 is a flowchart of a data reading method according to an embodiment of the present invention. Referring to fig. 2, in step S21, the processor 211 selects a target entity page of a target word line to perform a read operation on a target codeword stored in the target entity page. Specifically, the selection manner and the timing point of the target entity page are already described in detail, which is not repeated here. In an embodiment, processor 211 may look up the physical address corresponding to the logical address indicated by the read instruction received from host system 10 and select the target physical page corresponding to the physical address to perform the read operation.
Next, in step S22, the read assist circuit unit 215 (or the soft information management circuit 2151) reads the target entity page using a preset read voltage corresponding to the target entity page to obtain a read codeword corresponding to the target entity page, and the error checking and correcting circuit 214 performs a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read codeword is stored in a codeword buffer and a first one of the plurality of read codeword syndromes is stored in a syndrome buffer.
For example, assuming that the target physical page is a lower physical page, as shown in fig. 3A, the read assist circuit unit 215 (or the soft information management circuit 2151) may read the lower physical page by using the preset read voltage V (1) 4 corresponding to the lower physical page to obtain the storage states of the lower physical pages of the target storage units of the target word line. The plurality of storage states of the lower physical page of the plurality of target storage units may constitute a read codeword corresponding to the lower physical page.
Then, the error checking and correcting circuit 214 performs a predetermined decoding operation on the read codeword. As described above, the error checking and correction circuit 214 performs a plurality of iterative decoding operations on the read codeword, and obtains a plurality of syndromes (also referred to as read codeword syndromes) corresponding to the plurality of iterative decoding operations. The total number of the plurality of iterative decoding operations does not exceed an iteration number threshold. The error checking and correction circuit 214 may sequentially obtain the plurality of read codeword syndromes according to an execution order of the plurality of iterative decoding operations. The read assist circuit unit 215 (or soft information management circuit 2151) may store the read codeword syndrome (the first of the plurality of read codeword syndromes) that is the first in order among the plurality of read codeword syndromes to a syndrome buffer, and store the read codeword to a codeword buffer. The first one of the plurality of read codeword syndromes is a syndrome obtained after performing a first iterative decoding operation on the read codeword. The present invention is not limited to the allocation positions of the syndrome buffer and the codeword buffer. For example, in an embodiment, the syndrome buffer or the codeword buffer may be configured in a buffer memory of the read assist circuit unit 215.
In addition, as described above, the error checking and correcting circuit 214 may determine whether the preset decoding operation corresponding to the read codeword is successful according to whether the plurality of bit values of the last one of the plurality of read codeword syndromes (the last one of the plurality of read codeword syndromes is ordered) are all zero.
In step S23, in response to determining that the bit values of the last one of the plurality of read codeword syndromes are not all zero, the processor 211 re-reads the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, and the error checking and correcting circuit 214 performs the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the first adjusted codeword is stored in the codeword buffer and the first one of the plurality of first adjusted codeword syndromes is stored in the syndrome buffer.
Specifically, in response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are not all zero (i.e., determining that the preset decoding operation corresponding to the read codeword failed/unsuccessful), the processor 211 performs a read retry operation corresponding to the target entity page. In the read retry operation, the processor 211 reads the target entity page again using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page.
Then, the error checking and correcting circuit 214 performs a predetermined decoding operation on the first adjusted codeword. As described above, the error checking and correction circuit 214 performs a plurality of iterative decoding operations on the first adjustment codeword, and obtains a plurality of syndromes (also referred to as first adjustment codeword syndromes) corresponding to the plurality of iterative decoding operations. The error checking and correcting circuit 214 may sequentially obtain the first adjustment codeword syndromes according to the execution order of the iterative decoding operations. The read assist circuit unit 215 (or soft information management circuit 2151) may store a first ordered syndrome of the plurality of first adjusted codeword syndromes (a first one of the plurality of first adjusted codeword syndromes) to a syndrome buffer and store the first adjusted codeword to a codeword buffer. The first one of the plurality of first adjustment codeword syndromes is a syndrome obtained after performing a first iterative decoding operation on the first adjustment codeword. At this time, the syndrome buffer stores the first adjustment codeword syndrome corresponding to the first adjustment codeword and the read codeword syndrome corresponding to the read codeword; the codeword buffer stores the first adjustment codeword and the read codeword. It should be noted that, in the present embodiment, the codeword buffer is used to store the original codeword (codeword that has not undergone the decoding operation) read out for each read voltage, and the syndrome buffer is used to store a plurality of syndromes obtained by performing the first iterative decoding operation on a plurality of original codewords in the codeword buffer.
The error checking and correcting circuit 214 may determine whether the preset decoding operation corresponding to the first adjustment codeword is successful according to whether the plurality of bit values of the last one of the plurality of first adjustment codeword syndromes (the last first adjustment codeword syndrome ordered among the plurality of first adjustment codeword syndromes) are all zero. If both are zero, the error checking and correcting circuit 214 determines that the preset decoding operation corresponding to the first adjustment codeword is successful; if not, the error checking and correcting circuit 214 determines that the predetermined decoding operation corresponding to the first codeword is unsuccessful (failure) (also indicated that the read retry operation fails), and proceeds to step S24.
It is worth mentioning that, in response to determining that the plurality of bit values of the last one of the plurality of read codeword syndromes are all zero, the error checking and correction circuit 214 identifies the decoded read codeword corresponding to the last one of the plurality of read codeword syndromes as the valid codeword for the read operation and completes the read operation. Further, in response to determining that the plurality of bit values of the last of the plurality of first adjustment codeword syndromes are all zero, the error checking and correction circuit 214 identifies a decoded first adjustment codeword corresponding to the last of the plurality of first adjustment codeword syndromes as the valid codeword corresponding to the read operation and completes the read operation.
In step S24, in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero, the read auxiliary circuit unit 215 (or soft information management circuit 2151) generates soft information for each of the plurality of target storage units according to the plurality of codewords in the codeword buffer corresponding to the read operation.
Specifically, in the present embodiment, the soft information management circuit 2151 identifies the smallest syndrome of the total number of syndromes having the smallest bit value "1" among the plurality of syndromes of the syndrome buffer.
Next, the soft information management circuit 2151 selects a codeword corresponding to the minimum syndrome among the plurality of codewords of the codeword buffer to set the selected codeword as the hard bit codeword corresponding to the plurality of target storage units, and sets the remaining codewords, which are not selected among the plurality of codewords of the codeword buffer, as the soft bit codeword corresponding to the plurality of target storage units.
Finally, soft information management circuit 2151 uses the hard bit codeword and the soft bit codeword to compose the soft information for each of the plurality of target memory locations.
FIG. 4A is a diagram illustrating the size versus relationship of the plurality of syndromes according to the first falling aspect of the present invention. FIG. 6A is a diagram illustrating a plurality of preset confidence levels of a target physical page with 1 transition read voltage and a set corresponding to a first falling pattern according to an embodiment of the present invention.
Referring to fig. 4A and fig. 6A, assume that the target physical page is a lower physical page, and the read auxiliary circuit unit 215 first uses the preset read voltage V (1) 4 corresponding to the lower physical page to read the lower physical page, and obtains the read codeword and the corresponding read codeword syndrome 411; and the lower physical page is read using the first adjusted read voltage V (2) 4 corresponding to the preset read voltage V (1) 4, and the first adjusted codeword and the corresponding first adjusted codeword syndrome 412 are obtained. The read codeword syndrome 411 and the first adjustment codeword syndrome 412 are stored in a syndrome buffer.
In addition, the soft information management circuit 2151 may identify that the first number of bit values (total number of bit values "1") of the read codeword syndrome 411 is "SN1", and that the first number of bit values of the first adjustment codeword syndrome 412 is "SN2" (SN 2> SN 1).
Since the first bit value number of the read codeword syndrome 411 is the smallest, the soft information management circuit 2151 may select/identify the read codeword syndrome 411 as the smallest syndrome and set the read codeword corresponding to the read codeword syndrome 411 as a hard bit codeword. Next, the soft information management circuit 2151 sets the remaining syndromes in the syndrome buffer, i.e., the first adjustment codeword syndrome 412, to the soft bit codeword.
As shown in fig. 6A, the soft information management circuit 2151 may combine the hard bit codeword with the soft bit codeword to read a plurality of soft information from a plurality of target memory locations of the target physical page. That is, for a certain memory cell, the soft information management circuit 2151 may identify a read bit value corresponding to the memory cell in the hard bit codeword and identify the read bit value as the hard bit value of the memory cell; the read bit value corresponding to the memory cell is identified in the soft bit codeword and the soft bit value of the memory cell is identified. Next, the soft information management circuit 2151 combines the hard bit values with the soft bit values to obtain soft information for the memory cells. It should be noted that, in an embodiment, if there are a plurality of soft bit code words, the soft information management circuit 2151 orders the soft bit code words according to the absolute voltage difference between the read voltage corresponding to the soft bit code words and the read voltage of the hard bit code words from small to large, and sequentially selects the plurality of soft bit code words to combine soft information (e.g., the soft bit code word corresponding to the minimum absolute voltage difference is selected to combine soft information).
In this embodiment, the soft information management circuit 2151 can identify the voltage relative relationship between the threshold voltage distribution area to which the target memory cell belongs and the converted read voltage of the target physical page through the soft information of the target memory cell.
For example, assume that the soft information management circuit 2151 is to identify the threshold voltage distribution region to which the first target memory cell (soft information thereof is "1 0") belongs and the voltage relative relationship between the first target memory cell and the converted read voltage V (1) 4 of the lower physical page. The soft information management circuit 2151 may identify that the first target memory cell belongs to the threshold voltage distribution region R61 between the read voltage V (1) 4 and the read voltage V (2) 4 by identifying the soft information "1 0" of the first target memory cell. For another example, another target memory cell with soft information "1 1" is identified as belonging to the threshold voltage distribution region R62; yet another target memory cell having soft information "0 0" is identified as belonging to the threshold voltage distribution region R63. In this embodiment, since the read bit value stored in the memory cell closer to the converted read voltage has a higher probability of misjudgment, the confidence of the memory cell closest to the converted read voltage is the lowest, and the confidence of the memory cell farthest from the converted read voltage is the highest. In the above-mentioned threshold voltage distribution regions R61 to R63, the first target memory cell belonging to the threshold voltage distribution R61 is closer to the switching read voltage V (1) 4 than the other target memory cell belonging to the threshold voltage distribution region R62. Accordingly, the confidence of the first target memory cell (i.e., the memory cell having soft information "1 0") belonging to the threshold voltage distribution R61 is set to a small absolute value (e.g., |a|); the confidence of another target memory cell (i.e., a memory cell with soft information "1 1") belonging to the threshold voltage distribution R62 is set to a larger absolute value (e.g., |b|). On the other hand, since still another target memory cell having soft information "0 0" belongs to the threshold voltage distribution region R63, the range is from the voltage value of the conversion read voltage V (1) 4 to the voltage value of infinity. The absolute value of the confidence of the soft information "0 0" (e.g., |x|) may be set according to one range interval. The maximum value of the range interval is |B| and the minimum value is |A|. In one embodiment, X may be set to be the average of A and B. It should be noted that since the soft information pattern "0 1" does not belong to the corresponding converted read voltage V (1) 4. So the soft information pattern "0 1" is not recorded in the corresponding confidence table, or the predetermined confidence level corresponding to the soft information pattern "0 1" can be set to "0" directly.
After obtaining the soft information of each of the plurality of target storage units, in step S25, the reading assisting circuit unit 215 (or the confidence table managing circuit 2152) may identify a target confidence table corresponding to the magnitude relation from a plurality of confidence tables corresponding to the target entity page according to the magnitude relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the magnitude relation of a plurality of aspects, and the plurality of confidence tables respectively have a plurality of preset confidence degrees respectively corresponding to the plurality of soft information aspects.
Specifically, in the present embodiment, the confidence table management circuit 2152 (or the soft information management circuit 2151) can determine whether the size relative relationship between the plurality of syndromes in the syndrome buffer is one of a plurality of aspects. The plurality of aspects may be further classified according to a total number of the plurality of syndromes in the syndrome buffer. If the total number of the plurality of syndromes is 2 (e.g., the read codeword syndrome corresponding to the read codeword and the first adjusted codeword syndrome corresponding to the first adjusted codeword), the plurality of aspects of the magnitude-versus-magnitude relationship between the 2 syndromes includes a first falling aspect, a first rising aspect, and a horizontal aspect, wherein the 2 syndromes can be classified as a left syndrome corresponding to the codeword read via a lower read voltage and a right syndrome corresponding to the codeword read via a higher read voltage. In more detail, if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude relation is identified as the first falling pattern, wherein the right syndrome is identified as the smallest syndrome; if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the left syndrome, the magnitude-relative relationship is identified as the first ascending pattern, wherein the left syndrome is identified as the smallest syndrome; if the difference between the total number of bit values "1" of the right syndrome and the total number of bit values "1" of the left syndrome is less than a syndrome difference threshold, and the total number of bit values "1" of the right syndrome and the total number of bit values "1" of the left syndrome are both less than a syndrome threshold, the magnitude relation is identified as the horizontal aspect, wherein the total number of syndromes having smaller bit values "1" is identified as the smallest syndrome. Furthermore, the confidence table management circuit 2152 may design a plurality of confidence tables corresponding to the first falling pattern, the first rising pattern, and the horizontal pattern, respectively.
On the other hand, if the total number of the plurality of syndromes is 3 (e.g., a read codeword syndrome corresponding to a read codeword, a first adjusted codeword syndrome corresponding to a first adjusted codeword, and a second adjusted codeword syndrome corresponding to a second adjusted codeword), the plurality of aspects of the magnitude-versus-relationship between the 3 syndromes includes a second falling aspect, a second rising aspect, and a hooking aspect, wherein the 3 syndromes can be classified into a left syndrome corresponding to a codeword read via a lower read voltage, a right syndrome corresponding to a codeword read via a higher read voltage, and an intermediate syndrome corresponding to a codeword read via an intermediate read voltage. In more detail, if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the middle syndrome and the total number of bit values "1" of the middle syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude relation is identified as the second declining pattern, wherein the right syndrome is identified as the smallest syndrome; if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the intermediate syndrome and the total number of bit values "1" of the intermediate syndrome is greater than the total number of bit values "1" of the left syndrome, the magnitude-versus-relationship is identified as the second ascending pattern, wherein the left syndrome is identified as the smallest syndrome; if the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the left syndrome and the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the right syndrome, the magnitude-versus-relationship is identified as the tick state-like, wherein the intermediate syndrome is identified as the minimum syndrome. In addition, the confidence table management circuit 2152 may design a plurality of confidence tables corresponding to the second falling pattern, the second rising pattern, and the hooking pattern, respectively. The following describes the manner of determining/identifying the plurality of aspects with reference to a plurality of drawings.
Referring to fig. 4A, as shown in example < EX41>, assuming that the target physical page (e.g., the lower physical page) has 1 converted read voltage (e.g., the preset read voltage V (1) 4), the soft information management circuit 2151 performs two reads (using the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 corresponding to the left adjustment generated by the preset read voltage V (1) 4), respectively), and obtains the read codeword and the read codeword syndrome corresponding to the preset read voltage V (1) 4 and the first adjusted codeword syndrome corresponding to the first adjusted read voltage V (2) 4 through the corresponding preset decoding operation. In addition, the total number of bit values "1" (first bit value total) of the read codeword syndromes 412 corresponding to the read codeword obtained via the preset read voltage V (1) 4 is "SN2"; the first bit value of the first adjustment codeword syndrome 411 corresponding to the first adjustment codeword obtained via the first adjustment read voltage V (2) 4 is "SN1", where "SN2" is greater than "SN1". Since the sizes of the syndromes 412 and 411 are in a decreasing direction from left to right, the confidence table management circuit 2152 (or the soft information management circuit 2151) determines that the relative relationship between the sizes of the syndromes 411 and 412 is the first decreasing pattern. It should be noted that, since the predetermined read voltage V (1) 4 is closer to the boundary between the two threshold voltage distributions, the corresponding read codeword is more correct (i.e., the total number of the first bit values of the corresponding syndrome is smaller).
Similarly, as shown in example < EX42>, it is assumed that the target physical page (e.g., the lower physical page) has 1 converted read voltage (e.g., the preset read voltage V (1) 4), and the soft information management circuit 2151 performs two reads (using the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 corresponding to the preset read voltage V (1) 4, respectively, which is adjusted to the right). The total number of first bit values of the read codeword syndrome 421 corresponding to the read codeword obtained via the preset read voltage V (1) 4 is "SN1"; the first bit value of the first adjustment codeword syndrome 422 corresponding to the first adjustment codeword obtained via the first adjustment read voltage V (2) 4 is summed to "SN2". Since the sizes of the syndromes 421 and 422 are in a decreasing direction from left to right, the confidence table management circuit 2152 (or the soft information management circuit 2151) determines that the relative relationship between the sizes of the syndromes 421 and 422 is the first decreasing pattern. It should be noted that, in one embodiment, the confidence table management circuit 2152 (or the soft information management circuit 2151) determines whether the absolute difference between the "SN2" and the "SN1" is greater than a difference threshold. If the difference threshold is greater than the threshold, the confidence level management circuit 2152 (or the soft information management circuit 2151) further determines whether the first rising pattern or the first falling pattern is present.
FIG. 4B is a diagram illustrating the size versus relationship of the plurality of syndromes according to the first rising aspect according to an embodiment of the present invention.
Referring to fig. 4B, as shown in example < EX43>, it is assumed that the soft information management circuit 2151 uses the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 to read the target physical page twice. In addition, the first bit value of the read codeword syndrome 431 corresponding to the read codeword obtained via the preset read voltage V (1) 4 is "SN2"; the first bit values of the first adjustment codeword syndrome 432 corresponding to the first adjustment codeword obtained via the first adjustment read voltage V (2) 4 are summed to "SN1", where "SN2" is greater than "SN1". Since the sizes of the syndromes 432 and 431 are in the upward direction in the left-to-right direction, the confidence table management circuit 2152 (or the soft information management circuit 2151) determines that the relative relationship between the sizes of the syndromes 411 and 412 is the first upward pattern. Similarly, example < EX44> is another example of the first rising pattern. The total number of first bit values "SN1" of the read codeword syndrome 441 corresponding to the preset read voltage V (1) 4 is smaller than the total number of first bit values "SN2" of the first adjustment codeword syndrome 442 corresponding to the first adjustment read voltage V (2) 4, and the sizes of the read codeword syndrome 441 and the first adjustment codeword syndrome 442 are in an ascending trend. The read codeword syndrome 441 and the first adjust codeword syndrome 442 are identified as the first rising pattern.
It should be noted that, in an embodiment, if the absolute difference between the total numbers of the first bit values of the plurality of syndromes in the syndrome buffer is not greater than the difference threshold and is smaller than the syndrome threshold, the confidence table management circuit 2152 (or the soft information management circuit 2151) determines that the plurality of syndromes are in a horizontal state.
FIG. 4C is a diagram illustrating the relative sizes of the syndromes according to the embodiment of the invention. Referring to fig. 4C, as shown in example < EX45>, assuming that the target physical page (e.g., the lower physical page) has 1 converted read voltage (e.g., the preset read voltage V (1) 4), the soft information management circuit 2151 uses the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 to read the target physical page twice, and obtains the read codeword and the read codeword syndrome corresponding to the preset read voltage V (1) 4 and the first adjusted codeword syndrome corresponding to the first adjusted read voltage V (2) 4 through the corresponding preset decoding operation, respectively. In addition, the total number of first bit values of the read codeword syndrome 451 corresponding to the preset read voltage V (1) 4 is "SN3"; the first bit value of the first adjusted codeword syndrome 452 corresponding to the first adjusted read voltage V (2) 4 is "SN1". In this example, the confidence table management circuit 2152 identifies that "SN3" is greater than "SN1," that the absolute difference between "SN3" and "SN1" is not greater than the difference threshold, and that "SN3" and "SN1" are both less than the syndrome threshold. At this time, the confidence table management circuit 2152 determines that the magnitude relationship between the read codeword syndrome 451 and the first adjusted codeword syndrome 452 is horizontal (the trend of rising or falling is not obvious). It should be noted that, in this example, the confidence table management circuit 2152 predicts that the predetermined read voltage V (1) 4 corresponding to the read codeword syndrome 451 and the first adjusted read voltage V (1) 2 corresponding to the first adjusted codeword syndrome 452 are both close to the boundary between the two threshold voltage distributions, and the confidence table management circuit 2152 predicts that the optimal transition read voltage should be set between the predetermined read voltage V (1) 4 and the first adjusted read voltage V (1) 2.
Similarly, as shown in example < EX46>, the absolute difference between the total number of first bit values "SN3" of the read codeword syndrome 461 corresponding to the preset read voltage V (1) 4 and the total number of first bit values "SN1" of the first adjustment codeword syndrome 462 corresponding to the first adjustment read voltage V (2) 4 is not greater than the difference threshold, and the total number of first bit values "SN1" and "SN3" are smaller than the syndrome threshold. The read codeword syndrome 461 and the first adjustment codeword syndrome 462 are identified as horizontal.
It should be noted that, for the plurality of syndromes of the horizontal pattern, since the corresponding plurality of read voltages are very close to the boundary of the threshold voltage distribution, the confidence table management circuit 2152 considers that the read bit values of the memory cells corresponding to the threshold voltage distribution region between the plurality of read voltages are unreliable, and the confidence table management circuit 2152 sets the preset confidence of the soft information corresponding to the threshold voltage distribution region to a specific value (please refer to the following description of fig. 8A).
The above examples merely illustrate aspects of the relative relationship of the sizes of the two syndromes corresponding to the two read voltages. In addition, a plurality of aspects of the size-relative relationship of the three syndromes of the three read voltages will be described with reference to fig. 5A to 5C.
In an embodiment, the step S24 may further include the following steps: in response to determining that the last one of the plurality of first adjusted codeword syndromes is not zero, the read auxiliary circuit unit 215 (or the soft information management circuit 2151) generates a second adjusted read voltage according to the predetermined read voltage, the first adjusted read voltage and the corresponding plurality of syndromes. The soft information management circuit 2151 may calculate a voltage difference obtained by subtracting the preset read voltage from the first adjusted read voltage, wherein the read assist circuit unit adds the voltage difference to the first adjusted read voltage to generate the second adjusted read voltage in response to a total number of bits of the syndrome corresponding to the first adjusted read voltage being greater than a total number of bits of the syndrome corresponding to the preset read voltage being "1" in the syndrome buffer, and the read assist circuit unit subtracts the voltage difference from the preset read voltage to generate the second adjusted read voltage in response to a total number of bits of the syndrome corresponding to the first adjusted read voltage being greater than a total number of bits of the syndrome corresponding to the preset read voltage being "1". In an embodiment, in response to the absolute difference between the total number of bits "1" of the syndrome corresponding to the first adjusted read voltage and the total number of bits "1" of the syndrome corresponding to the preset read voltage in the syndrome buffer being less than a difference threshold, and the total number of bits "1" of the syndrome corresponding to the first adjusted read voltage and the total number of bits "1" of the syndrome corresponding to the preset read voltage in the syndrome buffer being less than a syndrome threshold, the average of the preset read voltage and the first adjusted read voltage is calculated as the second adjusted read voltage (because the preset read voltage and the first adjusted read voltage may have been close to the optimal converted read voltage of the target page). The following description is made with reference to fig. 5A.
FIG. 5A is a diagram illustrating the size versus relationship of the plurality of syndromes according to the second falling aspect of the present invention. In more detail, referring to fig. 5A, in example < EX51>, it is assumed that the soft information management circuit 2151 has used the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 to read the target physical page, and the corresponding syndromes 513 and 512 are obtained. In response to the bit values of the syndrome 513 being non-zero and the total number of first bit values corresponding to the syndrome 513 in the syndrome buffer being greater than the total number of first bit values of the syndrome 511, the soft information management circuit 2151 determines that adjusting the preset read voltage V (1) 4 to the left is a codeword (i.e., a first adjusted codeword) whose first adjusted read voltage is worse (the total number of first bit values is greater), and the soft information management circuit 2151 adjusts the preset read voltage V (1) 4 to the right. That is, the soft information management circuit 2151 adds the preset read voltage V (1) 4 to the voltage difference between the preset read voltage V (1) 4 and the first adjusted read voltage V (2) 4 to generate the second adjusted read voltage V (3) 4. In other words, the soft information management circuit 2151 determines the voltage value of the second adjusted read voltage according to the voltage magnitude relation between the preset read voltage and the first adjusted read voltage and the magnitude relation between the syndromes corresponding to the preset read voltage and the first adjusted read voltage. Briefly, if the adjusted read voltage obtained by using one voltage adjustment direction would result in a worse decoding result (corresponding syndrome has a larger total number of first bits), the soft information management circuit 2151 would speculate that the adjusted read voltage generated in the opposite direction should obtain a better result (corresponding syndrome has a smaller total number of first bits) (as shown in example < EX51> of fig. 5A); if the adjusted read voltage obtained by using one voltage adjustment direction results in a better decoding result (corresponding syndrome has a smaller total number of first bits), the soft information management circuit 2151 may infer that the adjusted read voltage generated by continuing to the same adjustment direction should obtain a better result (corresponding syndrome has a smaller total number of first bits) (e.g., as shown in example < EX52> of fig. 5A).
After obtaining the second adjusted read voltage, the soft information management circuit 2151 reads the target physical page using the second adjusted read voltage to obtain a second adjusted codeword corresponding to the target physical page. That is, the soft information management circuit 2151 also performs another read retry operation (using the second adjusted read voltage) to attempt to obtain a valid codeword for the target physical page. The error checking and correcting circuit 214 performs the preset decoding operation on the second adjustment codeword to obtain a plurality of second adjustment codeword syndromes corresponding to the second adjustment codeword. The soft information management circuit 2151 stores the second adjusted codeword in the codeword buffer and stores the first of the plurality of second adjusted codeword syndromes in the syndrome buffer. It should be noted that, at this time, the syndrome buffer stores three syndromes, namely, the read codeword syndrome, the first adjustment codeword syndrome and the second adjustment codeword syndrome.
In response to determining that the last one of the plurality of second adjustment codeword syndromes is not all zero (i.e., the second adjustment codeword obtained in response to the current read retry operation fails in decoding), the soft information management circuit 2151 generates the soft information for each of the plurality of target storage units according to all codewords in the codeword buffer that correspond to the read operation; in response to determining that the plurality of bit values of the last of the plurality of second adjustment codeword syndromes are all zero, the error checking and correction circuit 214 identifies a decoded first adjustment codeword corresponding to the last of the plurality of first adjustment codeword syndromes as the valid codeword corresponding to the read operation (or read retry operation), and the processor completes the read operation.
The following describes a manner of determining/identifying a plurality of aspects corresponding to the size-relative relationship of the three syndromes with reference to a plurality of drawings.
Referring to fig. 5A, in example < EX51>, the total number of first bit values "SN2" of the read codeword syndrome 511 corresponding to the preset read voltage V (1) 4 is smaller than the total number of first bit values "SN3" of the first adjustment codeword syndrome 512 corresponding to the first adjustment read voltage V (2) 4, and the total number of first bit values "SN1" of the second adjustment codeword syndrome 513 corresponding to the second adjustment read voltage V (3) 4 is smaller than the total number of first bit values "SN2" of the read codeword syndrome 511 corresponding to the preset read voltage V (1) 4. The sizes of the first codeword syndrome 512, the read codeword syndrome 511 and the second codeword syndrome 513 are in a decreasing trend. The size relative relationship between the first adjusted codeword syndrome 512, the read codeword syndrome 511 and the second adjusted codeword syndrome 513 is identified as a second declining pattern.
Similarly, in example < EX52>, the sizes of the read codeword syndrome 521, the first adjusted codeword syndrome 522, and the second adjusted codeword 523 are in a decreasing trend. The size relationship among the read codeword syndrome 521, the first adjusted codeword syndrome 522 and the second adjusted codeword 523 is identified as a second falling pattern.
FIG. 5B is a diagram illustrating the size versus relationship of the plurality of syndromes according to the second rising aspect of the present invention. Referring to fig. 5B, in example < EX53>, the sizes of the second adjusted codeword syndrome 533, the first adjusted codeword syndrome 532, and the read codeword syndrome 531 are in an ascending trend. The second adjusted codeword syndrome 533, the first adjusted codeword syndrome 532, and the read codeword syndrome 531 are identified as second rising patterns. Similarly, in example < EX54>, the sizes of the second modified codeword syndrome 543, the read codeword syndrome 541, and the first modified codeword syndrome 542 are in an upward trend. The size relationship among the second adjusted codeword syndrome 543, the read codeword syndrome 541 and the first adjusted codeword syndrome 542 is identified as a second rising pattern.
FIG. 5C is a diagram illustrating the relative sizes of the plurality of syndromes according to the present invention. Referring to fig. 5C, in example < EX55>, the sizes of the first adjusted codeword syndrome 552, the read codeword syndrome 551 and the second adjusted codeword syndrome 553 are in the form of hooks. That is, the total number of first bit values of the read codeword syndrome 551 in the middle is the smallest. The size relationships among the first adjusted codeword syndrome 552, the read codeword syndrome 551 and the first adjusted codeword syndrome 553 are identified as tick. Similarly, in example < EX56>, the second modified codeword syndrome 563, the read codeword syndrome 561, and the first modified codeword syndrome 562 are sized in a hook. The size relative relationship between the second codeword adjustment syndrome 563, the read codeword syndrome 561 and the first codeword adjustment syndrome 562 is identified as a hook state. It should be noted that in the above-described embodiment, the syndrome that is the smallest syndrome is drawn in black, and the codeword corresponding to the smallest syndrome is set as the hard bit codeword.
In this embodiment, the confidence tables corresponding to the target entity page correspond to different aspects. Each confidence table has a plurality of preset confidence levels and a corresponding plurality of soft information patterns. In this embodiment, the absolute values of the preset confidence levels of a confidence table are set according to the corresponding pattern of the confidence table (i.e., the target pattern of the size-relative relationship among the syndromes obtained by reading the target entity page). The plurality of soft information aspects of the confidence table are obtained according to reading the target physical page via the read assist circuit unit 215 (or confidence table management circuit 2152) sequentially using one or more converted read voltages corresponding to the target aspect and the target physical page and one or more adjusted read voltages corresponding to the one or more converted read voltages. The absolute value of one or more preset confidence levels corresponding to one or more soft information aspects of the one or more converted read voltages is set to a smaller value as the soft information aspects are closer to each other, wherein the absolute value of the preset confidence level corresponding to the soft information aspect between one of the one or more converted read voltages and the corresponding adjusted read voltage is set to a minimum value. The positive and negative of the plurality of preset confidence levels are set according to the hard bit value in the corresponding soft information pattern, wherein the first preset confidence level is set to be a negative value in response to the hard bit value in the soft information pattern corresponding to one of the plurality of preset confidence levels being "1". In addition, in response to the hard bit value in the soft information pattern corresponding to the preset confidence being "0", the first preset confidence is set to a positive value.
Referring to fig. 6A, for example, assume that a plurality of preset confidence levels of the confidence table of the lower physical page of the first drop pattern are currently set. The read assist circuit unit 215 uses the converted read voltage V (1) 4 (e.g., the preset read voltage) and the adjusted read voltage V (2) 4 corresponding to the lower physical page to read the lower physical page, so as to obtain the soft information pattern shown in fig. 6A. It should be noted that, for the first falling pattern, the codeword corresponding to the converted read voltage V (1) 4 is a hard bit codeword and the codeword corresponding to the adjusted read voltage V (2) 4 is a soft bit codeword. Furthermore, as described above, the absolute value of the preset confidence level corresponding to the soft information pattern "1 0" between the transition read voltage V (1) 4 and the adjustment read voltage V (2) 4 is set to be minimum (e.g., |a|) and set to be negative (because the corresponding hard bit value is "1"). The A| represents the preset confidence of the converted read voltage closest to the boundary of the threshold voltage distribution, for example, |3|'. The absolute value of the preset confidence of the soft information version "1 1" farther from the transition read voltage V (1) 4 is set to a value greater than |a| (e.g., b|) and to a negative value (because the corresponding hard bit value is "1"). B is, for example, "5". However, the memory cells belonging to the soft information pattern "0 0" may be very close to the converted read voltage V (1) 4 or very far from the converted read voltage V (1) 4, and thus, the absolute value of the preset confidence level corresponding to the soft information pattern "0 0" is set to a specific value (e.g., |x|), and the setting range of the specific value is determined according to the preset confidence level of the soft information pattern "1 0" and the preset confidence level of the soft information pattern "1 1". For example, |x| max may be set to |b|, and min may be set to |a|. In addition, the preset confidence level corresponding to the soft information pattern "0 0" is set to a positive value (because the corresponding hard bit value is "0"). It should be noted that the plurality of soft information aspects "1 1", "1 0", and "0 0" may be considered to correspond to the converted read voltage V (1) 4.
FIG. 6B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a first falling pattern and a target physical page having 2 converted read voltages according to an embodiment of the present invention. Referring to fig. 6B, for example, assume that a plurality of preset confidence levels of a confidence table of a physical page (e.g., a middle physical page) having two converted read voltages of a first falling pattern is currently set. The read assist circuit unit 215 uses the converted read voltage V (1) 2 and the adjusted read voltage V (2) 2 corresponding to the middle physical page to read the middle physical page, and can obtain a plurality of soft information patterns corresponding to the converted read voltage V (1) 2 as shown in fig. 6B; the converted read voltage V (1) 6 and the adjusted read voltage V (2) 6 corresponding to the middle physical page are used to read the middle physical page, so that a plurality of soft information patterns corresponding to the converted read voltage V (1) 6 shown in fig. 6B can be obtained. It should be noted that, due to the first falling pattern, the codeword corresponding to the converted read voltage V (1) 2 is a hard bit codeword and the codeword corresponding to the adjusted read voltage V (2) 4 is a soft bit codeword; the codeword corresponding to the converted read voltage V (1) 6 is a hard bit codeword and the codeword corresponding to the adjusted read voltage V (2) 6 is a soft bit codeword. Furthermore, for the three soft information patterns on the left, the absolute value of the preset confidence level corresponding to the soft information pattern "1 0" between the transition read voltage V (1) 2 and the adjustment read voltage V (2) 2 is set to be the minimum (e.g., |a|) and set to be negative. The absolute value of the preset confidence level of the soft information pattern "1 1" farther from the transition read voltage V (1) 2 is set to a value greater than |a| (e.g., b|) and to a negative value. The absolute value of the preset confidence corresponding to the soft information pattern "0 0" is set to a specific value (e.g., |x|) and is set to a positive value. Similarly, for the three soft information patterns on the right, the absolute value of the preset confidence level corresponding to the soft information pattern "0 1" between the transition read voltage V (1) 6 and the adjustment read voltage V (2) 6 is set to be minimum (e.g., a) and set to be positive. The absolute value of the preset confidence level of the soft information pattern "0 0" farther from the transition read voltage V (1) 6 is set to a value greater than |a| (e.g., b|) and to a positive value. The absolute value of the preset confidence corresponding to the soft information pattern "1 1" is set to a specific value (e.g., |x|) and is set to a negative value.
It should be noted that the two sets of soft information patterns on the left and right sides each have the same soft information pattern (but each have different preset confidence levels). Accordingly, the confidence-table management circuit 2152 is adjusted based on the smaller predetermined confidence level so that the same soft information pattern corresponds to the same predetermined confidence level.
For example, soft information pattern "0 0" in the soft information pattern set corresponding to the transition read voltage V (1) 2 has a preset confidence level "+x", and soft information pattern "0 0" in the soft information pattern set corresponding to the transition read voltage V (1) 6 has a preset confidence level "+b". In this case, the confidence table management circuit 2152 recognizes "+b" as a smaller preset confidence level, and adjusts the preset confidence level of the soft information pattern "0 0" in the soft information pattern group corresponding to the converted read voltage V (1) 2 from the original "+x" to "+b". Similarly, the confidence table management circuit 2152 adjusts the default confidence level of the soft information pattern "1 1" in the soft information pattern group corresponding to the converted read voltage V (1) 6 from the original "—x" to "—b".
FIG. 6C is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a first falling pattern and a target physical page having 3 converted read voltages according to an embodiment of the present invention. Referring to fig. 6C, for a physical page with three converted read voltages (e.g., a middle physical page corresponding to a second read voltage pattern), the confidence table management circuit 2152 adjusts the predetermined confidence levels corresponding to all the same soft information patterns to be consistent. As shown in fig. 6C, the confidence table management circuit 2152 adjusts the preset confidence level of the soft information pattern "0 0" in the soft information pattern group corresponding to the converted read voltage V (1) 2 from original "+x" to "+b"; adjusting the preset confidence level of the soft information pattern "1 1" in the soft information pattern group corresponding to the converted read voltage V (1) 4 from original "-X" to "-B"; the preset confidence level of the soft information pattern "0 0" in the soft information pattern group corresponding to the converted read voltage V (1) 6 is adjusted from original "+x" to "+b".
FIG. 6D is a diagram illustrating a plurality of preset confidence levels for setting the target physical page corresponding to the first falling pattern and having 4 converted read voltages according to an embodiment of the present invention. Referring to fig. 6D, for a physical page with 4 converted read voltages (e.g., an upper physical page corresponding to a first read voltage pattern), the confidence table management circuit 2152 adjusts a plurality of predetermined confidences corresponding to all the same soft information patterns to be consistent. As shown in fig. 6D, the confidence table management circuit 2152 adjusts the preset confidence level of the soft information pattern "0 0" in the soft information pattern group corresponding to the converted read voltage V (1) 1 from original "+x" to "+b"; adjusting the preset confidence level of the soft information pattern "1 1" in the soft information pattern group corresponding to the converted read voltage V (1) 3 from original "-X" to "-B"; adjusting the preset confidence level of the soft information pattern "0 0" in the soft information pattern group corresponding to the converted read voltage V (1) 5 from original "+x" to "+b"; the preset confidence level of the soft information pattern "1 1" in the soft information pattern group corresponding to the converted read voltage V (1) 7 is adjusted from the original "-X" to the "-B".
Through the above embodiments, the confidence table management circuit 2152 can set the confidence table corresponding to the first falling pattern of each of the plurality of physical pages having different converted read voltages.
FIG. 6E is a diagram illustrating a plurality of confidence tables corresponding to a first drop pattern of a plurality of target entity pages according to one embodiment of the present invention. Referring to fig. 6E, for example, as shown in the table 600, the confidence table management circuit 2152 can generate a plurality of confidence tables corresponding to different physical pages, each of the confidence tables having a plurality of predetermined confidence levels and a plurality of soft information patterns of corresponding memory cells. Thereafter, the confidence-table management circuit 2152 may look up the confidence level of the memory location that matches the particular soft information pattern through the plurality of confidence tables. As described in step S26 of fig. 2, the respective confidence levels of the plurality of target storage units are searched from the target confidence table according to the plurality of soft information of the plurality of target storage units.
Specifically, for the first soft information of the first target storage unit of the plurality of target storage units, the read assist circuit unit 215 (or the confidence table management circuit 2152) searches for a first soft information pattern corresponding to the first soft information from the plurality of soft information patterns of the target confidence table according to the first soft information, and a first preset confidence corresponding to the first soft information pattern. The confidence table management circuit 2152 identifies the first preset confidence level as a first confidence level of the first target storage unit corresponding to the target entity page.
For example, assume that the target physical page has 2 transition read voltages and the first soft information of the first target memory cell is "1 0". The confidence table management circuit 2152 identifies the preset confidence level corresponding to the soft information pattern corresponding to "1 0" as "-a" and identifies "-a" as the confidence level of the first target storage unit.
In addition, in response to the first soft information not conforming to one of the plurality of soft information aspects of the target confidence table, the read assist circuit unit sets the first preset confidence level corresponding to the first soft information to a preset value.
For example, assume that the target physical page has 1 transition read voltage and the first soft information of the first target memory cell is "0 1". The confidence-table managing circuit 2152 recognizes that the preset confidence level corresponding to the soft information pattern corresponding to "0 1" is "Null" (because the confidence-table managing circuit 2152 does not set the preset confidence level corresponding to the soft information pattern "0 1" in the confidence table, as shown in fig. 6A, the soft information pattern "0 1" does not exist), and the confidence-table managing circuit 2152 sets the confidence level of the first target storage unit to a preset value. In one embodiment, the preset value may be "0". In one embodiment, in the process of setting the plurality of preset confidence levels of the confidence table, after setting the plurality of soft information patterns corresponding to all the read voltages and the plurality of preset confidence levels corresponding to the plurality of soft information patterns, the confidence table management circuit 2152 may directly set the preset confidence level of each of the other one or more soft information patterns (e.g., the first soft information pattern "0 1" in the above example) that are not set as the preset value in the corresponding confidence table.
FIG. 7A is a diagram illustrating a plurality of preset confidence levels of a target physical page with 1 transition read voltage and a set corresponding to a first rising pattern according to an embodiment of the present invention. Referring to fig. 7A, for example, assume that a plurality of preset confidence levels of a confidence table of a lower physical page (e.g., a physical page having 1 transition read voltage) of a first rising pattern is currently set. The read assist circuit unit 215 uses the converted read voltage V (1) 4 and the adjusted read voltage V (2) 4 corresponding to the lower physical page to read the lower physical page, so as to obtain the soft information pattern shown in fig. 7A. It should be noted that, since the first rising pattern is the codeword corresponding to the converted read voltage V (1) 4 is a hard bit codeword and the codeword corresponding to the adjusted read voltage V (2) 4 is a soft bit codeword. Furthermore, as described above, the absolute value of the preset confidence level corresponding to the soft information pattern "0 1" between the transition read voltage V (1) 4 and the adjustment read voltage V (2) 4 is set to be minimum (e.g., |a|) and to be positive (because the corresponding hard bit value is "0"). The absolute value of the preset confidence of the soft information version "0 0" farther from the transition read voltage V (1) 4 is set to a value greater than |a| (e.g., b|), and to a positive value (because the corresponding hard bit value is "1"). However, the memory cells belonging to the soft information pattern "1 1" may be very close to the converted read voltage V (1) 4 or very far from the converted read voltage V (1) 4, and thus, the absolute value of the preset confidence level corresponding to the soft information pattern "0 0" is set to a specific value (e.g., |x|), and the setting range of the specific value is determined according to the preset confidence level of the soft information pattern "0 1" and the preset confidence level of the soft information pattern "0 0". For example, |x| max may be set to |b|, and min may be set to |a|. In addition, the preset confidence level corresponding to the soft information pattern "1 1" is set to a negative value (because the corresponding hard bit value is "1"). It should be noted that the plurality of soft information aspects "1 1", "0 1", and "0 0" may be considered to correspond to the converted read voltage V (1) 4.
FIG. 7B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to the first rising pattern and a target physical page having 2 transition read voltages according to an embodiment of the present invention. Referring to FIG. 7B, similar to the above description, the soft information management circuit 2151 sets a plurality of soft information patterns corresponding to the transition read voltage V (1) 2; and a plurality of soft information patterns corresponding to the converted read voltage V (1) 6. In addition, in order to make the preset confidence degrees corresponding to the same soft information pattern the same, the final preset confidence degrees are set as shown in fig. 7B. The process of setting the confidence table for the first rising pattern of the physical page with more than 2 converted read voltages is similar to the process described in fig. 6B to 6D, and is not repeated here.
FIG. 7C is a diagram illustrating a plurality of confidence tables corresponding to a first rising pattern of a plurality of target entity pages according to an embodiment of the invention. Referring to fig. 7C, as shown in the table 700, the confidence table management circuit 2152 can generate a plurality of confidence tables corresponding to different physical pages of the first rising pattern, each confidence table having a plurality of preset confidence levels and a plurality of soft information patterns of corresponding memory cells.
FIG. 8A is a diagram illustrating a set corresponding horizontal pattern and a plurality of predetermined confidence levels for a target physical page with 1 transition read voltage according to an embodiment of the present invention. Referring to fig. 8A, for example, assume that a plurality of preset confidence levels of a confidence table of a lower physical page (e.g., a physical page having 1 converted read voltage) of a horizontal aspect is currently set. The read assist circuit unit 215 uses the converted read voltage V (1) 4 and the adjusted read voltage V (2) 4 corresponding to the lower physical page to read the lower physical page, so as to obtain the soft information pattern shown in fig. 8A. The codeword corresponding to the adjusted read voltage V (2) 4 having the smaller total number of first bit values is identified as a hard bit codeword, and the codeword corresponding to the converted read voltage V (1) 4 is set as a soft bit codeword. In addition, because of the horizontal aspect, the confidence-table management circuit 2152 considers that the optimal voltage value of the converted read voltage should be between the converted read voltage V (1) 4 and the adjusted read voltage V (2) 4. Accordingly, the predetermined confidence level corresponding to the soft information pattern "0 1" between the converted read voltage V (1) 4 and the adjusted read voltage V (2) 4 would be a more ambiguous value. For example, the absolute value of the predetermined confidence level may be set to a smaller specific value (e.g., Y < X). Y is, for example, "2". The positive and negative values of the predetermined confidence of the soft information pattern "0 1" may be set to positive or negative values depending on the hard bit codeword. In another embodiment, the positive and negative values of the preset confidence of the soft information pattern "0 1" may be set to a positive value (soft bit codeword "1" and preset confidence to a negative value) or a negative value, depending on the soft bit codeword.
However, the soft information pattern "0 0" on the right side of the transition read voltage V (1) 4 and the soft information pattern "1 1" on the left side of the adjustment read voltage V (2) 4 can be both confirmed as soft information patterns farther from the optimal transition read voltage. Accordingly, the absolute value of the preset confidence of soft information aspect "0 0" will be set to a value greater than |a| (e.g., b|), and to a positive value (because the corresponding hard bit value is "0"); the absolute value of the preset confidence of soft information pattern "1 1" will be set to a value greater than |a| (e.g., |b|) and to a negative value (because the corresponding hard bit value is "1").
FIG. 8B is a diagram illustrating a set of corresponding horizontal aspects and a plurality of predetermined confidence levels for a target physical page with 2 converted read voltages according to an embodiment of the present invention. Referring to FIG. 8B, similar to the above description, the soft information management circuit 2151 sets a plurality of soft information patterns corresponding to the transition read voltage V (1) 2; and a plurality of soft information patterns corresponding to the converted read voltage V (1) 6. Next, the confidence table management circuit 2152 sets a plurality of predetermined confidence levels corresponding to the plurality of soft information patterns (see fig. 8B) in the manner described above, and may generate a corresponding plurality of confidence tables (e.g., table 800 shown in fig. 8C). It is worth mentioning that in one embodiment, Y may be set to 0. In another embodiment, Y may be set to a random value between "-X" and "X".
FIG. 9A is a diagram illustrating a plurality of preset confidence levels of the target physical page corresponding to the second falling pattern and having 1 transition read voltage according to an embodiment of the present invention. Referring to fig. 9A, in a manner similar to the first falling pattern of fig. 6A, the soft information management circuit 2151 obtains the soft information pattern shown in fig. 9A. The codeword corresponding to the converted read voltage V (3) 4 is a hard bit codeword and the codeword corresponding to the adjusted read voltage V (1) 4、V(2)4 is a soft bit codeword. It should be noted that in combining the soft information patterns, soft bit codewords closer to the read voltage V (2) 4 of the hard bit codeword V (3) 4 are ordered farther forward in the soft information pattern. Eventually, soft information patterns "111", "110", "100", "000" are produced. Then, the corresponding preset confidence level is set to "-C", "-B", "-A", "+X". Where |c| > b| (because the soft information pattern "111" is identified as being farther from the converted read voltage V (3) 4 than the soft information pattern "110"), the absolute value of the corresponding preset confidence level is greater). Since the range of the threshold voltage distribution of the memory cell corresponding to the soft information pattern "000" is ambiguous (can approach or depart from the switching read voltage V (3) 4), the absolute value of the preset confidence level corresponding to the soft information pattern "000" is set to be |x| and positive. The maximum value of |X| is |C|, the minimum value is |A|, and a manufacturer can set specific numerical values of |X| within the range of |A| to |C| according to requirements.
Fig. 9B to 9D are schematic diagrams showing setting of a plurality of preset confidence levels corresponding to the second falling pattern and the target physical page with 2 converted read voltages according to an embodiment of the present invention. Referring to fig. 9B, the confidence table management circuit 2152 sets the predetermined confidence levels of the soft information patterns "111", "110", "100", "000" corresponding to the converted read voltage V (1) 2 to be "-C", "-B", "-a", "+x"; the predetermined confidence levels of the soft information patterns "000", "001", "011", "111" corresponding to the converted read voltage V (1) 6 are "+c", "+b", "+a", "-X". In this embodiment, the confidence table management circuit 2152 sets the preset confidence level of the read voltage adjacent to the hard bit codeword to the same absolute value (based on the value that has been currently confirmed).
For example, the confidence table management circuit 2152 adjusts the preset confidence level of the soft information pattern "000" adjacent to the read voltage V (3) 2 from "+x" to "—a"; the preset confidence level of the soft information pattern "111" adjacent to the read voltage V (3) 6 is adjusted from "-X" to "+a". Referring to fig. 9C, after adjustment, the predetermined confidence levels of the soft information patterns "111", "110", "100", "000" of the corresponding converted read voltage V (1) 2 are "—c", "-B", "-a"; the predetermined confidence levels of the soft information patterns "000", "001", "011", "111" corresponding to the converted read voltage V (1) 6 are "+c", "+b", "+a". The confidence list management circuit 2152 then adjusts the predetermined confidence levels for the same soft information patterns to be consistent. For example, the soft information pattern "000" (with the preset confidence level "+a") corresponding to the converted read voltage V (1) 2 is the same as the soft information pattern "000" (with the preset confidence level "+c") corresponding to the converted read voltage V (1) 6, but the same soft information pattern "000" does not have the same preset confidence level. In one embodiment, the confidence list management circuit 2152 sets the absolute values of the predetermined confidence levels corresponding to the two identical soft information patterns as an intermediate value, for example, "|b|". In one embodiment, the confidence table management circuit 2152 sets the absolute values of the predetermined confidence levels corresponding to the two identical soft information patterns as an average value, which is the average of the absolute values of the two predetermined confidence levels originally corresponding to the two predetermined confidence levels (e.g., [ (+a) +(+c) ]/2=d).
Referring to fig. 9D, after adjusting the preset confidence level to be consistent, the confidence list management circuit 2152 sets the confidence list of the target physical page with 2 converted read voltages for the second falling pattern. The predetermined confidence levels of the soft information patterns "111", "110", "100", "000" corresponding to the converted read voltages V (1) 2 are "-B" (or "-D"), "-B", "-a", "+b" (or "+d"); the predetermined confidence levels of the soft information patterns "000", "001", "011", "111" corresponding to the converted read voltage V (1) 6 are "+b" (or "+d"), "+b", "+a", "-B" (or "-D"). The resulting multiple confidence tables corresponding to the second drop pattern are shown in table 900 of fig. 9E.
By analogy, the confidence-table management circuit 2152 may generate a plurality of confidence tables corresponding to the second rising pattern, as shown in table 1000 in fig. 10. The detailed setting manner and process can be known from the above embodiments, and are not repeated here.
FIG. 11A is a diagram illustrating setting of a plurality of predetermined confidence levels corresponding to a page of a target entity having 1 transition read voltage according to an embodiment of the present invention. Referring to the left example of fig. 11A, in the example, the soft information management circuit 2151 sequentially uses the converted read voltage V (1) 4, the first adjusted read voltage V (2) 4 (adjusted to the left) and the second adjusted read voltage V (3) 4 (adjusted to the right) to read the target physical page, and obtain the corresponding soft information patterns "111", "101", "001", "000". The confidence-list management circuit 2152 sets the preset confidence levels of the soft information patterns "101", "001" to "-a", "+a"; the preset confidence levels of the soft information patterns "111", "000" are set to "-C", "+c". Referring to the right example of fig. 11A, in the example, the soft information management circuit 2151 sequentially uses the converted read voltage V (1) 4, the first adjusted read voltage V (2) 4 (right adjusted) and the second adjusted read voltage V (3) 4 (left adjusted) to read the target physical page, and obtain the corresponding soft information patterns "111", "110", "010", "000". The confidence list management circuit 2152 sets the preset confidence levels of the soft information patterns "110", "010" to "-a", "+a"; the preset confidence levels of the soft information patterns "111", "000" are set to "-C", "+c".
In one embodiment, if the total number of soft bit codewords is greater than one (e.g., 2 in the example of fig. 9A), the soft information management circuit 2151 performs an XOR operation or an XNOR operation on all soft bit codewords, and takes the obtained first operation result corresponding to the XOR operation or the obtained second operation result corresponding to the XNOR operation as the soft bit value of each of the plurality of target storage units; identifying respective hard bit values of the plurality of target memory locations from the hard bit codeword; and combining the hard bit values of each of the plurality of target storage units with the soft bit values of each of the plurality of target storage units to form the soft information of each of the plurality of target storage units.
FIG. 11B is a diagram illustrating setting of a plurality of preset confidence levels corresponding to a page of a target entity having 1 transition read voltage according to another embodiment of the present invention. For example, referring to fig. 11B, assume that the soft bit codeword corresponding to the read voltage V (2) is "1110", and the soft bit codeword corresponding to the read voltage V (2) is "1000". The soft information management circuit 2151 performs an XOR operation on the soft bit codeword "1110" and the soft bit codeword "1000", and takes the obtained result "0110" as a soft bit value of the soft information. Next, soft information management circuit 2151 combines hard bit value "1100" with soft bit value "0110" to produce soft information "10 11 01 00" (also referred to as soft information pattern "10 11 01 00").
Next, the confidence-table managing circuit 2152 sets the preset confidence levels of the soft information patterns "11", "01" to "-a", "+a"; the preset confidence levels of the soft information patterns "10", "00" are set to "-C", "+c". The generated multiple confidence tables corresponding to the hook state samples are shown in table 1100 of fig. 11C.
Returning again to fig. 2, after obtaining the plurality of confidence levels of the plurality of target storage units, in step S27, the plurality of confidence levels of the plurality of target storage units are substituted for a plurality of log likelihood ratio values corresponding to the plurality of target storage units in the preset decoding operation, and the adjusted preset decoding operation having the substituted plurality of log likelihood ratio values is performed on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and the reading operation is completed.
Specifically, the preset decoding operation originally corresponding to the target word line performs a plurality of iterative decoding operations according to a plurality of log likelihood ratio values corresponding to the plurality of target memory cells and the original soft information corresponding to the plurality of target memory cells. The original soft information is not identical to the soft information generated in step S24. The original soft information is obtained via a plurality of auxiliary read voltage groups corresponding to a plurality of converted read voltages, wherein one auxiliary read voltage group corresponding to one converted read voltage has two auxiliary read voltages in pairs, one auxiliary read voltage is smaller than the converted read voltage by a voltage deviation value, and the other auxiliary read voltage is larger than the converted read voltage by a voltage deviation value.
However, in step S26, the error checking and correcting circuit 214 replaces the log likelihood ratios of the target memory cells with the confidence levels of the target memory cells, replaces the original soft information with the soft information of the target memory cells generated in step S24, and performs the preset decoding operation (also referred to as the adjusted preset decoding operation) on the soft information of the target memory cells again. After completing the adjusted preset decoding operation, the error checking and correction circuit 214 may obtain a valid codeword and complete the read operation corresponding to the target word line. The valid codeword is output upon completion of the read operation and is treated by processor 211 as the read correct target codeword stored in the target physical page.
It should be noted that, in the present embodiment, the read assisting circuit unit 215 uses the gray code count value obtained by reading the verified data to identify the magnitude relation of the plurality of read voltages of the plurality of read voltage groups. The following description will be made with reference to fig. 12A, 12B, and 13.
Fig. 12A is a schematic diagram illustrating calculating offset number differences according to an embodiment of the present invention. In this embodiment, the read assist circuit unit 215 reads the verified data stored in the target word line by using a plurality of read voltages of one read voltage set to obtain the offset number difference of the plurality of read voltage values of the one read voltage set. Referring to fig. 12A, for example, assume that the read assist circuit unit 215 uses the read voltage set V (1) to read verified data. The read voltage set V (1) includes a plurality of read voltages V (1) 1～V(1)7.
Since the read assist circuit unit 215 already knows the preset storage states (preset gray codes) of the verified data of the plurality of memory cells stored in the target word line. Therefore, the read assisting circuit unit 215 can directly recognize the offset direction of the gray code of each memory cell and the corresponding offset amount. For example, if the predetermined gray code of a target memory cell is gray code pattern "111" (G1) and the gray code obtained by the read voltage set V (1) is gray code "110" (G2), the read auxiliary circuit unit 215 can identify that the memory state of the target memory cell on the upper physical page corresponding to the read voltage V (1) is shifted rightward, and the read auxiliary circuit unit 215 can accumulate the number of rightward shifts of the corresponding upper physical page, denoted by C (1) G1G2 (also referred to as a right shift count value). Wherein, "(1)" is used to indicate the corresponding read voltage set V (1), "G1G2" is used to indicate that the storage state of the target memory cell is shifted from the preset gray code pattern G1"111" to the currently read gray code pattern G2"110" (the storage state of the upper physical page of the target memory cell is shifted to the right). In addition, it is understood that the corresponding read voltage V (1) 1 is the read voltage used to distinguish the gray code pattern G1 from the gray code pattern G2 in the read voltage set V (1), and the order of "G1" and "G2" in the "G1G2" may also indicate that the offset direction is from G1 to G2, i.e. to the right.
That is, as shown in the table 1200, the read voltage V (1) 1 corresponds to the gray code pattern G1"111" and the gray code pattern G2"110"; the read voltage V (1) 2 corresponds to Gray code pattern G2"110" and Gray code pattern G3"100"; the read voltage V (1) 3 corresponds to Gray code pattern G3"100" and Gray code pattern G4"101"; the read voltage V (1) 4 corresponds to Gray code pattern G4"101" and Gray code pattern G5"001"; the read voltage V (1) 5 corresponds to Gray code pattern G5"001" and Gray code pattern G6"000"; the read voltage V (1) 6 corresponds to Gray code pattern G6"000" and Gray code pattern G7"010"; the read voltage V (1) 7 corresponds to the gray code pattern G7"010" and the gray code pattern G8"011". The verified data stored in the target word line is read through the plurality of read voltages V (1) 1 to V (1) of the read voltage set V (1), and the read assist circuit unit 215 can record/count the corresponding left offset count value and right offset count value.
For example, as shown in table 1200, for the read voltage V (1) 1, the read assist circuit unit 215 may record a right offset count value C (1) G1G2 and a left offset count value C (1) G2G1 corresponding to the read voltage V (1) 1.
After counting the right offset count value and the left offset count value of all the read voltages corresponding to the read voltage group V (1), the read auxiliary circuit unit 215 may calculate the offset number difference according to the right offset count value and the left offset count value corresponding to each read voltage. Specifically, the offset number difference may be the difference of the right offset count value minus the left offset count value.
For example, referring to fig. 12A, for the read voltage V (1) 1, the read auxiliary circuit unit 215 can calculate the offset number difference D (1) 1 (i.e., D (1) 1＝C(1)G1G2-C(1)G2G1) according to the right offset count value C (1) G1G2 and the left offset count value C (1) G2G1 of the corresponding read voltage V (1) 1.
In this embodiment, the read assist circuit unit 215 further sums the offset differences corresponding to all the read voltages in one read voltage set to obtain a sum of the offset differences corresponding to the one read voltage set. Then, the read assist circuit unit 215 may determine the relative relationship of the voltage magnitudes among the plurality of read voltage sets by using the sum of the offset number differences of the plurality of read voltage sets.
FIG. 12B is a diagram illustrating a statistics table for recording offset number differences and sums of offset number differences according to an embodiment of the present invention. Referring to fig. 12B, as shown in a table 1210, the read assist circuit 215 may record the offset differences of the read voltages of the plurality of read voltage sets V (1) to V (X) and the sum of the offset differences of the plurality of read voltage sets V (1) to V (X) (i.e., the sum of the offset differences SD (1) to SD (X)).
In the present embodiment, if the sum of the first offset numbers of the first read voltage set is smaller than the sum of the second offset numbers of the second read voltage set, the read assisting circuit unit 215 determines that the plurality of read voltages of the first read voltage set are smaller than the second read voltage set (e.g., the read voltage V (1) 1 is smaller than the read voltage V (2) 1). Conversely, if the third offset number difference sum of the third read voltage set is greater than the fourth offset number difference sum of the fourth read voltage set, the read auxiliary circuit unit 215 determines that the plurality of read voltages of the third read voltage set are greater than the fourth read voltage set (e.g., the read voltage V (3) 1 is greater than the read voltage V (4) 1).
It should be noted that one of the plurality of read voltage sets may be a preset read voltage set for reading the target physical page (the preset read voltage of the preset read voltage set is used for reading the target physical page), and another one of the plurality of read voltage sets may be a first adjusted read voltage set for reading the corresponding preset read voltage set of the target physical page (the first adjusted read voltage of the first adjusted read voltage set is used for reading the target physical page again).
FIG. 13 is a schematic diagram illustrating a plurality of read voltage sets sorted by offset number difference sum according to an embodiment of the present invention. Referring to fig. 13, the read assist circuit unit 215 may sort the plurality of read voltage sets according to the magnitude of the sum of the plurality of offset number differences of the plurality of read voltage sets.
For example, as shown in the table 1300, the read assist circuit unit 215 can calculate the sum of offset differences "5" of the read voltage set V (1) according to the offset differences "-1,9,6, -4, -3, -2,0" of the plurality of read voltages V (1) 1～V(1)7 of the read voltage set V (1). After calculating the sum of all offset differences, the read assist circuit unit 215 may sort the plurality of read voltage sets V (1) to V (16). Then, the read assist circuit unit 215 may directly determine the magnitude relation of the read voltages among the plurality of read voltage groups V (1) to V (16) according to the ordering of the plurality of read voltage groups V (1) to V (16).
For example, assume that the preset read voltage set is the read voltage set V (13) having a ranking value of "1", and the first adjusted read voltage set V (12) corresponding to the preset read voltage set being the read voltage set V (13) has a ranking value of "10". The read assist circuit 215 determines that the predetermined set of read voltages V (13) is smaller than the first set of adjusted read voltages V (12) (1 < 12). That is, the read assist circuit unit 215 determines that the read voltage of the preset read voltage set V (13) is smaller than the read voltage of the first adjusted read voltage set V (12) (e.g., the preset read voltage V (13) 4 is smaller than the first adjusted read voltage V (12) 4).
In another embodiment, the offset number difference calculated by the read assist circuit unit 215 may be the difference of the right offset count value minus the left offset count value, and the subsequent method of determining the two read voltage sets using the offset number difference sum is adjusted accordingly. For example, in the other embodiment, if the sum of the first offset numbers of the first read voltage set is smaller than the sum of the second offset numbers of the second read voltage set, the read assisting circuit unit 215 determines that the plurality of read voltages of the first read voltage set are "greater than" the second read voltage set (e.g., the read voltage V (1) 1 is greater than the read voltage V (2) 1).
It should be noted that, in the above embodiments, the reading auxiliary circuit unit 215 is implemented in a hardware circuit, but the invention is not limited thereto. For example, in one embodiment, the read assist circuit unit 215 may be implemented in software as a read assist program code module having the functions of the read assist circuit unit 215. The read assist program code modules may include a soft information manager program code module and a confidence table manager program code module. The soft information management program code module is a program code module having a function of the soft information management circuit 2151; the confidence table management program code module is a program code module having the function of the confidence table management circuit 2152. The processor 211 may access and execute a read-assist program code module (or a soft information management program code module and a confidence table management program code module) to implement the data read method (or the read-assist method) provided by the present invention.
In summary, the data reading method, the memory controller and the memory device according to the embodiments of the present invention can obtain a plurality of codewords corresponding to a target physical page by using a preset read operation (using a preset read voltage) and a read retry operation (using a first adjusted read voltage) performed on the target physical page without preparing verified data, and perform a preset decoding operation on the plurality of codewords to obtain a plurality of corresponding syndromes. And then, in response to a failure of the read retry operation (the syndrome of the codeword of the read retry operation is not zero), generating respective soft information of a plurality of target storage units of the target entity page according to the relative relationship between the syndromes and the codewords, so as to find out a plurality of confidence levels of the plurality of target storage units from a confidence table corresponding to the relative relationship and the target entity page, and further executing the adjusted iterative decoding operation according to the plurality of confidence levels. Therefore, the effective code word of the target entity page can be decoded through the adjusted iterative decoding operation with strong decoding capability, so that the correct effective code word can be obtained after the reading retry operation fails, the correctness and the reliability of the data read from the target word line are improved, the negative effect of the failure of the reading retry operation is reduced, the overall time for obtaining the effective code word by the reading operation is saved, and the overall efficiency of the data reading operation is further improved.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and practiced by those skilled in the art without departing from the spirit and scope of the present invention.

Claims (23)

1. A data reading method suitable for use in a memory device configured with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is to be programmed to a bit value, the method comprising:
selecting a target entity page of a target word line to perform a read operation on a target codeword stored by the target entity page, wherein a plurality of target storage units of the target entity page are used for respectively storing a plurality of target bit values of the target codeword;
Reading the target entity page using a preset read voltage corresponding to the target entity page to obtain a read codeword corresponding to the target entity page, and performing a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read codeword is stored in a codeword buffer and a first one of the plurality of read codeword syndromes is stored in a syndrome buffer;
In response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are not all zero, re-reading the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, and performing the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the first adjusted codeword is stored in the codeword buffer and the first of the plurality of first adjusted codeword syndromes is stored in the syndrome buffer;
Generating soft information for each of the plurality of target memory cells from a plurality of codewords in the codeword buffer corresponding to the read operation in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero;
Identifying a target confidence table corresponding to the size relative relation from a plurality of confidence tables corresponding to the target entity page according to the size relative relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the size relative relation of a plurality of patterns, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information patterns;
searching the respective confidence degrees of the plurality of target storage units from the target confidence table according to the plurality of soft information of the plurality of target storage units; and
Replacing a plurality of log likelihood ratios corresponding to the plurality of target memory cells in the preset decoding operation with a plurality of confidence levels of the plurality of target memory cells, and performing an adjusted preset decoding operation with the replaced plurality of log likelihood ratios on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and completing the reading operation.
2. The data reading method of claim 1, wherein the preset decoding operation comprises a plurality of iterative decoding operations applying a low density parity check algorithm.
3. The data reading method of claim 1, the method further comprising:
In response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are all zero, identifying a decoded read codeword corresponding to the last of the plurality of read codeword syndromes as the valid codeword for the read operation and completing the read operation; and
In response to determining that the plurality of bit values of the last of the plurality of first adjustment codeword syndromes are all zeros, identifying a decoded first adjustment codeword corresponding to the last of the plurality of first adjustment codeword syndromes as the valid codeword corresponding to the read operation, and completing the read operation.
4. The data reading method of claim 1, wherein if the total number of the plurality of syndromes in the syndrome buffer is equal to 2, and the plurality of syndromes includes a left syndrome corresponding to a lower read voltage and a right syndrome corresponding to a higher read voltage, wherein the magnitude relation includes one of the following aspects:
A first falling pattern, wherein if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude-relative relationship is identified as the first falling pattern, wherein the right syndrome is identified as a minimum syndrome; and
A first rising aspect in which the magnitude relation is identified as the first rising aspect, wherein the left syndrome is identified as a smallest syndrome if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the left syndrome,
A horizontal aspect in which if a difference between a total number of bit values "1" of the right syndrome and a total number of bit values "1" of the left syndrome is smaller than a syndrome difference threshold value, and the total number of bit values "1" of the right syndrome and the total number of bit values "1" of the left syndrome are both smaller than a syndrome threshold value, the magnitude relation is identified as the horizontal aspect in which a syndrome having a smaller total number of bit values "1" is identified as a minimum syndrome,
The plurality of confidence tables corresponding to the target entity page correspond to the first falling pattern, the first rising pattern and the horizontal pattern respectively.
5. The data reading method of claim 1, the step of generating the soft information for each of the plurality of target memory cells from a plurality of codewords in the codeword buffer corresponding to the read operation in response to determining that a plurality of bit values of a last one of the plurality of first adjustment codeword syndromes are not all zero comprising:
generating a second adjusted read voltage according to the preset read voltage, the first adjusted read voltage and the corresponding plurality of syndromes in response to determining that the last of the plurality of first adjusted codeword syndromes is not all zero;
reading the target entity page using the second adjustment read voltage to obtain a second adjustment codeword corresponding to the target entity page, and performing the preset decoding operation on the second adjustment codeword to obtain a plurality of second adjustment codeword syndromes corresponding to the second adjustment codeword, wherein the second adjustment codeword is stored in the codeword buffer and a first one of the plurality of second adjustment codeword syndromes is stored in the syndrome buffer; and
In response to determining that the last of the plurality of second adjustment codeword syndromes is not all zero, generating the soft information for each of the plurality of target memory cells from all codewords in the codeword buffer corresponding to the read operation.
6. The data reading method according to claim 5, wherein if the total number of the plurality of syndromes in the syndrome buffer is equal to 3, and the plurality of syndromes includes a left syndrome corresponding to a lowest read voltage, a right syndrome corresponding to a highest read voltage, and an intermediate syndrome corresponding to an intermediate read voltage, wherein the magnitude relation includes one of the following aspects:
a second descent pattern, wherein if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the intermediate syndrome and the total number of bit values "1" of the intermediate syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude-versus-relationship is identified as the second descent pattern, wherein the right syndrome is identified as a minimum syndrome;
A second rising pattern, wherein if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the intermediate syndrome and the total number of bit values "1" of the intermediate syndrome is greater than the total number of bit values "1" of the left syndrome, the magnitude-versus-relationship is identified as the second rising pattern, wherein the left syndrome is identified as a minimum syndrome;
A tick state sample in which if the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the left syndrome and the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the right syndrome, the magnitude relation is identified as the tick state sample, wherein the intermediate syndrome is identified as the smallest syndrome,
The plurality of confidence tables corresponding to the target entity page correspond to the second falling pattern, the second rising pattern and the hooking pattern respectively.
7. The data reading method according to claim 5, wherein the step of generating the second adjusted read voltage according to the preset read voltage, the first adjusted read voltage and the corresponding plurality of syndromes comprises:
calculating a voltage difference value obtained by subtracting the preset reading voltage from the first adjustment reading voltage;
In response to a total number of syndrome bit values "1" in the syndrome buffer corresponding to the first adjusted read voltage being less than a total number of syndrome bit values "1" corresponding to the preset read voltage, adding the first adjusted read voltage to the voltage difference to generate the second adjusted read voltage; and
In response to a total number of syndrome bit values "1" in the syndrome buffer corresponding to the first adjusted read voltage being greater than a total number of syndrome bit values "1" corresponding to the preset read voltage, subtracting the voltage difference from the preset read voltage to generate the second adjusted read voltage.
8. The data reading method of claim 1, the step of generating the soft information for each of the plurality of target memory cells from the plurality of codewords in the codeword buffer corresponding to the read operation comprising:
Identifying a smallest syndrome of the plurality of syndromes of the syndrome buffer having a smallest bit value of "1",
Selecting a codeword corresponding to the minimum syndrome among the plurality of codewords of the codeword buffer to set the selected codeword as a hard bit codeword corresponding to the plurality of target storage units, and setting remaining codewords not selected among the plurality of codewords of the codeword buffer as soft bit codewords corresponding to the plurality of target storage units; and
The soft information for each of the plurality of target memory locations is composed using the hard bit codeword and the soft bit codeword.
9. The data reading method of claim 8, wherein if the total number of soft bit codewords is greater than one, the step of using the hard bit codewords and the soft bit codewords to compose the soft information of each of the plurality of target memory cells comprises:
Performing an XOR operation or XNOR operation on all soft bit codewords, and taking the obtained first operation result corresponding to the XOR operation or the obtained second operation result corresponding to the XNOR operation as soft bit values of each of the plurality of target storage units;
Identifying respective hard bit values of the plurality of target memory locations from the hard bit codeword; and
Combining the hard bit values of each of the plurality of target storage units with the soft bit values of each of the plurality of target storage units to form the soft information of each of the plurality of target storage units.
10. The data reading method according to claim 1, wherein the step of looking up the confidence of each of the plurality of target storage units from the target confidence table based on the plurality of soft information of the plurality of target storage units comprises:
For a first soft information of a first target storage unit of the plurality of target storage units,
Searching a first soft information pattern which accords with the first soft information and a first preset confidence corresponding to the first soft information pattern from a plurality of soft information patterns of the target confidence table according to the first soft information, wherein the first preset confidence corresponding to the first soft information is set to be a preset value in response to the fact that the first soft information does not accord with one of the plurality of soft information patterns of the target confidence table; and
And identifying the first preset confidence as the first confidence of the corresponding target entity page of the first target storage unit.
11. The data reading method according to claim 10, wherein the absolute value magnitudes of each of a plurality of preset confidence levels in the target confidence table are set according to a target aspect of the magnitude-versus-relationship corresponding to the target confidence table,
Wherein the plurality of soft information aspects of the target confidence table are obtained from reading the target physical page by sequentially using one or more transition read voltages corresponding to the target aspects and the target physical page and one or more adjustment read voltages corresponding to the one or more transition read voltages,
Wherein the absolute value of one or more preset confidence levels corresponding to one or more soft information aspects of the one or more converted read voltages is set to a smaller value as the soft information aspects are closer to each other, wherein the absolute value of the preset confidence level corresponding to the soft information aspect between one of the one or more converted read voltages and the corresponding adjusted read voltage is set to a minimum value as the soft information aspects are in the soft information aspects,
Wherein the positive and negative of the plurality of preset confidence levels are set according to hard bit values in the corresponding soft information pattern,
Wherein the first predetermined confidence level is set to a negative value in response to the hard bit value of "1" in the soft information pattern corresponding to one of the plurality of predetermined confidence levels,
Wherein the first predetermined confidence level is set to a positive value in response to the hard bit value in the soft information pattern corresponding to the predetermined confidence level being "0".
12. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:
the connection interface circuit is used for being coupled to the host system;
A memory interface control circuit to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells includes a plurality of physical pages, and each of the plurality of physical pages is to be programmed to a bit value;
A read assist circuit unit;
an error checking and correcting circuit; and
A processor coupled to the connection interface circuit, the memory interface control circuit, the read assist circuit unit, and the error checking and correction circuit,
Wherein the processor is configured to select a target entity page of a target word line to perform a read operation on a target codeword stored by the target entity page, wherein a plurality of target memory locations of the target entity page are configured to store a plurality of target bit values of the target codeword, respectively,
Wherein the processor is further configured to read the target physical page using a preset read voltage corresponding to the target physical page to obtain a read codeword corresponding to the target physical page, wherein the error checking and correction circuit is configured to perform a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read assist circuit unit is configured to store the read codeword in a codeword buffer and store a first one of the plurality of read codeword syndromes in a syndrome buffer,
Wherein in response to determining that the plurality of bit values of the last one of the plurality of read codeword syndromes are not all zero, the processor is further configured to re-read the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, wherein the error checking and correction circuit is further configured to perform the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the read assist circuit unit is further configured to store the first adjusted codeword in the codeword buffer and store a first one of the plurality of first adjusted codeword syndromes in the syndrome buffer,
Wherein in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero, the read assist circuit is further configured to generate soft information for each of the plurality of target memory cells based on a plurality of codewords in the codeword buffer corresponding to the read operation,
Wherein the reading auxiliary circuit unit is further configured to identify a target confidence table corresponding to a magnitude-relation among a plurality of confidence tables corresponding to the target entity page according to the magnitude-relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to magnitude-relation of a plurality of aspects, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information aspects,
Wherein the read assist circuit unit is further configured to look up the respective confidence levels of the plurality of target storage units from the target confidence table based on the plurality of soft information of the plurality of target storage units,
Wherein the read assist circuit unit is further configured to replace a plurality of log likelihood ratio values corresponding to the plurality of target memory cells in the preset decoding operation with a plurality of confidence levels of the plurality of target memory cells, and the error checking and correcting circuit is further configured to perform an adjusted preset decoding operation with the replaced plurality of log likelihood ratio values on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and complete the read operation.
13. The memory controller of claim 12, wherein the preset decoding operation comprises a plurality of iterative decoding operations applying a low density parity check algorithm.
14. The memory controller of claim 12, wherein
In response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are all zero, the error checking and correction circuit identifies a decoded read codeword corresponding to the last of the plurality of read codeword syndromes as the valid codeword for the read operation, and the processor completes the read operation; and
In response to determining that the plurality of bit values of the last of the plurality of first adjustment codeword syndromes are all zero, the error checking and correction circuit identifies a decoded first adjustment codeword corresponding to the last of the plurality of first adjustment codeword syndromes as the valid codeword corresponding to the read operation, and the processor completes the read operation.
15. The memory controller of claim 12, wherein if the total number of the plurality of syndromes in the syndrome buffer is equal to 2, and the plurality of syndromes includes a left syndrome corresponding to a lower read voltage and a right syndrome corresponding to a higher read voltage, wherein the magnitude relative relationship includes one of the following aspects:
A first falling pattern, wherein if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude-relative relationship is identified as the first falling pattern, wherein the right syndrome is identified as a minimum syndrome; and
A first rising aspect in which the magnitude relation is identified as the first rising aspect, wherein the left syndrome is identified as a smallest syndrome if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the left syndrome,
A horizontal aspect in which if a difference between a total number of bit values "1" of the right syndrome and a total number of bit values "1" of the left syndrome is smaller than a syndrome difference threshold value, and the total number of bit values "1" of the right syndrome and the total number of bit values "1" of the left syndrome are both smaller than a syndrome threshold value, the magnitude relation is identified as the horizontal aspect in which a syndrome having a smaller total number of bit values "1" is identified as a minimum syndrome,
The plurality of confidence tables corresponding to the target entity page correspond to the first falling pattern, the first rising pattern and the horizontal pattern respectively.
16. The memory controller of claim 12 wherein, in said act of generating said soft information for each of said plurality of target memory cells based on a plurality of codewords in said codeword buffer corresponding to said read operation in response to determining that a plurality of bit values of a last one of said plurality of first adjustment codeword syndromes are not all zero,
In response to determining that the last one of the plurality of first adjustment codeword syndromes is not all zero, the read auxiliary circuit unit generates a second adjustment read voltage according to the preset read voltage, the first adjustment read voltage and the corresponding plurality of syndromes,
Wherein the read assist circuit unit uses the second adjusted read voltage to read the target physical page to obtain a second adjusted codeword corresponding to the target physical page, wherein the error checking and correcting circuit performs the preset decoding operation on the second adjusted codeword to obtain a plurality of second adjusted codeword syndromes corresponding to the second adjusted codeword, wherein the read assist circuit unit stores the second adjusted codeword in the codeword buffer and stores a first one of the plurality of second adjusted codeword syndromes in the syndrome buffer,
Wherein in response to determining that the last of the plurality of second adjustment codeword syndromes is not all zero, the read assist circuit unit generates the soft information for each of the plurality of target memory cells from all codewords in the codeword buffer corresponding to the read operation.
17. The memory controller of claim 16, wherein if the total number of the plurality of syndromes in the syndrome buffer is equal to 3, and the plurality of syndromes includes a left syndrome corresponding to a lowest read voltage, a right syndrome corresponding to a highest read voltage, and an intermediate syndrome corresponding to an intermediate read voltage, wherein the magnitude relation includes one of:
a second descent pattern, wherein if the total number of bit values "1" of the left syndrome is greater than the total number of bit values "1" of the intermediate syndrome and the total number of bit values "1" of the intermediate syndrome is greater than the total number of bit values "1" of the right syndrome, the magnitude-versus-relationship is identified as the second descent pattern, wherein the right syndrome is identified as a minimum syndrome;
A second rising pattern, wherein if the total number of bit values "1" of the right syndrome is greater than the total number of bit values "1" of the intermediate syndrome and the total number of bit values "1" of the intermediate syndrome is greater than the total number of bit values "1" of the left syndrome, the magnitude-versus-relationship is identified as the second rising pattern, wherein the left syndrome is identified as a minimum syndrome;
A tick state sample in which if the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the left syndrome and the total number of bit values "1" of the intermediate syndrome is less than the total number of bit values "1" of the right syndrome, the magnitude relation is identified as the tick state sample, wherein the intermediate syndrome is identified as the smallest syndrome,
The plurality of confidence tables corresponding to the target entity page correspond to the second falling pattern, the second rising pattern and the hooking pattern respectively.
18. The memory controller of claim 16, wherein in operation of the read assist circuit unit generating the second adjusted read voltage according to the preset read voltage, the first adjusted read voltage and the corresponding plurality of syndromes,
The read auxiliary circuit unit calculates a voltage difference obtained by subtracting the preset read voltage from the first adjusted read voltage,
Wherein the total number of bit values "1" of the syndromes corresponding to the first adjusted read voltage in response to the syndrome buffer is smaller than the total number of bit values "1" of the syndromes corresponding to the preset read voltage, the read assist circuit unit adds the first adjusted read voltage to the voltage difference to generate the second adjusted read voltage,
Wherein the read assist circuit unit subtracts the voltage difference from the preset read voltage to generate the second adjusted read voltage in response to a total number of bit values "1" of the syndromes corresponding to the first adjusted read voltage being greater than a total number of bit values "1" of the syndromes corresponding to the preset read voltage in the syndrome buffer.
19. The memory controller of claim 12 wherein in operation the read assist circuit unit generates the soft information for each of the plurality of target memory cells from the plurality of codewords in the codeword buffer corresponding to the read operation,
The read assist circuit unit identifies a smallest syndrome of the plurality of syndromes of the syndrome buffer having a smallest bit value of "1",
Wherein the read assist circuit unit selects a codeword corresponding to the minimum syndrome among the plurality of codewords of the codeword buffer to set the selected codeword as a hard bit codeword corresponding to the plurality of target memory cells, and sets the remaining codewords, which are not selected among the plurality of codewords of the codeword buffer, as soft bit codewords corresponding to the plurality of target memory cells,
Wherein the read assist circuit unit uses the hard bit codeword and the soft bit codeword to compose the soft information for each of the plurality of target memory cells.
20. The memory controller of claim 19, wherein if the total number of soft bit codewords is greater than one,
The read assist circuit unit performs an XOR operation or XNOR operation on all soft bit codewords, and takes the obtained first operation result corresponding to the XOR operation or the obtained second operation result corresponding to the XNOR operation as soft bit values of the respective plurality of target memory cells,
Wherein the read assist circuit unit identifies the hard bit value of each of the plurality of target memory cells from the hard bit codeword,
Wherein the read assist circuit unit combines the hard bit values of the respective ones of the plurality of target memory cells with the soft bit values of the respective ones of the plurality of target memory cells to form the soft information of the respective ones of the plurality of target memory cells.
21. The memory controller of claim 12, wherein in operation of the read assist circuit unit looking up the confidence of each of the plurality of target memory cells from the target confidence table based on a plurality of soft information of the plurality of target memory cells,
For a first soft information of a first target storage unit of the plurality of target storage units,
The reading auxiliary circuit unit searches a first soft information pattern corresponding to the first soft information from a plurality of soft information patterns of the target confidence table according to the first soft information, and a first preset confidence corresponding to the first soft information pattern,
Wherein in response to the first soft information not conforming to one of the plurality of soft information aspects of the target confidence table, the read assist circuit unit sets the first preset confidence level corresponding to the first soft information to a preset value,
The reading auxiliary circuit unit identifies the first preset confidence as the first confidence of the first target storage unit corresponding to the target entity page.
22. The memory controller of claim 21, wherein the absolute value magnitudes of each of the plurality of preset confidence levels in the target confidence table are set according to a target aspect of the magnitude-versus-relationship corresponding to the target confidence table,
Wherein the plurality of soft information aspects of the target confidence table are obtained from reading the target physical page via the read assist circuit unit sequentially using one or more converted read voltages corresponding to the target aspects and the target physical page and one or more adjusted read voltages corresponding to the one or more converted read voltages,
Wherein the absolute value of one or more preset confidence levels corresponding to one or more soft information aspects of the one or more converted read voltages is set to a smaller value as the soft information aspects are closer to each other, wherein the absolute value of the preset confidence level corresponding to the soft information aspect between one of the one or more converted read voltages and the corresponding adjusted read voltage is set to a minimum value as the soft information aspects are in the soft information aspects,
Wherein the positive and negative of the plurality of preset confidence levels are set according to hard bit values in the corresponding soft information pattern,
Wherein the first predetermined confidence level is set to a negative value in response to the hard bit value of "1" in the soft information pattern corresponding to one of the plurality of predetermined confidence levels,
Wherein the first predetermined confidence level is set to a positive value in response to the hard bit value in the soft information pattern corresponding to the predetermined confidence level being "0".
23. A storage device, the storage device comprising:
A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of word lines, wherein each of the plurality of word lines is coupled to a plurality of memory cells, wherein each of the plurality of memory cells comprises a plurality of physical pages, and each of the plurality of physical pages is to be programmed to a one-bit value;
A memory interface control circuit coupled to the rewritable non-volatile memory module; and
A processor coupled to the memory interface control circuit, wherein the processor loads and executes a read-assist program code module to implement a data reading method, the data reading method comprising the steps of:
selecting a target entity page of a target word line to perform a read operation on a target codeword stored by the target entity page, wherein a plurality of target storage units of the target entity page are used for respectively storing a plurality of target bit values of the target codeword;
Reading the target entity page using a preset read voltage corresponding to the target entity page to obtain a read codeword corresponding to the target entity page, and performing a preset decoding operation on the read codeword to obtain a plurality of read codeword syndromes corresponding to the read codeword, wherein the read codeword is stored in a codeword buffer and a first one of the plurality of read codeword syndromes is stored in a syndrome buffer;
In response to determining that the plurality of bit values of the last of the plurality of read codeword syndromes are not all zero, re-reading the target entity page using a first adjusted read voltage corresponding to the preset read voltage to obtain a first adjusted codeword corresponding to the target entity page, and performing the preset decoding operation on the first adjusted codeword to obtain a plurality of first adjusted codeword syndromes corresponding to the first adjusted codeword, wherein the first adjusted codeword is stored in the codeword buffer and the first of the plurality of first adjusted codeword syndromes is stored in the syndrome buffer;
Generating soft information for each of the plurality of target memory cells from a plurality of codewords in the codeword buffer corresponding to the read operation in response to determining that the last of the plurality of first adjustment codeword syndromes is not all zero;
Identifying a target confidence table corresponding to the size relative relation from a plurality of confidence tables corresponding to the target entity page according to the size relative relation among a plurality of syndromes in the syndrome buffer, wherein the plurality of confidence tables respectively correspond to the size relative relation of a plurality of patterns, and each of the plurality of confidence tables has a plurality of preset confidence degrees respectively corresponding to a plurality of soft information patterns;
searching the respective confidence degrees of the plurality of target storage units from the target confidence table according to the plurality of soft information of the plurality of target storage units; and
Replacing a plurality of log likelihood ratios corresponding to the plurality of target memory cells in the preset decoding operation with a plurality of confidence levels of the plurality of target memory cells, and performing an adjusted preset decoding operation with the replaced plurality of log likelihood ratios on the plurality of soft information to obtain a valid codeword corresponding to the target entity page, and completing the reading operation.
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