CN111901250A - Data message transmission method, device, equipment and readable storage medium - Google Patents
Data message transmission method, device, equipment and readable storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/28—Flow control; Congestion control in relation to timing considerations
- H04L47/283—Flow control; Congestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/32—Flow control; Congestion control by discarding or delaying data units, e.g. packets or frames
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2212/00—Encapsulation of packets
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Abstract
The invention discloses a data message transmission method, which comprises the following steps: analyzing the received data message transmission request to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period. By applying the technical scheme provided by the embodiment of the invention, the space waste is greatly reduced, and the transmission delay is reduced. The invention also discloses a data message transmission device, equipment and a storage medium, and has corresponding technical effects.
Description
Technical Field
The present invention relates to the field of computer application technologies, and in particular, to a data message transmission method, apparatus, device, and computer-readable storage medium.
Background
In the fields of high-performance calculation and the like, the data message obtained by calculation needs to be transmitted to a target end, and further analysis is carried out through the target end. For example, a Field-Programmable Gate Array (FPGA) and a server are interconnected by using a PCIE (peripheral component interconnect express), the FPGA acquires data to be processed through interfaces such as an ethernet, performs high-performance processing on the data, and finally uploads a processing result to the server through a PCIE interface for subsequent further processing. In the whole transmission process, the requirement on transmission delay is very high, and even microsecond-level optimization is very helpful for improving the calculation efficiency of the whole system.
Referring to fig. 1, fig. 1 is a block diagram of a data transmission system. When uploading data inside the FPGA, the PCIE interface module receives a processing result of the high-performance computing module, packages the data according to different lengths of the result, adds a TLP header and encapsulates the TLP header into a TLP packet, and sequentially writes the TLP packet into a server memory by using a PCIE bus through a Direct Memory Access (DMA) or direct uploading mode.
A TLP packet of PCIE is divided into two parts, namely a header and a payload, where a general header is 16 bytes, and a payload is generally 256 bytes at maximum for a general server, so that the total length of the TLP packet is 272 bytes at maximum. Because the length of the message to be uploaded is not fixed, when the length of the message exceeds 256 bytes, the message needs to be split and packaged. A PCIE interface within an FPGA can typically transmit 64 bytes of data per transmission cycle. Because the output length of the processing result of the front-end module is not fixed, the length of the message transmitted each time is also not fixed.
Referring to fig. 2, fig. 2 is a block diagram of a structure of a PCIE interface module in an FPGA in the prior art. The front-end module uploads the processing result to the PCIE uploading package module as PCIE uploading data, the PCIE uploading package module transmits the PCIE uploading data to the PCIE interface high-speed serial-parallel conversion transceiver, and the PCIE interface high-speed serial-parallel conversion transceiver uploads the PCIE uploading data to the server through the PCIE bus. When the server issues data through the PCIE interface module, the PCIE downlink data is firstly sent to the PCIE interface high-speed serial-parallel conversion transceiver, the PCIE interface high-speed serial-parallel conversion transceiver sends the PCIE downlink data to the PCIE downlink packaging module, and the PCIE downlink packaging module returns the PCIE downlink data to the FPGA. The PCIE interface management module plays a role in coordination management in the process of uploading and downloading data.
Referring to fig. 3, fig. 3 is a timing diagram of data uploaded by PCIE in FPGA in the prior art. The PCIE interface module transmits 4 TLP packets, where 256 bytes of payloads of the TLP1 and the TLP2, 68 bytes of payloads of the TLP3, and 144 bytes of payloads of the TLP4 take 15 FPGA cycle numbers in the whole transmission process.
In the existing scheme, the FPGA can only transmit the content of the same TLP packet in each transmission cycle, and if the length of the TLP packet is not a multiple of 64 bytes, for example, 16, 20, and 32 bytes at the tail of the TLP packet in fig. 3, a very large byte space is wasted in the FPGA cycle, for example, 48 bytes are correspondingly wasted in 16 bytes. As the amount of data transmitted increases, the amount of wasted space can be significant, which can be equivalent to increasing the delay in transmission.
In summary, how to effectively solve the problems of large total amount of space waste, prolonged transmission and the like in the existing data transmission mode is a problem that needs to be solved urgently by technical personnel in the field at present.
Disclosure of Invention
The invention aims to provide a data message transmission method, which greatly reduces the space waste and the transmission time delay; another object of the present invention is to provide a data message transmission apparatus, device and computer readable storage medium.
In order to solve the technical problems, the invention provides the following technical scheme:
a method of data message transmission, comprising:
analyzing the received data message transmission request to obtain each TLP packet to be transmitted;
sequentially sending the data packets in each TLP packet to a variable-length shift register;
combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group;
and sequentially sending each data message group to a target receiving end according to the transmission period.
In a specific embodiment of the present invention, sequentially sending data packets in each TLP packet to a variable-length shift register includes:
acquiring the target capacity of the variable-length shift register;
and sequentially sending each data message to the variable-length shift register by combining the target capacity.
In a specific embodiment of the present invention, sequentially sending each data packet to the variable-length shift register in combination with the target capacity includes:
acquiring the existing data message volume in the variable-length shift register;
and sequentially sending each data message to the variable-length shift register by combining the target capacity and the existing data message quantity.
In a specific embodiment of the present invention, sequentially sending each data packet group to a target receiving end according to the transmission cycle includes:
and sequentially sending each data message group in the FPGA to a server according to the transmission period.
In a specific embodiment of the present invention, after sequentially sending each data packet group in the FPGA to the server according to the transmission cycle, the method further includes:
and when the completion of the sending of each data message group is detected, feeding back message sending completion prompt information to the CPU.
In a specific embodiment of the present invention, sending a completion notification message to a CPU feedback packet includes:
and feeding back message sending completion prompt information to the CPU in an interruption mode.
A data message transmission apparatus, comprising:
a packet obtaining unit, configured to parse the received data packet transmission request to obtain each TLP packet to be transmitted;
a packet sending unit, configured to send data packets in each TLP packet to a variable-length shift register in sequence;
a packet group obtaining unit, configured to combine, according to a sequence in which each data packet enters the variable-length shift register, each data packet with a unit of a target packet length transmittable per transmission cycle, to obtain each data packet group;
and the message group sending unit is used for sequentially sending each data message group to a target receiving end according to the transmission cycle.
In a specific embodiment of the present invention, the message sending unit includes:
a capacity acquisition subunit, configured to acquire a target capacity of the variable-length shift register;
and the message sending subunit is configured to sequentially send each data message to the variable-length shift register in combination with the target capacity.
A data message transmission device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the data message transmission method as described above when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the data message transmission method as set forth above.
By applying the method provided by the embodiment of the invention, the received data message transmission request is analyzed to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period. The TLP packet to be transmitted is sent to the variable-length shift register by deploying the variable-length shift register, and the variable-length shift register is utilized to combine the data packets by taking the length of the target packet which can be transmitted in each transmission cycle as a unit to obtain each data packet group, so that each transmission cycle is fully utilized, the space waste is greatly reduced, and the transmission delay is reduced.
Correspondingly, the embodiment of the invention also provides a data message transmission device, equipment and a computer readable storage medium corresponding to the data message transmission method, which have the technical effects and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a data transmission system;
fig. 2 is a block diagram of a structure of a PCIE interface module in an FPGA in the prior art;
fig. 3 is a timing diagram of data uploaded by PCIE in FPGA in the prior art;
fig. 4 is a flowchart of an implementation of a data packet transmission method according to an embodiment of the present invention;
fig. 5 is a block diagram of a PCIE interface module in an FPGA according to an embodiment of the present invention;
fig. 6 is a flowchart of another implementation of a data packet transmission method according to an embodiment of the present invention;
FIG. 7 is a block diagram of a variable length shift register according to an embodiment of the present invention;
FIG. 8 is a block diagram of a shift logic structure of a variable length shift register according to an embodiment of the present invention;
fig. 9 is a flowchart of another implementation of a data packet transmission method according to an embodiment of the present invention;
fig. 10 is a timing diagram of PCIE upload data in an FPGA according to an embodiment of the present invention;
fig. 11 is a block diagram of a data message transmission apparatus according to an embodiment of the present invention;
fig. 12 is a block diagram of a data packet transmission device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 4, fig. 4 is a flowchart of an implementation of a data packet transmission method in an embodiment of the present invention, where the method may include the following steps:
s401: and analyzing the received data message transmission request to obtain each TLP packet to be transmitted.
When data transmission is needed, for example, when a processing result of the FPGA needs to be sent to the server, a data packet transmission request is sent to the data transmission center, where the data packet transmission request includes each TLP packet to be transmitted. The data transmission center receives the data packet transmission request, and analyzes the received data packet transmission request to obtain each TLP packet to be transmitted.
S402: and sequentially sending the data packets in each TLP packet to a variable-length shift register.
Referring to fig. 5, fig. 5 is a block diagram of a structure of a PCIE interface module in an FPGA according to an embodiment of the present invention. By adding the variable-length shift register and optimizing the PCIE uploading packet module, the optimized PCIE uploading packet module is obtained. After each TLP packet to be transmitted is obtained through analysis, the data packets in each TLP packet are sequentially sent to the variable-length shift register. The variable-length shift register can pre-store the data message in advance in the process of uploading the data message by the PCIE, and the data quantity written into the PCIE interface high-speed serial-parallel conversion transceiver can be dynamically controlled by judging the quantity of the transmitted data message and the pre-stored data message of the variable-length shift register in the transmission process to be accurate to bytes.
S403: and combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group.
The length of the target message which can be transmitted in each transmission period is preset. After the data packets in each TLP packet are sequentially sent to the variable-length shift register, the data packets are combined in units of the length of the target packet transmittable per transmission cycle according to the sequence in which the data packets enter the variable-length shift register, so as to obtain each data packet group.
It should be noted that the target message length may be set and adjusted according to an actual situation, which is not limited in the embodiment of the present invention, for example, when the processing result obtained by the high performance processing of the PFGA is transmitted to the server through the PCIE interface module, since each transmission cycle of the PCIE interface may generally transmit 64 bytes of data, the target message length may be set to 64 bytes.
S404: and sequentially sending each data message group to a target receiving end according to the transmission period.
And after the data message groups are obtained through combination, sequentially sending the data message groups to a target receiving end according to a transmission period.
By adding the variable-length shift register, the judgment on the existing data packet volume in the variable-length shift register is increased, and the TLP packet is dynamically carried out according to the parameter, unlike the original TLP packet which can only be passively packed according to the input effective data volume, so that the TLP packet transmission is not limited to the data packet which can only transmit the same TLP packet in each transmission period, the idle byte of the transmission period where the tail of the TLP packet is located is effectively utilized, the data transmission efficiency is improved, and the data transmission delay is reduced.
By applying the method provided by the embodiment of the invention, the received data message transmission request is analyzed to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period. The TLP packet to be transmitted is sent to the variable-length shift register by deploying the variable-length shift register, and the variable-length shift register is utilized to combine the data packets by taking the length of the target packet which can be transmitted in each transmission cycle as a unit to obtain each data packet group, so that each transmission cycle is fully utilized, the space waste is greatly reduced, and the transmission delay is reduced.
It should be noted that, based on the first embodiment, the embodiment of the present invention further provides a corresponding improvement scheme. In the following embodiments, steps that are the same as or correspond to those in the first embodiment may be referred to each other, and corresponding advantageous effects may also be referred to each other, which are not described in detail in the following modified embodiments.
Example two:
referring to fig. 6, fig. 6 is a flowchart of another implementation of a data packet transmission method in the embodiment of the present invention, where the method may include the following steps:
s601: and analyzing the received data message transmission request to obtain each TLP packet to be transmitted.
S602: the target capacity of the variable length shift register is obtained.
And after each TLP packet to be transmitted is obtained through analysis, the target capacity of the variable-length shift register is obtained. Referring to fig. 7, fig. 7 is a block diagram of a variable length shift register according to an embodiment of the present invention. The variable length shift register is a first-in first-out buffer module, but is more flexible than a common first-in first-out buffer, and a user can flexibly control the byte number of input and output data, for example, when the length of a target message which can be transmitted per transmission cycle is 64 bytes, the byte number of the input and output data can be controlled from 1 to 64 bytes, thereby avoiding resource waste caused by fixed data width. As shown in table 1, the interface function of the variable length shift register is described when the target message length that can be transmitted per transmission cycle is 64 bytes and the target capacity of the variable length shift register is 192 bytes.
TABLE 1
It should be noted that the target capacity may be set and adjusted according to actual situations, which is not limited in the embodiment of the present invention. For example, when the processing result obtained by the PFGA high-performance processing is transmitted to the server through the PCIE interface module, if the length of the target packet that can be transmitted per transmission cycle is 64 bytes, in this case, the target capacity may be set to 192 bytes.
S603: and acquiring the existing data message volume in the variable-length shift register.
And acquiring the existing data message volume in the variable-length shift register.
S604: and sequentially sending each data message to the variable-length shift register by combining the target capacity and the existing data message quantity.
After the target capacity of the variable-length shift register, the total data packet amount of each TLP packet and the existing data packet amount in the variable-length shift register are obtained, the data packets are sequentially sent to the variable-length shift register in combination with the target capacity and the existing data packet amount. Referring to fig. 8, fig. 8 is a block diagram of a shift logic structure of a variable length shift register according to an embodiment of the present invention. The variable-length shift register mainly comprises two key parts, namely shift logic and the existing data volume calculation. The discussion is divided into three cases:
(1) input-only data messages
When only data messages are input, the front end judges how many data messages can be written according to the actual data message total amount of the front end and the existing data message amount of the variable-length shift register, and the front end ensures that the variable-length shift register does not overflow. The input control pointer moves backwards, and the existing data message volume of the variable-length shift register is correspondingly increased.
(2) Outputting only data messages
When only the data packet is output, the back-end optimized PCIE upload packet module reads the data packet as much as possible according to the existing data packet amount, encapsulates the TLP, and ensures that the read data packet amount does not exceed the existing data packet amount. The output control pointer moves backwards, and the existing data message volume of the variable-length shift register is correspondingly reduced.
(3) Simultaneous input and output data message
And when the data messages are input and output at the same time, the writing and reading operations are judged according to the existing data message quantity of the variable-length shift register at the current moment for the front-end writing and the rear-end reading. The input and output control pointers are simultaneously moved backwards, and the existing data message volume of the variable-length shift register is correspondingly updated, and the data message volume can be increased or reduced.
S605: and combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group.
S606: and sequentially sending each data message group in the FPGA to a server according to the transmission period.
Under the condition that a data transmission scene is that a processing result obtained by PFGA high-performance processing is transmitted to a server through a PCIE interface module, after each data message group is obtained through combination, each data message group in the FPGA is sequentially sent to the server according to a transmission period.
In the process of data transmission, the update calculation of the existing data message volume in the variable-length shift register can be discussed in three cases:
(1) input-only data messages
When only the data message is input, the existing data message volume is as follows:
the existing data message volume is the existing data message volume plus the effective byte number of the input data.
(2) Outputting only data messages
When only data is output, the existing data message volume is as follows:
the existing data message volume is the existing data message volume-the number of read data bytes.
(3) Simultaneous input and output data message
When inputting and outputting data at the same time, the existing data message volume is as follows:
the existing data volume parameter is the existing data message volume plus the effective byte number of the input data plus the byte number of the read data.
S607: and when the completion of the transmission of each data message group is detected, feeding back message transmission completion prompt information to the CPU in an interruption mode.
And detecting the transmission progress in the data transmission process, and feeding back message transmission completion prompt information to the CPU in an interruption mode when the completion of the transmission of each data message group is detected, so as to promote the utilization of the transmitted data messages for the next analysis operation.
It should be noted that, besides the feedback of the completion prompt information to the CPU by using the interrupt mode, other prompt information feedback modes may also be used, so as to achieve the purpose of feeding back the completion information of the data packet transmission to the CPU, which is not limited in the embodiment of the present invention.
Referring to fig. 9, fig. 9 is another implementation flowchart of the data packet transmission method in the embodiment of the present invention, in a specific example application, when the length of a target packet that can be transmitted in each transmission cycle is 64 bytes, after a program starts, an optimized PCIE upload packet module monitors the state of a variable length shift register, and waits for a data packet to exist in the variable length shift register. Before data is input into the variable-length shift register, splitting is performed according to 256 bytes of the maximum load of a packet capable of sending a TLP, so that TLP splitting related matters are not processed in the optimized PCIE upload packet module. After detecting that there is a data packet, it is determined whether the payload length of the data packet is greater than or equal to 48 bytes, because the TLP header has 16 bytes, and 16+48 bytes is 64 bytes, which is the PCIE interface width.
If the length of the payload packet is greater than or equal to 48 bytes, the payload data packet and the TLP packet header are combined into a data packet group, and the length of the remaining payload packet is reduced by 48. And continuously judging whether the length of the residual load message is larger than or equal to 64 bytes, if so, sending a data message group, subtracting 64 from the length of the residual load message, and then continuously judging the length of the residual load message until the length of the residual load message is smaller than 64 bytes.
If the length of the payload packet is less than 48 bytes and the last remaining payload packet length of the upper segment is less than 64 bytes, the same branch is entered, and it is determined whether a new TLP packet has been stored in the variable-length shift register at this time. If the data packet is stored, continuously judging whether the byte vacancy of the transmittable byte of the current transmission period is larger than 16 bytes, if so, splicing a TLP packet head and a payload of the next TLP packet with the residual load of the previous packet into a data packet group for transmission; if not, only the TLP header of the next TLP packet and the residual load of the previous packet are spliced into a data packet group to be sent.
If the next TLP packet is not stored in the variable-length shift register at this time, the remaining payload is directly sent.
Referring to fig. 10, fig. 10 is a timing diagram of PCIE upload data in an FPGA according to an embodiment of the present invention. Compared with fig. 3, the data transmission method provided by the embodiment of the present invention can save space of 48+48+ 44-140 bytes, and after optimization, the transmission time of the same 4 TLP packets is reduced from 15 cycles to 13 cycles by performing TLP head-to-tail splicing operation, so that the transmission efficiency is improved by 15.4%, and the performance is greatly improved.
Corresponding to the above method embodiments, the embodiments of the present invention further provide a data packet transmission apparatus, and the data packet transmission apparatus described below and the data packet transmission method described above may be referred to correspondingly.
Referring to fig. 11, fig. 11 is a block diagram of a data packet transmission apparatus according to an embodiment of the present invention, where the apparatus may include:
a packet obtaining unit 111, configured to parse the received data packet transmission request to obtain each TLP packet to be transmitted;
a packet sending unit 112, configured to send the data packets in each TLP packet to a variable-length shift register in sequence;
a packet group obtaining unit 113, configured to combine, according to the order in which each data packet enters the variable-length shift register, each data packet with a unit of a target packet length that can be transmitted in each transmission cycle, to obtain each data packet group;
a packet sending unit 114, configured to send each data packet to a target receiving end in sequence according to the transmission cycle.
The device provided by the embodiment of the invention is applied to analyze the received data message transmission request to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period. The TLP packet to be transmitted is sent to the variable-length shift register by deploying the variable-length shift register, and the variable-length shift register is utilized to combine the data packets by taking the length of the target packet which can be transmitted in each transmission cycle as a unit to obtain each data packet group, so that each transmission cycle is fully utilized, the space waste is greatly reduced, and the transmission delay is reduced.
In a specific embodiment of the present invention, the message sending unit 112 includes:
a capacity acquisition subunit, configured to acquire a target capacity of the variable-length shift register;
and the message sending subunit is configured to sequentially send each data message to the variable-length shift register in combination with the target capacity.
In a specific embodiment of the present invention, the message sending subunit is specifically configured to obtain an existing data message amount in the variable-length shift register; and combining the target capacity and the existing data message quantity to sequentially send each data message to a unit in the variable-length shift register.
In a specific embodiment of the present invention, the packet group sending unit 114 is specifically a unit that sequentially sends each data packet group in the FPGA to the server according to the transmission cycle.
In one embodiment of the present invention, the apparatus may further include:
and the prompt information sending unit is used for feeding back message sending completion prompt information to the CPU when the completion of the sending of each data message group is detected after each data message group in the FPGA is sent to the server in sequence according to the transmission period.
In a specific embodiment of the present invention, the prompt information sending unit is specifically a unit that feeds back the message sending completion prompt information to the CPU in an interrupt manner.
Corresponding to the above method embodiment, referring to fig. 12, fig. 12 is a schematic diagram of a data packet transmission device provided in the present invention, where the device may include:
a memory 121 for storing a computer program;
the processor 122, when executing the computer program stored in the memory 121, may implement the following steps:
analyzing the received data message transmission request to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period.
For the introduction of the device provided by the present invention, please refer to the above method embodiment, which is not described herein again.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
analyzing the received data message transmission request to obtain each TLP packet to be transmitted; sequentially sending the data packets in each TLP packet to a variable-length shift register; combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group; and sequentially sending each data message group to a target receiving end according to the transmission period.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method for data message transmission, comprising:
analyzing the received data message transmission request to obtain each TLP packet to be transmitted;
sequentially sending the data packets in each TLP packet to a variable-length shift register;
combining the data messages by taking the length of the target message which can be transmitted in each transmission period as a unit according to the sequence of the data messages entering the variable-length shift register to obtain each data message group;
and sequentially sending each data message group to a target receiving end according to the transmission period.
2. The method according to claim 1, wherein sending the data packets in each TLP packet to a variable-length shift register in sequence, includes:
acquiring the target capacity of the variable-length shift register;
and sequentially sending each data message to the variable-length shift register by combining the target capacity.
3. The method of claim 2, wherein sequentially transmitting each of the data packets into the variable length shift register in combination with the target capacity comprises:
acquiring the existing data message volume in the variable-length shift register;
and sequentially sending each data message to the variable-length shift register by combining the target capacity and the existing data message quantity.
4. The method according to any one of claims 1 to 3, wherein the step of sequentially transmitting each data packet group to a target receiving end according to the transmission cycle comprises:
and sequentially sending each data message group in the FPGA to a server according to the transmission period.
5. The data packet transmission method according to claim 4, wherein after sequentially sending each data packet group in the FPGA to the server according to the transmission cycle, the method further comprises:
and when the completion of the sending of each data message group is detected, feeding back message sending completion prompt information to the CPU.
6. The data message transmission method of claim 5, wherein feeding back a message sending completion hint to the CPU comprises:
and feeding back message sending completion prompt information to the CPU in an interruption mode.
7. A data message transmission apparatus, comprising:
a packet obtaining unit, configured to parse the received data packet transmission request to obtain each TLP packet to be transmitted;
a packet sending unit, configured to send data packets in each TLP packet to a variable-length shift register in sequence;
a packet group obtaining unit, configured to combine, according to a sequence in which each data packet enters the variable-length shift register, each data packet with a unit of a target packet length transmittable per transmission cycle, to obtain each data packet group;
and the message group sending unit is used for sequentially sending each data message group to a target receiving end according to the transmission cycle.
8. The data message transmission device of claim 7, wherein the message sending unit comprises:
a capacity acquisition subunit, configured to acquire a target capacity of the variable-length shift register;
and the message sending subunit is configured to sequentially send each data message to the variable-length shift register in combination with the target capacity.
9. A data message transmission device, comprising:
a memory for storing a computer program;
processor for implementing the steps of the data message transmission method according to one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the data message transmission method according to one of claims 1 to 6.
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