CN111901007B - Packet transmission control method and packet transmission circuit - Google Patents
Packet transmission control method and packet transmission circuit Download PDFInfo
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- CN111901007B CN111901007B CN201910367451.1A CN201910367451A CN111901007B CN 111901007 B CN111901007 B CN 111901007B CN 201910367451 A CN201910367451 A CN 201910367451A CN 111901007 B CN111901007 B CN 111901007B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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Abstract
A packet transmission circuit and a packet transmission control method are provided, the packet transmission control method is applied to the packet transmission circuit, and comprises the following steps: make the packet receiving circuit, multiple processing circuits and packet transmitting circuit in the packet transmission circuit in the closed state; judging that the packet receiving circuit needs to start the receiving circuit, waking up the packet receiving circuit to a working state to receive the packet streaming, and recovering to a closing state after the receiving is finished; waking up the processing circuits to a working state respectively at respective required time according to the working sequence of the processing circuits so as to receive and transmit the packet streams from the packet receiving circuit, processing the packet streams within respective processing time, and recovering to a closing state after the processing is finished; and waking up the packet transmission circuit to a working state so as to transmit the packet stream processed by the processing circuit to an external device, and recovering to a closed state after the transmission is finished.
Description
Technical Field
The present invention relates to a packet transmission technology, and more particularly, to a packet transmission control method and a packet transmission circuit.
Background
In order to reduce the idle consumption of the IC, power saving mechanisms including turning off the power supply and turning off the clock are often made according to the operation mode of the IC. When the IC does not need to receive or transmit packets, most circuits which are not needed to be used can be turned off to enter a power-saving mode, and at the moment, only a packet detection circuit is needed to be turned on.
In the power saving mode, when the packet detection circuit detects that a packet arrives, the receiving circuit is turned on, but because the packet is processed in layers from a front-end high-frequency or analog circuit to a physical layer circuit to a control layer circuit inside the IC, the actual time for operating and processing the packet of each layer of circuit is not completely the same, and the actual time for operating and processing the packet of the internal functional module of each layer of circuit is not completely the same. After each layer of circuits and each functional module are turned on, there is usually some time to wait without processing packets, for example: unnecessary power consumption occurs before the previous layer of circuits have completed processing or after the packet has been handed to the next layer of circuits. When a packet needs to be transmitted, although the uncertainty of when the packet needs to be transmitted is low, because the packet is processed in layers from the control layer circuit to the physical layer circuit to the front end high frequency or analog circuit, the actual time for processing the packet by each layer of circuit is not completely the same, the actual time for operating and processing the packet by the internal functional module of each layer of circuit is not completely the same, and after each layer of circuit and each functional module are started, part of the time is in a waiting state without processing the packet, and unnecessary power consumption is generated.
Therefore, it is an urgent need in the art to design a new packet transmission control method and a new packet transmission circuit to solve the above-mentioned drawbacks.
Disclosure of Invention
This summary is intended to provide a simplified summary of the disclosure in order to provide a basic understanding to the reader. This summary is not an extensive overview of the disclosure and is intended to neither identify key/critical elements of the embodiments nor delineate the scope of the embodiments.
To achieve the above object, one embodiment of the present invention relates to a packet transmission control method applied in a packet transmission circuit, including: make the packet receiving circuit, multiple processing circuits and packet transmitting circuit in the packet transmission circuit in the closed state; judging that a packet receiving circuit in the packet transmission circuit needs to start receiving a packet stream, waking up the packet receiving circuit to a working state, receiving the packet stream, and recovering to the closing state after the receiving is finished; waking up the processing circuits to a working state respectively at the time required to run respectively according to the working sequence of the processing circuits so as to receive and transmit the packet stream from the packet receiving circuit, process the packet stream within the respective processing time and recover to a closing state after the processing is finished; and waking up the packet transmission circuit to a working state so as to transmit the packet stream processed by the processing circuit to an external device, and recovering to a closed state after the transmission is finished.
Another technical embodiment of the present disclosure relates to a packet transmission circuit, including: the device comprises a packet receiving circuit, a plurality of processing circuits and a packet transmitting circuit. The packet receiving circuit is configured to be in a closed state, wake up to an operating state to receive the packet stream when the packet stream needs to be received, and recover to the closed state after the reception is completed. The processing circuit is configured to be in a closed state, and awakens to the working state respectively at the time of respective operation according to the working sequence of the processing circuit, so as to receive and transmit the packet stream from the packet receiving circuit, process the packet stream within the respective processing time, and recover to the closed state after the processing is completed. The packet transmission circuit is configured to be in a closed state, transmits the packet stream processed by the processing circuit to an external device after waking up to a working state, and restores to the closed state after transmission is completed.
The packet transmission control method and the packet transmission circuit can enable the included circuit to be in the closed state for a long time, and only when the packet stream needs to be processed, the included circuit is sequentially waken to the working state for processing and then is recovered to the closed state, so that the long-time standby waiting for the packet stream is not needed any more, and the waste of power supply is avoided.
Drawings
In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a block diagram of a packet transmission circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram illustrating the operation of various circuits included in the packet transmission circuit according to an embodiment of the present invention;
FIG. 3 is a block diagram of a packet transmission circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the operation of various circuits included in the packet transmission circuit according to an embodiment of the present invention;
and
fig. 5 is a flowchart of a packet transmission control method according to an embodiment of the present invention.
Description of the symbols
1. 3: the packet transmission circuit 100: packet detection circuit
102. 300, and (2) 300: packet reception circuitry 104, 106, 108, 110, 302, 304:
112. 306: packet processing circuit of packet transmission circuit
PS: packet streams T21-T29, T30, T32, T41-T49:
500: packet transmission control method time point
501-504: step (ii) of
Detailed Description
Please refer to fig. 1 and fig. 2 simultaneously. Fig. 1 is a block diagram of a packet transmission circuit 1 according to an embodiment of the present invention. Fig. 2 is a timing diagram illustrating operations of the circuits included in the packet transmission circuit 1 according to an embodiment of the present invention.
The packet transmission circuit 1 includes: the apparatus includes a packet detection circuit 100, a packet reception circuit 102, a plurality of processing circuits 104, 106, 108, 110, and a packet transmission circuit 112. In the present embodiment, the packet transmission circuit 1 is a receiving end (RX) of a network device (not shown).
The packet detection circuit 100 may include portions of front-end circuitry. When the packet transmission circuit 1 is located in a wireless network device, the front-end circuit may be a Radio Frequency (RF) circuit. When the packet transmission circuit 1 is located in a wired network device, the front-end circuit may be an ethernet (ethernet) circuit.
In the embodiment, since the packet transmission circuit 1 is a receiving end of a network device (not shown), it cannot predict when the packet stream will be received, and therefore the packet detection circuit 100 is continuously in an active state for detection before detecting the packet. As shown in fig. 2, the packet detection circuit 100 is continuously in the operating state from the time point T21 until the packet is detected.
When the packet detection circuit 100 detects the packet stream PS, the packet receiving circuit 102 is awakened to receive packets in the packet stream PS.
The processing circuits 104, 106, 108, 110 include, for example, but are not limited to, physical layer circuits and Medium Access Control (MAC) circuits. In the present embodiment, the processing circuit 104 is a phy layer packet detection circuit, the processing circuit 106 is a phy layer circuit, the processing circuit 108 is a mac packet error detection circuit, and the processing circuit 110 is a mac circuit.
The processing circuits 104, 106, 108, 110 are configured to be in a shutdown state, and wake up to a working state at respective required running time according to the working sequence of the processing circuits 104, 106, 108, 110, respectively, so as to perform packet detection, error detection, reception, processing and transmission on the packet stream PS from the packet receiving circuit 102, and shutdown the layer of circuits after the completion of the running.
In one embodiment, the packet detection circuit 100 wakes up the packet reception circuit 102 as a front-end circuit to receive the packet stream PS when detecting a packet, and then wakes up and delivers the packet to the processing circuit 104 as a phy layer packet detection circuit. The processing circuit 104, acting as a physical layer packet detection circuit, detects and determines whether the packet needs to be received: if not, abandoning the package and closing the related circuit again; if it is needed, then it wakes up and passes the packet to processing circuitry 106, which is a physical layer circuit. The processing circuit 106, which is a phy layer circuit, processes the packet stream PS and then wakes up and delivers the packet to the processing circuit 108, which is a mac packet error detection circuit.
The processing circuit 108, which is a mac packet error detection circuit, detects and determines whether the packet needs to be received. If not, abandoning the package and closing the related circuit again; if it is needed, it then wakes up and passes the packet to the processing circuit 110, which acts as a mac circuit. The processing circuit 110, which is a mac circuit, processes the packet stream PS and then wakes up and delivers the packet to the packet transmitting circuit 112. And the layer-by-layer processing is completed until the packet processing is completed, and the layer of circuit is started only when the operation is determined to be needed, and is closed when the operation is completed.
The operation timing of each layer of circuitry will be described in more detail below, in conjunction with the timing shown in fig. 2.
As shown in fig. 2, the packet receiving circuit 102 is in the off state at the time point T21. At time T22, the packet receiving circuit 102 wakes up to receive the packet stream PS and performs processing at the processing time from time T22 to time T23. Further, the packet receiving circuit 102 will return to the off state after completing the processing of the packet stream PS at the time point T23.
On the other hand, the processing circuit 104 is also in the off state at the time point T21. At time T24, the processing circuit 104 wakes up to receive the packet stream PS from the packet receiving circuit 102 and performs processing at the processing time from time T24 to time T26. Further, the processing circuit 104 will return to the off state after completing the processing of the packet stream PS at the time point T26. Similarly, the processing circuits 106, 108, 110 are sequentially woken up to an active state and then restored to an off state after processing is complete.
In this embodiment, after the packet receiving circuit 102 completes processing the header of the packet in the packet stream PS, it can simultaneously continue to process the packet stream PS and transmit the packet stream PS to the next processing circuit 104, so as to wake up the processing circuit 104 to the working state for processing. Therefore, the processing times T22-T23 of the processing circuit 102 and the processing times T24-T26 of the processing circuit 104 overlap each other.
Further, the processing circuit 104 will return to the off state after completing the processing of the packet stream PS at the time point T26.
It is noted that in other embodiments, the packet receiving circuit 102 and the processing circuit 104 may transmit to the next stage after completely processing the packet stream PS. In such a case, the processing times of the packet reception circuit 102 and the processing circuit 104 do not overlap with each other.
In sequence, the processing circuits 106, 108, and 110 respectively process the packet stream PS from time T26 to time T25, from time T28 to time T30, and from time T30 to time T27, and then return to the off state after completion.
In one embodiment, the packet forwarding circuit 112 includes upper layer circuits. The packet forwarding circuit 112 is also in the off state at the time point T21. At time T32, the packet transmitting circuit 112 wakes up to receive the packet stream PS from the processing circuit 110, processes the packet stream PS at the processing time from time T32 to time T29, transmits the packet stream PS to an external device (not shown), and returns to the off state after the transmission is completed at time T29.
In one embodiment, the external device may be a network device in which the packet transmission circuit 1 is located, and includes other circuit modules such as a first-in-first-out queue, a Direct Memory Access (DMA) circuit, and the like, or other devices coupled by the network device through a bus.
It should be noted that, in the present embodiment, four processing circuits 104, 106, 108, and 110 are exemplified. In different embodiments, other processing circuits may be configured to perform corresponding processing on the packet stream PS according to the requirements of the actual application. The number and functions of the processing circuits are not limited to those described in the above embodiments.
Please refer to fig. 3 and fig. 4 simultaneously. Fig. 3 is a block diagram of a packet transmission circuit 3 according to an embodiment of the present invention. Fig. 4 is a timing diagram illustrating operations of the circuits included in the packet transmission circuit 3 according to an embodiment of the present invention.
The packet transmission circuit 3 includes: a packet receiving circuit 300, a plurality of processing circuits 302, 304, and a packet transmitting circuit 306. In the present embodiment, the packet transmission circuit 3 is a transmitting Terminal (TX) of a network device (not shown).
The packet receiving circuit 300 may include upper layer circuits. The packet receiving circuit 300 is configured to receive a packet stream PS from a packet source (not shown). The packet source may be other circuit modules such as a first-in-first-out queue, a Direct Memory Access (DMA) circuit and the like included in the network device where the packet transmission circuit 3 is located, or other devices coupled by the network device through a bus.
In the embodiment, since the packet transmission circuit 3 is the transmitting end, it can know when the packet is received according to the packet source. Therefore, as shown in fig. 4, the packet receiving circuit 300 may be in the off state at time T41 and wake up to the on state at time T42 according to the control of the packet source to receive the packet stream PS.
When the packet receiving circuit 300 determines that the packet stream PS is received, the packets in the packet stream PS are processed at the processing time from the time point T42 to the time point T43. Further, the packet receiving circuit 300 is restored to the off state after completing the processing of the packet stream PS at the time point T43.
In the present embodiment, the processing circuit 302 is a mac circuit, and the processing circuit 304 is a phy layer circuit.
The processing circuits 302 and 304 are configured to be in the off state and wake up to the on state according to the operation sequence of the processing circuits 302 and 304, respectively, to receive and transmit the packet stream PS from the packet receiving circuit 300.
In one embodiment, the processing circuit 302, which is a mac circuit, receives the packet stream PS, processes the packet stream PS, and further delivers the processed packet stream PS to the processing circuit 304. The processing circuit 304, as a physical layer circuit, receives the packet stream PS after the processing circuit 302, processes the packet stream PS, and further delivers to the packet transmitting circuit 306.
As shown in fig. 4, the processing circuit 302 is in the off state at a time point T41. At time T44, the processing circuit 302 wakes up to receive the packet stream PS from the packet receiving circuit 300 and performs processing at the processing time from time T44 to time T45. Further, the processing circuit 302 will return to the off state after completing the processing of the packet stream PS at the time point T45.
On the other hand, the processing circuit 304 is also in the off state at the time point T41. At time T46, the processing circuit 304 wakes up to receive the packet stream PS from the processing circuit 302 and performs processing at the processing time from time T46 to time T47.
In this embodiment, after completing the header of the packet in the packet stream PS, the processing circuit 302 may continue to process the packet stream PS and transmit the packet stream PS to the next processing circuit 304, so as to wake up the processing circuit 304 to be in an active state and perform processing. Therefore, the processing times T44-T45 of the processing circuit 302 and the processing times T46-T47 of the processing circuit 304 overlap each other.
Further, the processing circuit 304 will return to the off state after completing the processing of the packet stream PS at the time point T47.
It is noted that in other embodiments, the processing circuit 302 and the processing circuit 304 may transmit to the next stage after completely processing the packet stream PS. In such a case, the processing times of the processing circuit 302 and the processing circuit 304 do not overlap with each other.
The packet forwarding circuit 306 is also in the off state at time T41. At time T48, the packet transmitting circuit 306 wakes up to receive the packet stream PS from the processing circuit 304, processes the packet stream PS at the processing time from time T48 to time T49, transmits the packet stream PS to an external device (not shown), and returns to the off state after the transmission is completed at time T49.
In one embodiment, the packet transmit circuit 306 includes front-end circuitry. When the packet transmission circuit 3 is located in the wireless network device, the front-end circuit may be a radio frequency circuit. When the packet transmission circuit 3 is located in a wired network device, the front-end circuit may be an ethernet circuit.
In one embodiment, the external device may be an external network device connected to the front-end circuit through, for example but not limited to, an antenna or a physical network cable.
It should be noted that, in the present embodiment, two processing circuits 302 and 304 are exemplified. In different embodiments, other processing circuits may be configured to perform corresponding processing on the packet stream PS according to the requirements of the actual application. The number and functions of the processing circuits are not limited to those described in the above embodiments.
In the above embodiments, the shutdown state and the operation state of each of the packet receiving circuit, the processing circuit and the packet transmitting circuit can be realized by mechanisms such as (but not limited to) power gating and clock gating.
Therefore, the packet transmission circuit 1 and the packet transmission circuit 3 of the present invention can make the included circuits in the off state for a long time, and only when the packet stream needs to be processed, the included circuits are sequentially waken to the working state for processing, and then are recovered to the off state. The packet transmission circuit 1 and the packet transmission circuit 3 will not need to wait for the packet stream in the working state for a long time to cause the waste of power.
Please refer to fig. 5. Fig. 5 is a flowchart of a packet transmission control method 500 according to an embodiment of the present invention. The packet transmission control method 500 can be applied to the packet transmission circuit 1 shown in fig. 1 or the packet transmission circuit 3 shown in fig. 3. The packet transmission circuit 1 shown in fig. 1 will be described as an example.
The packet transmission control method 500 includes the following steps (it should be understood that the steps mentioned in the present embodiment, except the sequence specifically mentioned, can be performed simultaneously or partially simultaneously according to the actual requirement.
In step 501, the packet receiving circuit 102, the processing circuits 104, 106, 108, 110 and the packet transmitting circuit 112 in the packet transmitting circuit 1 are turned off.
In step 502, it is determined that the packet receiving circuit 102 in the packet transmission circuit 1 needs to start receiving the packet stream PS, wake up the packet receiving circuit 102 to an operating state, receive the packet stream PS, and recover to a shutdown state after receiving is completed.
In one embodiment, the packet receiving circuit 102 is awakened by the packet detection circuit 100 after the packet detection circuit 100 detects the packet stream PS.
In step 503, the processing circuits 104, 106, 108, and 110 are respectively awakened to an operating state according to the operating sequence of the processing circuits 104, 106, 108, and 110, so as to receive and transmit the packet stream PS from the packet receiving circuit 102, perform processing within the respective processing time, and recover to a shutdown state after the processing is completed.
In step 504, the packet transmitting circuit 112 is awakened to an active state to transmit the packet stream PS processed by the processing circuits 104, 106, 108, and 110 to the external device, and is restored to an off state after the transmission is completed.
Although the foregoing embodiments have been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (10)
1. A packet transmission control method is applied to a packet transmission circuit and comprises the following steps:
enabling a packet receiving circuit, a plurality of processing circuits and a packet transmitting circuit in the packet transmission circuit to be in a closed state;
judging that a packet receiving circuit in the packet transmission circuit needs to start receiving a packet stream, waking up the packet receiving circuit to a working state, receiving the packet stream, and recovering to the closing state after the receiving is finished;
waking up the processing circuits to a working state respectively at the time of respective required operation according to a working sequence of the processing circuits so as to receive and transmit the packet stream from the packet receiving circuit, perform processing within respective processing time, and recover to the closing state after the processing is completed; and
waking up the packet transmission circuit to the working state so as to transmit the packet stream processed by the processing circuit to an external device, and recovering to the closing state after the transmission is completed.
2. The packet transmission control method according to claim 1, wherein the processing times of the processing circuits do not overlap with each other.
3. The packet transmission control method according to claim 1, wherein the processing circuits continue to process the packet stream and transmit the packet stream to the next processing circuit after completing processing a header of at least one packet in the packet stream, the processing time of each processing circuit overlapping each other.
4. The method of claim 1, wherein the packet transmission circuit is a receiver of a network device, the packet reception circuit comprises a front-end circuit, the processing circuit comprises a PHY circuit and a MAC circuit, and the packet transmission circuit comprises an upper layer circuit.
5. The packet transmission control method according to claim 1, wherein the packet transmission circuit is a transmitting end of a network device, the packet reception circuit includes an upper layer circuit, the processing circuit includes a medium access control circuit and a physical layer circuit, the packet transmission circuit includes a front end circuit;
the packet receiving circuit is in the closed state, wakes up to the working state according to the control of a packet stream source to receive the packet stream for processing, and restores to the closed state after the processing is finished.
6. A packet transmission circuit, comprising:
a packet receiving circuit configured to be in a closed state, wake up to an operating state to receive a packet stream when the packet stream needs to be received, and recover to the closed state after the reception is completed;
a plurality of processing circuits configured to be in a shutdown state, and wake up to a working state respectively at respective required operation time according to a working sequence of the processing circuits, so as to receive and transmit the packet stream from the packet receiving circuit, perform processing within respective processing time, and recover to the shutdown state after the processing is completed; and
and the packet transmission circuit is configured to be in the closed state, transmits the packet stream processed by the processing circuit to an external device after waking up to the working state, and restores to the closed state after transmission is finished.
7. The packet transmission circuit according to claim 6, wherein the processing times of the processing circuits do not overlap.
8. The packet transmission circuit according to claim 6, wherein the processing circuits continue processing the packet stream and transmitting the packet stream to the next processing circuit after processing a header of at least one packet in the packet stream, the processing times of each of the processing circuits overlapping each other.
9. The packet transmission circuit according to claim 6, wherein the packet transmission circuit is a receiving end of a network device, the packet reception circuit includes a front end circuit, the processing circuit includes a physical layer circuit and a medium access control circuit, and the packet transmission circuit includes an upper layer circuit.
10. The packet transmission circuit according to claim 6, wherein the packet transmission circuit is a transmitting end of a network device, the packet reception circuit includes an upper layer circuit, the processing circuit includes a physical layer circuit and a medium access control circuit, the packet transmission circuit includes a front end circuit;
the packet receiving circuit is in the closed state, wakes up to the working state according to the control of a packet stream source to receive the packet stream for processing, and restores to the closed state after the processing is finished.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102045818A (en) * | 2009-10-15 | 2011-05-04 | 友劲科技股份有限公司 | Data message filtering method of wireless device |
| CN102421171A (en) * | 2010-09-28 | 2012-04-18 | 国基电子（上海）有限公司 | Mobile station, access point and method of saving electricity for mobile station |
| CN205319699U (en) * | 2016-01-22 | 2016-06-15 | 江苏中海昇物联科技有限公司 | Engineering equipment monitoring devices's power supply unit and engineering equipment monitoring devices |
| CN108539743A (en) * | 2018-05-19 | 2018-09-14 | 北京合众汇能科技有限公司 | A kind of high-efficiency and energy-saving type distribution terminal |
| CN109036299A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Data transmission method, device, system and storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI517628B (en) * | 2010-03-29 | 2016-01-11 | 瑞昱半導體股份有限公司 | Low power consumption network device and communication method thereof |
| JP6373415B2 (en) * | 2014-06-02 | 2018-08-15 | エルジー エレクトロニクス インコーポレイティド | Power save mode based operation method and apparatus in wireless LAN |
| US9716505B2 (en) * | 2014-12-15 | 2017-07-25 | Nxp Usa, Inc. | System and method for enhanced clocking operation |
| EP3506712B1 (en) * | 2016-08-23 | 2021-06-30 | Electronics and Telecommunications Research Institute | Method for operating communication node supporting low power mode in wireless lan |
| CN108738111B (en) * | 2017-04-20 | 2021-01-08 | 华为技术有限公司 | Verification association method, mobile wireless access point and station |
-
2019
- 2019-05-05 CN CN201910367451.1A patent/CN111901007B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102045818A (en) * | 2009-10-15 | 2011-05-04 | 友劲科技股份有限公司 | Data message filtering method of wireless device |
| CN102421171A (en) * | 2010-09-28 | 2012-04-18 | 国基电子（上海）有限公司 | Mobile station, access point and method of saving electricity for mobile station |
| CN205319699U (en) * | 2016-01-22 | 2016-06-15 | 江苏中海昇物联科技有限公司 | Engineering equipment monitoring devices's power supply unit and engineering equipment monitoring devices |
| CN109036299A (en) * | 2017-06-09 | 2018-12-18 | 京东方科技集团股份有限公司 | Data transmission method, device, system and storage medium |
| CN108539743A (en) * | 2018-05-19 | 2018-09-14 | 北京合众汇能科技有限公司 | A kind of high-efficiency and energy-saving type distribution terminal |
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