CN111900954A - Random phase noise digital extraction filtering method and device - Google Patents
Random phase noise digital extraction filtering method and device Download PDFInfo
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- CN111900954A CN111900954A CN202010493185.XA CN202010493185A CN111900954A CN 111900954 A CN111900954 A CN 111900954A CN 202010493185 A CN202010493185 A CN 202010493185A CN 111900954 A CN111900954 A CN 111900954A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H21/00—Adaptive networks
- H03H21/0012—Digital adaptive filters
- H03H21/002—Filters with a particular frequency response
- H03H21/0023—Comb filters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/26—Measuring noise figure; Measuring signal-to-noise ratio
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0248—Filters characterised by a particular frequency response or filtering method
- H03H17/0251—Comb filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H2017/0072—Theoretical filter design
- H03H2017/0081—Theoretical filter design of FIR filters
Abstract
The invention discloses a random phase noise digital extraction filtering method and a device, comprising a first input signal synchronous clock module and a second output signal synchronous clock module, wherein the first clock module and the second clock module adjust the clock frequency according to the input frequency measured by a digital phase-locked loop; the clock module I controls the high-speed phase noise digital stream input module, and the high-speed phase noise digital stream input module is transmitted to the variable-rate extraction filtering module through a data bus; the second clock module controls the output of the low-speed phase noise digital stream. The digital phase-locked loop is combined with a variable speed extraction filtering method, so that the high-speed phase noise digital signal is analyzed in real time, and the additional phase noise introduced by the clock jitter of the measurement system is reduced.
Description
Technical Field
The invention relates to the field of phase noise measurement, in particular to a method and a device for digitally extracting and filtering random phase noise.
Background
The digital decimation filtering is widely applied to the field of analog-to-digital conversion to realize signal analysis, in a phase noise digital measurement system, high-speed signals are directly subjected to analog-to-digital conversion, and noise power spectrum estimation is performed on the high-speed digital phase fluctuation signals demodulated by digital down-conversion. Different from the traditional digital signal extraction filtering, the digital stream signal to be processed of the digital phase noise measurement system is a random noise signal, and the design of an extraction filter is to avoid errors introduced when the sampling rate is reduced as much as possible; on the other hand, when the bandwidth of the input signal is any frequency point within the range of hundreds of megahertz, the phase noise power spectrum needs to analyze different fourier analysis frequency intervals, different extraction rates are set for random phase fluctuation signals, and the extraction rate of the extraction filter is a non-integer value, which puts higher requirements on the filter design.
In view of the above, the present invention provides a random phase fluctuation digital decimation filtering method, which designs a variable rate digital decimation filter for decimation filtering of a high-speed sampled digital signal to reduce uncertainty of a digitized phase noise measurement result.
Disclosure of Invention
The invention aims to provide a method and a device for digitally extracting and filtering random phase noise, which solve the problem of uncertainty of a digital phase noise measurement result.
In order to solve the technical problems, the invention adopts the following technical scheme: the device comprises a first input signal synchronous clock module and a second output signal synchronous clock module, wherein the first clock module and the second clock module adjust clock frequency according to input frequency measured by a digital phase-locked loop, the digital phase-locked loop is externally connected with a variable rate extraction filtering module, the variable rate extraction filtering module is connected with an FIR filtering module, and the FIR filtering module is sequentially connected with a low-speed phase noise digital stream output and a cross-correlation phase fluctuation spectrum estimation module;
the first clock module controls a high-speed phase noise digital stream input module, and the high-speed phase noise digital stream input module is transmitted to the variable-rate extraction filtering module through a data bus; and the second clock module controls the output of the low-speed phase noise digital stream.
Furthermore, the variable rate decimation filtering module comprises an integral filtering response module, a down-sampling rate module, a differential response filtering module and a decimation rate regulation control module; the integral filtering response module outputs signals to the down-sampling rate module, the down-sampling rate module is connected with the decimation rate adjustment control module, the decimation rate of the down-sampling rate module is dynamically adjusted in real time according to the decimation rate control signals output by the decimation rate adjustment control module, filtering response is carried out on an integral stage, and meanwhile, the down-sampling rate module outputs signals to the differential response filtering module; and the differential response filtering module is connected with a low-speed phase noise digital stream output.
Furthermore, the integral filtering response module is internally composed of a first adder, a second adder, a first delay module and a second delay module; the first adder receives an input high-speed digital signal, outputs a response signal by a first delay module in the first adder, and outputs the response signal to a second adder after signal accumulation; the second adder is coupled to the input of the second delay block and is responsive to the output signal of the second delay block, the first adder and the second adder delaying the summed output signals for output to the down-sampling rate block.
Furthermore, the differential response filtering module is internally composed of a node I, a node II, a third adder, a fourth adder, a third delay module and a fourth delay unit; the first node is connected with an output signal end of the down sampling rate module, the first node outputs signals to a third delay module and a third adder, the third adder responds to the output of the third delay module and outputs signals after addition to a fourth delayer and a fourth adder through the second node, and the fourth adder responds to the output of the fourth delayer and adds the signals to form low-speed phase noise digital stream output.
Furthermore, the variable rate decimation filtering module is a cascade integrator comb filter.
Furthermore, the digital phase-locked loop provides an extraction rate control signal for the FIR filtering module according to the measured rate of the input digital stream, so that the variable rate extraction filtering module performs extraction at a non-integer extraction rate, and performs filtering processing of the FIR filtering module after extraction filtering.
Further, the signal output by the low-speed phase noise digital stream controlled by the second clock module is specifically a signal with a rate 2 times the fourier analysis frequency of the phase fluctuation spectrum.
Further, firstly, sampling is carried out on input signals of the phase noise measurement system through a clock module I and a clock module I;
secondly, the digital phase-locked loop controls a variable speed extraction filtering module to extract a first control clock module and a first clock module, so that phase noise introduced by clock jitter and errors introduced by signal reconstruction after extraction and filtering are reduced;
thirdly, the variable-rate decimation filtering module designs an integral filtering response module of non-integer filtering decimation rate by using a loop cascade mode of an adder and a delayer, performs down-sampling processing on an integral filtering response stage by a down-sampling rate module design, performs differential filtering on a down-sampled digital stream signal by a differential response filtering module to form a phase fluctuation digital stream signal of Fourier analysis frequency 2 frequency multiplication sampling rate, and outputs and transmits the phase fluctuation digital stream signal to a cross-correlation phase fluctuation spectrum estimation module by low-speed phase noise digital stream;
and fourthly, performing cross-correlation power spectrum analysis on the phase fluctuation digital stream signal of the Fourier analysis frequency 2 frequency multiplication sampling rate by a cross-correlation phase fluctuation spectrum estimation module to realize phase noise digital analysis.
Further, the FIR filtering module is specifically a CIC filter.
Further, the FIR filtering module is a finite impulse response filter.
Compared with the prior art, the invention has the beneficial technical effects that:
the invention relates to a random phase noise digital extraction filtering method and a random phase noise digital extraction filtering device, which realize real-time analysis of a high-speed phase noise digital signal by combining a digital phase-locked loop with a variable-speed extraction filtering method, measure the change of the speed of an input high-speed digital signal and the speed of a low-speed output signal after extraction filtering in real time by using the digital phase-locked loop, and monitor and adaptively adjust the extraction rate of digital extraction filtering.
Because the frequency range of the input signal of the phase noise measurement system usually covers any single frequency point in the range of 1MHz to 500MHz, when the signal frequency is an integer multiple of the sampling clock frequency, the signal reconstruction cannot be performed, therefore, the sampling rate of the random phase fluctuation digital signal demodulated at the front end of the system can be adaptively adjusted according to the frequency of the input signal, the control module 1c provides a decimation rate adjustment control signal according to the sampling rate of the input digital stream, and the decimation rate control quantity is determined according to the clock difference of two clock signals and the sampling rate of the measured digital stream.
A digital phase-locked loop is adopted to control an extraction filter to extract a control module clock, so that phase noise caused by clock jitter is reduced, and errors caused by signal reconstruction after extraction filtering are reduced; designing an integral filter of a non-integer filtering decimation rate by utilizing a loop cascade mode of an adder and a delayer; the integral filtering response stage is subjected to down-sampling processing through the design of a down-sampling module, and the down-sampled digital stream signals of the integral filtering module are subjected to differential filtering to form phase fluctuation digital stream signals of Fourier analysis frequency 2 frequency multiplication sampling rate for cross-correlation power spectrum analysis, so that phase noise digital analysis is realized. The CIC decimation filter with adjustable decimation rate adaptively adjusts the decimation rate, thereby reducing errors introduced by decimation filtering during digital demodulation of random phase noise at the rear end of the digital measurement system.
In summary, the technical scheme provided by the invention realizes real-time analysis of high-speed phase noise digital signals by combining a digital phase-locked loop with a variable-speed extraction filtering method, measures the change of the input high-speed digital signal speed and the low-speed output signal speed after extraction filtering in real time by using the digital phase-locked loop, monitors and adaptively adjusts the extraction rate of digital extraction filtering, and reduces the additional phase noise introduced by measuring the clock jitter of the system. The method is not only suitable for a phase noise measurement system for analyzing the phase noise by the traditional quadrature mixing method, but also suitable for analyzing the digital phase noise signal in the phase noise measurement system with the system front end directly performing digitization, and improves the real-time performance of the signal processing of the phase noise measurement system.
Drawings
The invention is further illustrated in the following description with reference to the drawings.
FIG. 1 is a flow chart of a method and apparatus for digitally decimating and filtering random phase noise according to the present invention;
FIG. 2 is a flow chart of the variable rate decimation filtering module of the present invention;
FIG. 3 is a flow chart of the integrator-filter response module assembly of the present invention;
FIG. 4 is a flow diagram of the differential response filtering module of the present invention;
description of reference numerals: 1. a first clock module; 2. a digital phase-locked loop; 3. a high-speed phase noise digital stream input module; 4. a variable rate decimation filtering module; 5. an FIR filtering module; 6. outputting a low-speed phase noise digital stream; 7. a cross-correlation phase fluctuation spectrum estimation module;
401. an integral filter response module; 402. a down-sampling rate module; 403. a differential response filtering module; 404. an extraction rate adjustment control module;
a1, a first adder; a2, a second adder; a3, a third adder; a4, fourth adder; d1, a first delay module; d2, a second delay module; d3, a third delay module; d4, fourth delay; n1, node one; n2, node two.
Detailed Description
As shown in fig. 1-2, a method and apparatus for digitally decimation filtering of random phase noise includes a first input signal synchronous clock module 1 and a second output signal synchronous clock module 6, where the first clock module 1 and the second clock module 6 adjust a clock frequency according to an input frequency measured by a digital phase-locked loop 2. The digital phase-locked loop 2 is externally connected with a variable rate extraction filtering module 4, the frequencies of the clock module I1 and the clock module II 6 are jittered by the change of environmental factors such as temperature, and in order to reduce the accessory phase noise introduced by the system clock jitter, the digital phase-locked loop 2 is used for measuring the difference of the two clocks and providing an extraction rate adjustment control signal for the variable rate extraction filtering module 4 according to the measured clock rate difference.
The variable rate decimation filtering module 4 is connected with a finite impulse response filter, namely an FIR filtering module 5. The variable rate decimation filtering module 4 is a cascaded integrator-comb filter, specifically a CIC filter. The FIR filtering module 5 is connected with a low-speed phase noise digital stream output 7 and a cross-correlation phase fluctuation spectrum estimation module 8 in sequence.
The clock module I1 controls a high-speed phase noise digital stream input module 3, the high-speed phase noise digital stream input module 3 is transmitted to the variable-rate extraction filtering module 4 through a data bus to perform extraction filtering, and the sampling rate of an input digital stream signal needs to be adjusted along with the frequency of an analog signal to be detected. The second clock module 6 controls the low-speed phase noise digital stream output 7.
The variable rate decimation filtering module 4 includes an integral filter response module 401, a down-sampling rate module 402, a derivative response filtering module 403 and a decimation rate adjustment control module 404.
As shown in fig. 3, the integral filter response module 401 is internally composed of a first adder a1, a second adder a2, a first delay module d1 and a second delay module d 2; the first adder a1 receives the input high-speed digital signal, outputs the response signal by the first delay module d1 inside, and outputs the response signal to the second adder a2 after signal accumulation; the second adder a2 is coupled to an input of the second delay block d2 and is responsive to the output signal of the second delay block d 2. the first adder a1 and the second adder a2 delay the summed response output signals for output to the down-sampling module 402.
The down-sampling rate module 402 is connected to the decimation rate adjustment control module 404, and dynamically adjusts the decimation rate of the down-sampling rate module 402 in real time according to the decimation rate control signal output by the decimation rate adjustment control module 404, and performs filtering response to the integration stage, and at the same time, the down-sampling rate module 402 outputs a signal to the differential response filtering module 403.
As shown in fig. 4, the differential response filter module 403 is internally composed of a node one N1, a node two N2, a third adder a3, a fourth adder a4, a third delay module d3 and a fourth delay module d 4; the node one N1 is connected to the output signal end of the down sampling rate module 402, the node one N1 outputs a signal to the third delay module d3 and the third adder a3, the third adder a3 outputs the added signal in response to the third delay module d3 and outputs the added signal to the fourth delay module d4 and the fourth adder a4 through the node two N2, and the fourth adder a4 outputs the added signal in response to the fourth delay module d4 and forms the low speed phase noise digital stream output 7.
The digital phase-locked loop 2 provides an extraction rate control signal for the FIR filter module 5 according to the measured rate of the input digital stream, so that the variable rate extraction filter module 4 performs extraction at a non-integer extraction rate, and performs filtering processing of the FIR filter module 5 after extraction filtering.
The signal of the low-speed phase noise digital stream output 7 controlled by the second clock module 6 is specifically a signal with a rate 2 times the fourier analysis frequency of the phase fluctuation spectrum.
The steps of the invention comprise the following:
firstly, sampling input signals of a phase noise measurement system through a clock module I1 and a clock module II 6;
secondly, the digital phase-locked loop 2 controls the variable rate extraction filtering module 4 to extract the control clock module I1 and the clock module II 6, so that phase noise introduced by clock jitter and errors introduced by signal reconstruction after extraction filtering are reduced;
thirdly, the variable rate decimation filtering module 4 designs an integral filtering response module 401 with non-integer filtering decimation rate by using an adder and delayer loop cascade mode, performs down-sampling processing on an integral filtering response stage through a down-sampling rate module 402, performs differential filtering on a down-sampled digital stream signal through a differential response filtering module 403 to form a phase fluctuation digital stream signal with Fourier analysis frequency 2 and frequency multiplication sampling rate, and transmits the phase fluctuation digital stream signal to a cross-correlation phase fluctuation spectrum estimation module 8 through a low-speed phase noise digital stream output 7;
fourthly, the cross-correlation phase fluctuation spectrum estimation module 8 performs cross-correlation power spectrum analysis on the phase fluctuation digital stream signal of the Fourier analysis frequency 2 frequency multiplication sampling rate to realize phase noise digital analysis.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solutions of the present invention can be made by those skilled in the art without departing from the spirit of the present invention, and the technical solutions of the present invention are within the scope of the present invention defined by the claims.
Claims (10)
1. A random phase noise digital decimation filtering device, characterized in that: the device comprises a first input signal synchronous clock module (1) and a second output signal synchronous clock module (6), wherein the first clock module (1) and the second clock module (6) adjust the clock frequency according to the input frequency measured by a digital phase-locked loop (2), the digital phase-locked loop (2) is externally connected with a variable rate extraction filtering module (4), the variable rate extraction filtering module (4) is connected with an FIR filtering module (5), and the FIR filtering module (5) is sequentially connected with a low-speed phase noise digital stream output (7) and a cross-correlation phase fluctuation spectrum estimation module (8);
the clock module I (1) controls a high-speed phase noise digital stream input module (3), and the high-speed phase noise digital stream input module (3) is transmitted to the variable-rate decimation filtering module (4) through a data bus; and the second clock module (6) controls the low-speed phase noise digital stream output (7).
2. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: the variable rate decimation filtering module (4) comprises an integral filtering response module (401), a down-sampling rate module (402), a differential response filtering module (403) and a decimation rate regulation control module (404); the integral filtering response module (401) outputs signals to the down-sampling rate module (402), the down-sampling rate module (402) is connected with the decimation rate adjustment control module (404), the decimation rate of the down-sampling rate module (402) is dynamically adjusted in real time according to the decimation rate control signals output by the decimation rate adjustment control module (404), filtering response is carried out on an integral stage, and meanwhile, the down-sampling rate module (402) outputs signals to the differential response filtering module (403); the differential response filtering module (403) is connected with a low-speed phase noise digital stream output (7).
3. The random phase noise digitized decimation filtering apparatus according to claim 2, wherein: the integral filtering response module (401) is internally composed of a first adder (a1), a second adder (a2), a first delay module (d1) and a second delay module (d 2); the first adder (a1) receives input high-speed digital signals, outputs response signals by a first delay module (d1) inside the first adder, and outputs the response signals to the second adder (a2) through signal accumulation; a second adder (a2) is coupled to an input of the second delay block (d2) and is responsive to the output signal of the second delay block (d2), and the first adder (a1) and the second adder (a2) delay the summed output signals for output to the down-sampling rate block (402).
4. The random phase noise digitized decimation filtering apparatus according to claim 2, wherein: the differential response filtering module (403) is internally composed of a node one (N1), a node two (N2), a third adder (a3), a fourth adder (a4), a third delay module (d3) and a fourth delay (d4) unit; the node one (N1) is connected to the output signal terminal of the down-sampling rate module (402), the node one (N1) outputs a signal to a third delay module (d3) and a third adder (a3), the third adder (a3) outputs the added signal to the fourth delay (d4) and the fourth adder (a4) through a node two (N2) in response to the output of the third delay module (d3), and the fourth adder (a4) outputs the added signal to the fourth delay (d4) and the fourth adder (a4) in response to the output of the fourth delay (d4) to form the low-speed phase noise digital stream output (7).
5. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: the variable rate decimation filtering module (4) is a cascade integrator comb filter.
6. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: and the digital phase-locked loop (2) provides an extraction rate control signal for the FIR filtering module (5) according to the measured speed of the input digital stream, so that the variable speed extraction filtering module (4) performs extraction at a non-integer extraction rate, and performs filtering processing of the FIR filtering module (5) after extraction filtering.
7. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: the signal of the low-speed phase noise digital stream output (7) controlled by the second clock module (6) is specifically a signal with a rate 2 times the Fourier analysis frequency of the phase fluctuation spectrum.
8. A method for digitally decimating random phase noise, the method comprising the steps of:
firstly, sampling input signals of a phase noise measurement system through a clock module I (1) and a clock module II (6);
secondly, the digital phase-locked loop (2) controls the variable rate extraction filtering module (4) to extract and control the clock module I (1) and the clock module II (6), so that phase noise introduced by clock jitter and errors introduced by signal reconstruction after extraction filtering are reduced;
thirdly, a variable-rate decimation filtering module (4) designs an integral filtering response module (401) of non-integer filtering decimation rate by using a mode of loop cascade of an adder and a delayer, performs down-sampling processing on an integral filtering response stage by a down-sampling rate module (402), performs differential filtering on a down-sampled digital stream signal by a differential response filtering module (403) to form a phase fluctuation digital stream signal of Fourier analysis frequency 2 frequency multiplication sampling rate, and transmits the phase fluctuation digital stream signal to a cross-correlation phase fluctuation spectrum estimation module (8) by a low-speed phase noise digital stream output (7);
fourthly, a cross-correlation phase fluctuation spectrum estimation module (8) carries out cross-correlation power spectrum analysis on the phase fluctuation digital stream signal of the Fourier analysis frequency 2 frequency multiplication sampling rate to realize phase noise digital analysis.
9. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: the FIR filtering module (5) is specifically a CIC filter.
10. The random phase noise digitized decimation filtering apparatus according to claim 1, wherein: the FIR filtering module (5) is a finite impulse response filter.
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| CN104393854A (en) * | 2014-12-04 | 2015-03-04 | 华侨大学 | FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof |
| CN110716092A (en) * | 2019-10-22 | 2020-01-21 | 上海交通大学 | Phase noise measuring device and measuring method based on laser frequency discrimination and cross-correlation processing |
| CN110932783A (en) * | 2019-12-31 | 2020-03-27 | 中国电子科技集团公司第三十四研究所 | Clock frequency transmission device capable of resisting optical fiber disturbance |
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| US20070192392A1 (en) * | 2006-02-16 | 2007-08-16 | Sigma Tel, Inc. | Decimation filter |
| CN104393854A (en) * | 2014-12-04 | 2015-03-04 | 华侨大学 | FPGA-based time division multiplexing cascaded integrator-comb decimation filter and realization method thereof |
| CN110716092A (en) * | 2019-10-22 | 2020-01-21 | 上海交通大学 | Phase noise measuring device and measuring method based on laser frequency discrimination and cross-correlation processing |
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