CN111899148B - Frame data processing method and system and storage medium - Google Patents

Frame data processing method and system and storage medium Download PDF

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Publication number
CN111899148B
CN111899148B CN202010629541.6A CN202010629541A CN111899148B CN 111899148 B CN111899148 B CN 111899148B CN 202010629541 A CN202010629541 A CN 202010629541A CN 111899148 B CN111899148 B CN 111899148B
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frame data
address
lookup table
bit
processing
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CN111899148A (en
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饶洋
彭乐立
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TCL China Star Optoelectronics Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)

Abstract

The invention provides a frame data processing method, a system and a storage medium, wherein the frame data processing method is implemented by a processor, the frame data of a display card can be read in real time, address conversion, address searching of a lookup table and a processing module of a picture are implemented by the processor, the conversion speed is increased, and the image processing module can use different algorithms for processing, so that the user-defined function is realized.

Description

Frame data processing method and system and storage medium
Technical Field
The present invention relates to the field of display technologies, and in particular, to a method and system for processing frame data, and a storage medium.
Background
As shown in fig. 1, in the conventional display Panel technology, it is difficult to read image data output by a Graphics Processing Unit (GPU) to a main control chip of a display, process the image integrated in the chip, and output the processed image data to a display Panel (Panel) for display, if an algorithm needs to be changed or user definition needs to be implemented.
The image processing algorithm is fixedly integrated in a main control chip of the display, and the display is produced in batch. Therefore, only the set algorithm can be realized, and the user-defined algorithm and effect cannot be realized.
Therefore, there is an urgent need to provide a method, a system, and a storage medium for processing frame data, which can solve the problem that a user cannot customize.
Disclosure of Invention
The invention aims to provide a frame data processing method, a frame data processing system and a storage medium, wherein the frame data processing method is implemented by a processor, so that user-defined processing can be realized, and the address conversion speed is increased.
In order to achieve the object of the present invention, the present invention provides a method for processing frame data, comprising: an acquisition step of acquiring real-time frame data, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits; judging whether the sub-pixel I in the real-time frame data exceeds I, if so, continuing to execute the acquiring step, otherwise, executing the following steps; an address aggregation step, namely aggregating original values Ri (i), gi (i) and Bi (i) of the first bit channel into an address index value Ad (i) of a second bit channel, wherein the second bit channel is 3m bits; searching, namely searching a corresponding lookup table address Va (i) according to the address index value Ad (i); an image processing step of searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values; an address classifying step of classifying the lookup table address Va (i) to obtain frame data Ro (i), go (i), bo (i) of the first bit lane; and a storing step of storing the frame data of the one-bit channel in the address classifying step and the lookup table address Va (i) into a buffer.
Further, in the step of obtaining, the real-time frame data is obtained from a graphics card GPU.
Further, the frame data processing method further includes: a back transmission step, namely, the frame data of the buffer area are transmitted back to the graphics card GPU and updated; and a display step of displaying the updated frame data in the panel.
Further, the address index value Ad (i) has a calculation formula Ad (i) = (Ri (i) < <2 m) + (Gi (i) < < m) +bi (i).
Further, in the address classifying step, the calculation formula of the frame data Ro (i), go (i), bo (i) of the first bit lane is: ro (i) =va (i) > >2m, go (i) = (Va (i) - (Ro (i) < <2 m)) > m, bo (i) =va (i) - ((Va (i) > > m) < < m).
Further, the address index value Ad (i) has a calculation formula Ad (i) = (Ri (i) > >2 m) + (Gi (i) > > m) +bi (i).
Further, in the address classifying step, the calculation formula of the frame data Ro (i), go (i), bo (i) of the first bit lane is: ro (i) =va (i) < <2m, go (i) = (Va (i) - (Ro (i) > >2 m)) < m, bo (i) =va (i) - ((Va (i) < < m) > > m).
The present invention provides a processing system for frame data, comprising at least one computer comprising at least one processor and at least one memory storing memory executable instructions, the computer executing the instructions to: acquiring real-time frame data of a graphics card GPU, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original numerical value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits; judging whether the number I of the sub-pixels in the real-time frame data exceeds I, if so, continuing to execute the previous step, and if not, executing the following steps; aggregating the original values Ri (i), gi (i) and Bi (i) of the first bit-lane into an address index value Ad (i) of a second bit-lane, the second bit-lane being 3m bits; searching a corresponding lookup table address Va (i) according to the address index value Ad (i); searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values; classifying the lookup table address Va (i) to obtain frame data of the first bit channel, i.e., ro (i), go (i), bo (i); storing the frame data of the first bit lane and the lookup table address Va (i) into a buffer; the frame data of the buffer area are transmitted back to the graphics card GPU and updated; the updated frame data is displayed in the panel.
Further, the computer also comprises a panel, a memory area and a circuit motherboard; the processor and the display card are integrated on the circuit motherboard; the graphics card GPU comprises the buffer area.
The present invention also provides a storage medium storing a computer program for executing the frame data processing method.
The beneficial effects of the invention are as follows: the invention provides a frame data processing method, a system and a storage medium, wherein the frame data processing method is executed by a processor, the frame data of a display card can be read in real time, address conversion, address searching of a lookup table and a picture processing module are carried out by the processor, the conversion speed is increased, and the image processing module can use different algorithms for processing, so that the user-defined function is realized.
Drawings
The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a functional block diagram of prior art frame data processing.
Fig. 2 is a flowchart of a frame data processing method provided by the present invention.
Fig. 3 is a functional block diagram of frame data processing according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
As shown in fig. 2, the present invention provides a method for processing frame data, which is executed by a processor, comprising the following steps.
S1, acquiring real-time frame data, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits.
In the step of obtaining, the real-time frame data is obtained from a graphics card GPU. The first bit lane, i.e. the number of bits stored by the physical address of the original value, is typically stored in binary form, i.e. the binary number of bits of the original values Ri (i), gi (i), bi (i) is m bits, e.g. 8 bits or 12 bits.
S2, judging whether the number I of the sub-pixels in the real-time frame data exceeds I, if so, continuing to execute the acquisition step, and if not, executing the following steps.
In the panel display, one frame of data includes consecutive I sub-pixels, and one frame of data is picture-displayed by displaying the I sub-pixels one by one. Step S2 is mainly the function of the frame data traversed, and each sub-pixel in the frame data is processed as follows.
S3, an address aggregation step, namely aggregating the original values Ri (i), gi (i) and Bi (i) of the first bit channel into an address index value Ad (i) of a second bit channel, wherein the second bit channel is 3m bits.
And the address aggregation step is used for aggregating the original values Ri (i), gi (i) and Bi (i) of the first bit channel, so that the bit number of the second bit channel formed by aggregation is 3m bits, namely the physical address bit number is 3m bits, and the second bit channel is stored in a binary form.
S4, searching the corresponding lookup table address Va (i) according to the address index value Ad (i).
The size of the memory can be reduced conveniently by searching the corresponding address, and the working efficiency of the processor can be increased conveniently and rapidly.
S5, an image processing step, namely searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values.
S6, an address classifying step, namely classifying the lookup table address Va (i) to obtain frame data of the first bit channel, namely Ro (i), go (i), and Bo (i), wherein the lookup table address Va (i) is mainly separated, so that the lookup table address Va (i) is conveniently stored in the same format.
And S7, a storage step, namely storing the frame data of the one-bit channel and the lookup table address Va (i) in the address classification step into a buffer area.
And S8, displaying the updated frame data in the panel.
In an embodiment, the formula of the address index value Ad (i) is Ad (i) = (Ri (i) < <2 m) + (Gi (i) < < m) +bi (i). In the address classifying step, the calculation formula of the frame data Ro (i), go (i), bo (i) of the first bit lane is: ro (i) =va (i) > >2m, go (i) = (Va (i) - (Ro (i) < <2 m)) > m, bo (i) =va (i) - ((Va (i) > > m) < < m).
In another embodiment, the calculation formula of the address index value Ad (i) is:
ad (i) = (Ri (i) > >2 m) + (Gi (i) > > m) +bi (i). In the address classifying step, the calculation formula of the frame data Ro (i), go (i), bo (i) of the first bit lane is: ro (i) =va (i) < <2m, go (i) = (Va (i) - (Ro (i) > >2 m)) < m, bo (i) =va (i) - ((Va (i) < < m) > > m).
The invention provides a frame data processing method, which uses a processor to execute the frame data processing method, can read the frame data of a display card in real time, and carries out address conversion, address searching of a lookup table and a picture processing module through the processor, thereby increasing the conversion speed, and the image processing module can use different algorithms for processing to realize the user-defined function.
As shown in fig. 3, the present invention also provides a processing system of frame data, including at least one computer, the computer including at least one processor and at least one memory. The processor is a CPU, which is used for calculating or sending instructions, and the memory is a hard disk.
The computer also comprises a panel and a circuit board, wherein the processor, the memory and the GPU are integrated on the circuit board. The panel is a display, and the processor and the display card are arranged in the host. The graphics card GPU comprises the buffer area. The processor includes the image processing module. The memory stores a look-up table. The circuit board is generally disposed in a host computer.
Wherein the memory stores memory-executable instructions that are executed by the computer to perform the operations of:
and acquiring real-time frame data of the graphics card GPU, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original numerical value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits.
And judging whether the number I of the sub-pixels in the real-time frame data exceeds I, if so, returning to the previous step, and if not, executing the following steps.
The original values Ri (i), gi (i) and Bi (i) of the first bit-lane are aggregated into an address index value Ad (i) of a second bit-lane, which is 3m bits.
And searching a corresponding lookup table address Va (i) according to the address index value Ad (i).
And searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values. The image processing module user can select different algorithms to operate according to the user, so that user definition is realized.
Classifying the lookup table address Va (i) to obtain frame data Ro (i), go (i), bo (i) of the first bit lane.
The frame data of the first bit lane and the lookup table address Va (i) are stored into a buffer.
And the frame data of the buffer area are transmitted back to the graphics card GPU and updated.
The updated frame data is displayed in the panel.
The present invention also provides a storage medium storing a computer program for executing the frame data processing method.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of the above examples is only for aiding in understanding the technical solution of the present invention and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (8)

1. A method of processing frame data, comprising:
an acquisition step of acquiring real-time frame data, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits;
judging, to judge whether the number I of the sub-pixels in the real-time frame data exceeds I, if yes, continuing to execute the obtaining step, otherwise, executing the following steps;
an address aggregation step, namely aggregating original values Ri (i), gi (i) and Bi (i) of the first bit channel into an address index value Ad (i) of a second bit channel, wherein the second bit channel is 3m bits;
searching, namely searching a corresponding lookup table address Va (i) according to the address index value Ad (i);
an image processing step of searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values;
an address classifying step of classifying the lookup table address Va (i) to obtain frame data Ro (i), go (i), bo (i) of the first bit lane;
a storing step of storing the frame data of the first bit lane in the address classifying step and the lookup table address Va (i) into a buffer;
the calculation formula of the address index value Ad (i) is Ad (i) = (Ri (i) < <2 m) + (Gi (i) < < m) +Bi (i), or Ad (i) = (Ri (i) > >2 m) + (Gi (i) > > m) +Bi (i).
2. The method for processing frame data according to claim 1, wherein,
in the step of obtaining, the real-time frame data is obtained from a graphics card GPU.
3. The method for processing frame data according to claim 2, further comprising:
a back transmission step, namely, the frame data of the buffer area are transmitted back to the graphics card GPU and updated;
and a display step of displaying the updated frame data in the panel.
4. The method for processing frame data according to claim 1, wherein,
when the calculation formula of the address index value Ad (i) is Ad (i) = (Ri (i) < <2 m) + (Gi (i) < < m) +bi (i), in the address classification step, the calculation formula of the frame data Ro (i), go (i), and Bo (i) of the first bit lane is:
Ro(i)=Va(i)>>2m,
Go(i)=(Va(i)-(Ro(i)<<2m))>>m,
Bo(i)=Va(i)-((Va(i)>>m)<<m)。
5. the method for processing frame data according to claim 1, wherein,
when the calculation formula of the address index value Ad (i) is Ad (i) = (Ri (i) > >2 m) + (Gi (i) > > m) +bi (i), in the address classification step, the calculation formula of the frame data Ro (i), go (i), and Bo (i) of the first bit lane is:
Ro(i)=Va(i)<<2m,
Go(i)=(Va(i)-(Ro(i)>>2m))<<m,
Bo(i)=Va(i)-((Va(i)<<m)>>m)。
6. a system for processing frame data, comprising at least one computer, the computer comprising at least one processor and at least one memory, the memory storing executable instructions, the computer executing the instructions to:
acquiring real-time frame data of a graphics card GPU, wherein the real-time frame data comprises I continuous sub-pixels, each sub-pixel comprises an original numerical value Ri (I), gi (I) and Bi (I) of a first bit channel, and the first bit channel is m bits;
judging whether the number I of the sub-pixels in the real-time frame data exceeds I, if so, returning to the previous step, and if not, executing the following steps;
aggregating the original values Ri (i), gi (i) and Bi (i) of the first bit-lane into an address index value Ad (i) of a second bit-lane, the second bit-lane being 3m bits;
searching a corresponding lookup table address Va (i) according to the address index value Ad (i);
searching a corresponding lookup table according to the lookup table address Va (i), and processing the lookup table by an image processing module to obtain RGB values;
classifying the lookup table address Va (i) to obtain frame data Ro (i), go (i), bo (i) of the first bit lane;
storing the frame data of the first bit lane and the lookup table address Va (i) into a buffer;
the frame data of the buffer area are transmitted back to the graphics card GPU and updated;
displaying the updated frame data in a panel;
the calculation formula of the address index value Ad (i) is Ad (i) = (Ri (i) < <2 m) + (Gi (i) < < m) +Bi (i), or Ad (i) = (Ri (i) > >2 m) + (Gi (i) > > m) +Bi (i).
7. The frame data processing system of claim 6, wherein,
the computer also comprises a panel, a memory area and a circuit motherboard;
the processor and the display card are integrated on the circuit motherboard;
the graphics card GPU comprises the buffer area.
8. A storage medium storing a computer program for executing the frame data processing method according to any one of claims 1 to 5.
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CN110012346A (en) * 2019-03-26 2019-07-12 合肥杰发科技有限公司 User applies method and apparatus, the equipment of the frame data in quick obtaining frame buffer

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Publication number Priority date Publication date Assignee Title
CN1868211A (en) * 2003-03-28 2006-11-22 微软公司 Accelerating video decoding using a graphics processing unit
CN1545254A (en) * 2003-11-13 2004-11-10 中兴通讯股份有限公司 A method of fast data packet filtering
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