CN111898748B - Fractional-order memristive bridge circuit, and synaptic circuit and neuron circuit formed by same - Google Patents

Fractional-order memristive bridge circuit, and synaptic circuit and neuron circuit formed by same Download PDF

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CN111898748B
CN111898748B CN202010757451.5A CN202010757451A CN111898748B CN 111898748 B CN111898748 B CN 111898748B CN 202010757451 A CN202010757451 A CN 202010757451A CN 111898748 B CN111898748 B CN 111898748B
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蒲亦非
余波
何秋燕
袁晓
张妮
王竹
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Abstract

The invention relates to the field of memristors, and discloses a fractional-order memristor bridge circuit, and a synapse circuit and a neuron circuit which are formed by the fractional-order memristor bridge circuit, so that more accurate neurosynaptic weighting is realized. The voltage-controlled power supply comprises two v-order incremental capacitive memory reactors, two integrated operational amplifiers, two first resistors and two second resistors; wherein the increments of the two incremental capacitive memantines are opposite; one ends of the two first resistors are grounded, the other ends of the two first resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, one ends of the two second resistors are connected with the pulse input end in parallel, the other ends of the two second resistors are connected with the positive input ends of the two integrated operational amplifiers respectively, the negative electrodes of the two capacitive memory resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, and the positive electrodes of the two capacitive memory resistors are connected with the positive input ends of the two integrated operational amplifiers respectively. The invention is applicable to neural synapse weighting.

Description

Fractional-order memristive bridge circuit, and synaptic circuit and neuron circuit formed by same
Technical Field
The invention relates to the field of memristors, in particular to a fractional-order memristor bridge circuit, and a synapse circuit and a neuron circuit formed by the fractional-order memristor bridge circuit.
Background
In 1971, professor zeila, berkeley, california university, proposed memristors to characterize the relationship between charge and magnetic flux. In addition to three basic circuit elements, resistance, capacitance and inductance, memristance is a novel nonlinear circuit element with memory and synapse-like properties. Fractional calculus has become an important and novel branch of mathematical analysis today. Fractional calculus, due to its long-term memory, non-locality and weak singularities, has been developed as a novel and useful tool in many scientific fields, such as diffusion processes, viscoelastic theory, fractal dynamics, fractional order control, image processing, impedance, fractional order memristions and neural networks. The basic feature of fractional calculus is that it extends the concepts of integer order difference and riemann summation. The characteristics of fractional calculus are very different from those of classical integer calculus. For example, in addition to being based on the Caputo definition, the fractional differential of the Heaviside function is non-zero, while its integer order differential must be zero. According to the Chua's axiom element system, the constitutive relation, the logical consistency, the axiom integrity and the form symmetry are considered, and fractional memristions should exist. Fractional order memristors are of two types: the capacitive fractional order memristor and the inductive fractional order memristor respectively correspond to a capacitive fractional reactance and an inductive fractional reactance. The electrical characteristics of the capacitive fractional memristor are intermediate between those of the capacitor and the memristor. In a similar manner, the electrical properties of the inductive fractional order memristors are intermediate between the inductance and the memristance.
The terms of the memory reactance and the memory reactance value are short for the fractional order memory resistor and the fractional order memory resistance value respectively. Pujia also does not have to deduct the impedance function of the arbitrary order driving point of the capacitive memory reactance and the inductive memory reactance respectively, namely
Figure BDA0002612064750000011
And
Figure BDA0002612064750000012
where c and l represent capacitance and inductance, respectively, and s isVariable laplace, h(s) ═ L { h [ q (t)]Is the transfer function of the memristor in the constituent memristor (the voltage-current relationship across the memristor is v)in(t)＝r[q(t)]iin(t)＝h[q(t)]*iin(t)，r[q(t)]Memory resistance), v ═ η + p is the operation order (v ≧ 0: if v is a positive integer, thenηV-1 andp1 is ═ 1; in addition to this, the present invention is,
Figure BDA0002612064750000013
and 0. ltoreq. p<1). Putiao et al also propose fingerprint features of memory antibodies and realize the first memory antibody by hardware. In addition, the memantine can also be divided into a positive increment memantine and a negative increment memantine. Thus, the concept of memristance has been generalized from the first classical integer-order memristance to the fractional-order memristance.
The neurosynaptic weight refers to the strength of the connection between two neurons. Synaptic weights change according to recent neuronal activity, a process called synaptic plasticity. Synaptic plasticity is the adaptation of neurons in the brain during learning. Research in the field of synapse weighting has met with only limited success due to the lack of suitable means to implement synapses. Kim et al propose a memristive bridge circuit consisting of four identical memristors to achieve zero, negative, and positive synaptic weights. Adhikari et al propose a simulation hardware architecture and corresponding learning scheme for a multi-layer neural network based on memristive bridge synapses. Sah et al propose a simple and compact memristive bridge-based circuit to achieve signed synaptic weighting in neuronal cells. Li et al propose a memcapacitor bridge circuit comprising four identical memcapacitors. Wang et al propose a spintronic memristive bridge synaptic circuit. However, in the mathematical nature, the memristive bridge synaptic circuits above all implement neural synaptic weighting based on memristions of integer order. The integer order memristive bridge circuit realizes linear weighting of input pulse signals and is not suitable for describing neural synapse weighting.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a fractional order memristive bridge circuit, and synaptic and neuronal circuits comprised thereof, are provided in order to achieve more accurate neurosynaptic weighting.
In order to achieve the purpose, the invention adopts the technical scheme that:
in one aspect, the invention provides a fractional order memristor bridge circuit for neural synapse weighting, comprising two v-order incremental capacitive memristors, two integrated operational amplifiers, two first resistors and two second resistors; wherein v is a positive real number, and the increment of the two v-order incremental capacitive memberships is opposite;
one ends of the two first resistors are grounded, the other ends of the two first resistors are connected with negative input ends of the two integrated operational amplifiers respectively, one ends of the two second resistors are connected with a pulse input end in parallel, the other ends of the two second resistors are connected with positive input ends of the two integrated operational amplifiers respectively, negative electrodes of the two incremental capacitive memory-sharing resistors are connected with negative input ends of the two integrated operational amplifiers respectively, and positive electrodes of the two incremental capacitive memory-sharing resistors are connected with positive input ends of the two integrated operational amplifiers respectively.
In another aspect, the present invention provides a fractional order memristive bridge synapse circuit, including a subtractor circuit, a first inverse proportion device circuit and the fractional order memristive bridge circuit, where two output terminals of the fractional order memristive bridge circuit are respectively connected to two input terminals of the subtractor circuit, and an output terminal of the subtractor circuit is connected to an input terminal of the inverse proportion device circuit.
Specifically, the subtractor circuit comprises a third integrated operational amplifier, two third resistors and two fourth resistors, two output ends of the fractional order memristor bridge circuit are respectively connected with one ends of the two third resistors, the other ends of the two third resistors are respectively connected with a positive input end and a negative input end of the third integrated operational amplifier, one ends of the two fourth resistors are respectively connected with the positive input end and the negative input end of the third integrated operational amplifier, the other end of one of the fourth resistors is grounded, and the other end of the other fourth resistor is connected with an output end of the third integrated operational amplifier.
Specifically, the first inverse proportion circuit comprises a fourth integrated operational amplifier, a fifth resistor, a sixth resistor and a seventh resistor, wherein the seventh resistor is a load resistor of the first inverse proportion circuit; one end of the fifth resistor is connected with the output end of the subtractor circuit, the other end of the fifth resistor is simultaneously connected with one end of the seventh resistor and the negative input end of the fourth integrated operational amplifier, one end of the sixth resistor is grounded, the other end of the sixth resistor is connected with the positive input end of the fourth integrated operational amplifier, and the output end of the fourth integrated operational amplifier is connected with the other end of the seventh resistor.
In another aspect, the invention further provides a fractional order memristive bridge neuron circuit, which includes a bias pulse end, a second inverse proportion circuit and the fractional order memristive bridge synapse circuit; the structure of the second inverse proportion device circuit is the same as that of the first inverse proportion device circuit in the fractional order memristive bridge synaptic circuit, the second inverse proportion device circuit and the first inverse proportion device circuits in all the fractional order memristive bridge synaptic circuits share the load resistor, the output end of the second inverse proportion device circuit is simultaneously connected with the output ends of all the fractional order memristive bridge synaptic circuits, and the input end of the second inverse proportion device circuit is connected with the bias pulse end.
The invention has the beneficial effects that: the synaptic weights of the pulse-based memristive bridge circuit are nonlinear functions with long-term memory, so that the nonlinear weights of input signals are realized, and the memristive bridge circuit is more suitable for describing the neural synaptic weights. It can be seen that the final fractional-order memristor-based neural synapse weighting circuit of the present invention can more effectively describe the cellular mechanisms of learning and memory, and is superior to the conventional integer-order memristor-based neural synapse weighting circuit.
Drawings
FIG. 1 is a pulse-based memristive bridge circuit diagram;
FIG. 2 is a diagram of memristive bridge synapse circuitry;
FIG. 3 is a circuit diagram of a memristive bridge neuron;
FIG. 4 is an architectural diagram of a memristive neural network circuit;
FIG. 5 is a graph of output voltage of a pulse-based memristive bridge;
FIG. 6 is a graph of output voltage of a pulse-based memristive bridge;
FIG. 7 is a graph of the output voltage of a pulse-based memristive bridge circuit, where the duty cycle of the input pulses is equal to 50%;
FIG. 8 is a graph of the output voltage of a pulse-based memristive bridge circuit, where the duty cycle of the input pulses is equal to 70%. .
Detailed Description
In order to realize the neural synapse weighting by the fractional memristance, the embodiment firstly discloses a pulse-based memristor (i.e. the fractional memristance) bridge circuit, as shown in fig. 1, comprising two v (v is a positive real number) order capacitive positive and negative incremental memristors (v is a positive real number)
Figure BDA0002612064750000031
And
Figure BDA0002612064750000032
) Two integrated operational amplifiers
Figure BDA0002612064750000033
And
Figure BDA0002612064750000034
two resistance values are rsFirst resistor, two resistors rpThe second resistance of (1).
Figure BDA0002612064750000035
Is a negative incremental memoborant, and
Figure BDA0002612064750000036
is a positive increment memantine. One end of each of the two first resistors is grounded, the other end of each of the two first resistors is connected with the negative input ends of the two integrated operational amplifiers, one end of each of the two second resistors is connected with the pulse input end in parallel, and the other end of each of the two second resistors is connected with the two integrated operational amplifiersThe positive input ends of the two integrated operational amplifiers are respectively connected with the positive electrodes of the two capacitive memory-sharing reactors. Two integrated operational amplifiers
Figure BDA0002612064750000037
And
Figure BDA0002612064750000038
two identical voltage-current converters are respectively constructed, and according to Kirchhoff Current Law (KCL) and Kirchhoff Voltage Law (KVL), the following relation is obtained:
Figure BDA0002612064750000041
Figure BDA0002612064750000042
Figure BDA0002612064750000043
Figure BDA0002612064750000044
Figure BDA0002612064750000045
Figure BDA0002612064750000046
input voltage in the formula
Figure BDA0002612064750000047
Is a positive or negative pulse signal. Whether or not
Figure BDA0002612064750000048
Is either positive or negative in polarity,
Figure BDA0002612064750000049
the change trend of memory resistance value and
Figure BDA00026120647500000410
the opposite is true. v. of0Is that
Figure BDA00026120647500000411
And
Figure BDA00026120647500000412
the initial voltage drop across. Pulse-based output voltage of memristive bridge circuit
Figure BDA00026120647500000413
Equal to the voltage difference between points B and a, and therefore, from equations (1) - (6),
Figure BDA00026120647500000414
can be expressed as:
Figure BDA00026120647500000415
because of H(s) ═ L { h [ q (t)]The reactance of the memristor in the incremental capacitive memantine is formed, so that synaptic weights of the pulse-based memantine bridge circuit are nonlinear functions with long-term memory, and nonvolatile storage and nonlinear weighting of the weights can be realized in the artificial neural network. The memristor bridge circuit comprises two positive and negative incremental capacitive memristors, and programmed pulses are input
Figure BDA00026120647500000416
The output voltage of the pulse-based memristive anti-bridge circuit can be controlled
Figure BDA00026120647500000417
Set as requiredThe value of (c):
Figure BDA00026120647500000418
the pulse-based memristor bridge circuit shown in fig. 1 is realized by two v-order positive and negative increment capacitive memristors, and in practical application, a first resistor rpAnd a second resistor rsDifferent parameters can be selected, and the output voltage of the memristor bridge circuit based on the pulse
Figure BDA00026120647500000419
Comprises the following steps:
Figure BDA00026120647500000420
FIG. 2 shows an embodiment of a memristive bridge synapse circuit, including the above pulse-based memristive bridge circuit, two integrated operational amplifiers
Figure BDA00026120647500000421
And
Figure BDA00026120647500000422
two resistance values are rtThe third resistor and the two resistors have the resistance value rfA fourth resistor having a resistance of
Figure BDA00026120647500000423
A fifth resistor having a resistance of
Figure BDA00026120647500000424
A sixth resistor of a resistance rLThe seventh resistor of (1). Third resistor, fourth resistor and integrated operational amplifier
Figure BDA0002612064750000051
Form a subtracter, a fifth resistor, a sixth resistor, a seventh resistor and an integrated operational amplifier
Figure BDA0002612064750000052
Form an inverse proportion device, an operational amplifier
Figure BDA0002612064750000053
And voltage-current conversion is realized at the inverting input terminal. r is a radical of hydrogenLIs a load resistance, and is,
Figure BDA0002612064750000054
is flowed through rLThe load current of (1). Thus, in
Figure BDA0002612064750000055
And
Figure BDA0002612064750000056
under the action of the catalyst alone, the following are obtained:
Figure BDA0002612064750000057
in addition, for
Figure BDA0002612064750000058
From equations (7) and (10), there are obtained:
Figure BDA0002612064750000059
load current
Figure BDA00026120647500000510
Only depend on
Figure BDA00026120647500000511
And a load resistance rLIs irrelevant. Therefore, the memristive bridge synapse circuit actually implements a differential current source.
FIG. 3 shows an embodiment of a memristive bridge neuron circuit, which includes a second inverse proportion device circuit and n (n > 1) fractional-order memristive bridge synapse circuits, the second inverse proportion device circuitThe structure of the circuit is the same as that of the first inverse proportion circuit in the synaptic circuits of the fractional-order memristive bridges, and the second inverse proportion circuit shares the load resistor r with the first inverse proportion circuit in all the synaptic circuits of the fractional-order memristive bridgesLThe output end of the second inverse proportion circuit is simultaneously connected with the output ends of all fractional order memristive bridge synapse circuits, and the input end of the second inverse proportion circuit is connected with a bias pulse end. Two memantines in FIG. 3: (
Figure BDA00026120647500000512
And
Figure BDA00026120647500000513
) And four integrated operational amplifiers
Figure BDA00026120647500000514
And
Figure BDA00026120647500000515
) A first memristive anti-synaptic circuit is constructed.
Figure BDA00026120647500000516
And
Figure BDA00026120647500000517
constructing the nth memristive anti-synapse circuit, integrating the operational amplifier An+1A cell bias circuit is implemented. v. ofb(t) is the cell bias voltage (voltage source bias pulse). i.e. iL(t) is the flow through rLThe load current of (1). Thus, according to KCL, there are obtained:
Figure BDA00026120647500000518
Figure BDA00026120647500000519
Figure BDA00026120647500000520
where i ∈ [1, n ]]Is a positive integer. As can be seen from FIG. 3 and equations (11) - (14), each memristive bridge synapse circuit weights the output current, and all output circuits together flow through the load resistor rL. Therefore, the following conclusions can be drawn:
Figure BDA00026120647500000521
Figure BDA00026120647500000522
fig. 4 shows an architecture of the memristive neural network circuit according to an embodiment. A common architecture for biological neural networks is a repetitive connection of each neuron. In a manner similar to biological neural networks, by applying a memristive neural network circuit, an architecture of the memristive neural network circuit may be implemented. The output of each neuron is connected to another memristive bridge neuron circuit.
Simulation experiments of the examples:
1. electrical characteristic comparison of pulse-based memristive bridge circuit and pulse-based memristive bridge circuit
The pulse-based membra bridge circuit of fig. 1 uses fluidic capacitive membra to analyze the circuit characteristics. In particular, it is assumed that the input current constituting the memristor in the incremental capacitive memantine is the same as the input current in the incremental capacitive memantine, and that the current is a pulse signal with amplitude a and frequency f. The memristor in the positive increment capacitive memristor is as follows:
rP[q(t)]＝K1+K2q(t) (17)
the memristor in the negative increment capacitive memristor is as follows:
rN[q(t)]＝K1-K2q(t) (18)
at the position ofGet K in the experiment12000 and K2＝5·107. By selecting appropriate voltage source and resistance (r)s1000 Ω), the fundamental frequency f of the input current is set05Hz and amplitude a 10 μ a. When v is 0 and p is 0, incremental capacitive memreactance becomes a special case, i.e. incremental memristor. Thus, the output voltage of the pulse-based memristive bridge and the output voltage of the pulse-based memristive bridge are shown in fig. 5 and 6, respectively. The pulse-based memristive bridge circuit realizes linear weighting of input signals, and the pulse-based memristive bridge circuit realizes nonlinear weighting operation of the input signals, and is more suitable for describing neural synapse weighting. Output current of memristive bridge synapse circuit is equal to
Figure BDA0002612064750000062
The shape of the output current is the same as the shape of the output voltage of the corresponding pulse-based memristive bridge circuit.
2. Modeling LTP and LTD
In neuroscience, t.v.p.bliss and T.
Figure BDA0002612064750000061
Long-Term Potentiation (LTP) of synaptic transmission was found in the dentate gyrus region of rabbits. LTP describes a persistent enhancement of synaptic weights. The reverse process of LTP, LTD (Long-Term suppression), is a continuous weakening of synaptic weights. Just as modification of synaptic weights is thought of as a process of learning and memory, LTP and LTD are widely thought of as two major cellular mechanisms with respect to learning and memory. The electrical characteristics of the pulse-based memristive bridge circuit may be used to describe the LTP and LTD, as shown in fig. 7 and 8. By applying a positive pulse, the output voltage of the memristive bridge circuit gradually increases, and the LTP phenomenon occurs. In contrast, when a negative pulse is applied, the output voltage of the memristive bridge circuit gradually decreases, and the LTD phenomenon occurs. When the duty cycle of the input pulse is equal to 50%, the output voltage returns almost to its initial value after one period, as shown in fig. 7. When the duty cycle of the input voltage pulse is equal to 70%, the output voltage increases after one period, as shown in fig. 8.

Claims (5)

1. The fractional order memristor bridge circuit for the neural synapse weighting is characterized by comprising two incremental capacitive memristors, two integrated operational amplifiers, two first resistors and two second resistors; wherein the increments of the two incremental capacitive memreactors are opposite;
one ends of the two first resistors are grounded, the other ends of the two first resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, one ends of the two second resistors are connected with the pulse input end in parallel, the other ends of the two second resistors are connected with the positive input ends of the two integrated operational amplifiers respectively, the negative electrodes of the two incremental capacitive memory-sharing resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, and the positive electrodes of the two incremental capacitive memory-sharing resistors are connected with the positive input ends of the two integrated operational amplifiers respectively.
2. The fractional order memristive bridge synapse circuit is characterized by comprising a subtracter circuit, a first inverse proportion device circuit and the fractional order memristive bridge circuit as claimed in claim 1, wherein two output ends of the fractional order memristive bridge circuit are respectively connected with two input ends of the subtracter circuit, and the output end of the subtracter circuit is connected with the input end of the inverse proportion device circuit.
3. The fractional order memristive bridge synapse circuit of claim 2, wherein the subtractor circuit comprises a third integrated operational amplifier, two third resistors, and two fourth resistors, wherein two output terminals of the fractional order memristive bridge circuit are respectively connected to one end of the two third resistors, the other ends of the two third resistors are respectively connected to positive and negative input terminals of the third integrated operational amplifier, one ends of the two fourth resistors are respectively connected to positive and negative input terminals of the third integrated operational amplifier, one end of one of the fourth resistors is connected to ground, and the other end of the other fourth resistor is connected to an output terminal of the third integrated operational amplifier.
4. The fractional order memristive bridge synapse circuit of claim 2, wherein the first inverse proportional circuit comprises a fourth integrated operational amplifier, a fifth resistance, a sixth resistance, and a seventh resistance, wherein the seventh resistance is a load resistance of the first inverse proportional circuit; one end of the fifth resistor is connected with the output end of the subtractor circuit, the other end of the fifth resistor is simultaneously connected with one end of the seventh resistor and the negative input end of the fourth integrated operational amplifier, one end of the sixth resistor is grounded, the other end of the sixth resistor is connected with the positive input end of the fourth integrated operational amplifier, and the output end of the fourth integrated operational amplifier is connected with the other end of the seventh resistor.
5. A fractional order memristive bridge neuron circuit, comprising a bias pulse terminal, a second inverse-proportioner circuit, and a plurality of fractional order memristive bridge synapse circuits of claim 4; the structure of the second inverse proportion device circuit is the same as that of the first inverse proportion device circuit in the fractional order memristive bridge synaptic circuit, the second inverse proportion device circuit and the first inverse proportion device circuits in all the fractional order memristive bridge synaptic circuits share the load resistor, the output end of the second inverse proportion device circuit is simultaneously connected with the output ends of all the fractional order memristive bridge synaptic circuits, and the input end of the second inverse proportion device circuit is connected with the bias pulse end.
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