CN111898748B - Fractional-order memristive bridge circuit, and its synaptic circuit and neuron circuit - Google Patents

Abstract

The invention relates to the field of memristors, and discloses a fractional-order memristor bridge circuit, and a synapse circuit and a neuron circuit which are formed by the fractional-order memristor bridge circuit, so that more accurate neurosynaptic weighting is realized. The voltage-controlled power supply comprises two v-order incremental capacitive memory reactors, two integrated operational amplifiers, two first resistors and two second resistors; wherein the increments of the two incremental capacitive memantines are opposite; one ends of the two first resistors are grounded, the other ends of the two first resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, one ends of the two second resistors are connected with the pulse input end in parallel, the other ends of the two second resistors are connected with the positive input ends of the two integrated operational amplifiers respectively, the negative electrodes of the two capacitive memory resistors are connected with the negative input ends of the two integrated operational amplifiers respectively, and the positive electrodes of the two capacitive memory resistors are connected with the positive input ends of the two integrated operational amplifiers respectively. The invention is applicable to neural synapse weighting.

Description

Fractional-order memristive bridge circuit, and its synaptic circuit and neuron circuit

technical field

The invention relates to the field of memristive, in particular to a fractional-order memristive bridge circuit, and a synaptic circuit and a neuron circuit composed of the same.

Background technique

In 1971, Professor Cai Shaotang of the University of California, Berkeley, proposed memristor to characterize the relationship between electric charge and magnetic flux. In addition to the three basic circuit elements of resistance, capacitance and inductance, memristor is a novel nonlinear circuit element with memory and synapse-like properties. Today, fractional calculus has become an important and novel branch of mathematical analysis. Due to its long-term memory, nonlocality, and weak singularity, fractional calculus has developed into a novel and useful tool in many scientific fields, such as diffusion processes, viscoelasticity theory, fractal dynamics, fractional-order control , image processing, fractional resistance, fractional order memristive and neural networks. The fundamental feature of fractional calculus is that it extends the concepts of integer-order differences and Riemann sums. The characteristics of fractional calculus are very different from those of classical integer calculus. For example, the fractional derivative of the Heaviside function is non-zero except based on the Caputo definition, while its integer-order derivative must be zero. According to Chua's axiom element system, considering constitutive relation, logical consistency, axiomatic integrity and formal symmetry, fractional-order memristive should exist. There are two types of fractional memristors: capacitive fractional memristors and inductive fractional memristors, which correspond to capacitive and inductive fractional impedances, respectively. The electrical properties of capacitive fractional memristors are intermediate between those of capacitors and memristors. In a similar manner, the electrical properties of inductive fractional-order memristors are intermediate between those of inductance and memristor.

和

其中c和l分别表示电容和电感，s是拉普拉斯变量，H(s)＝L{h[q(t)]}是构成分忆抗中的忆阻的传输函数(忆阻两端的电压-电流关系是v_in(t)＝r[q(t)]i_in(t)＝h[q(t)]*i_in(t)，r[q(t)]是忆阻值)，v＝η+p是运算阶数(v≥0：若v是正整数，则_η＝v-1和_p＝1；除此之外，

和0≤p<1)。蒲亦非等人提出了分忆抗的指纹特征并用硬件实现了第一个分忆抗。此外，分忆抗也可以分为正增量分忆抗和负增长量分忆抗。这样一来，忆阻的概念从最初经典的整数阶忆阻推广到分数阶忆阻。The terms "fractional memristor" and "fractional memristive value" in this patent are the abbreviations for "fractional memristor" and "fractional memristor", respectively. Pu Yifei et al. deduced the arbitrary-order instigation point impedance functions of capacitive and inductive discrete reactances, namely,

and

where c and l represent capacitance and inductance, respectively, s is the Laplace variable, and H(s)=L{h[q(t)]} is the transfer function that constitutes the memristive in the memristor (the The voltage-current relationship is v _in (t)=r[q(t)]i _in (t)=h[q(t)]*i _in (t), r[q(t)] is the memristor value) , v=η+p is the operation order (v≥0: if v is a positive integer, then _η =v-1 and _p =1; in addition,

and 0≤p<1). Pu Yifei et al. proposed the fingerprint feature of the memory resistance and realized the first memory resistance with hardware. In addition, the fractional resistance can also be divided into positive incremental fractional fractional resistance and negatively increased fractional fractional fractional fractional fraction. In this way, the concept of memristor is extended from the original classical integer-order memristor to fractional-order memristor.

The synaptic weight refers to the strength of the connection between two neurons. Depending on recent neuron activity, synaptic weights change, a process called synaptic plasticity. Synaptic plasticity is the adaptation of neurons in the brain during learning. Research in the field of synaptic weighting has had only limited success due to the lack of suitable devices to achieve synapses. Kim et al. proposed a memristive bridge circuit consisting of four identical memristors to achieve zero, negative, and positive synaptic weights. Adhikari et al. proposed an analog hardware architecture and a corresponding learning scheme of a multi-layer neural network based on memristive bridge synapses. Sah et al. proposed a simple and compact memristive bridge-based circuit to achieve signed synaptic weighting in neuronal cells. Li et al. proposed a memory-capacitance bridge circuit including four identical memory-capacitors. Wang et al. proposed a spintronic memristive bridge synaptic circuit. However, in the essence of mathematics, these memristive bridge synaptic circuits are all based on integer order memristors to achieve synaptic weighting. The integer-order memristive bridge circuit realizes the linear weighting of the input pulse signal, which is not suitable for describing the weighting of neural synapses.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a fractional-order memristive bridge circuit, and the synaptic circuit and neuron circuit formed by the same, so as to realize more accurate synaptic weighting.

For achieving the above object, the technical scheme adopted in the present invention is:

In one aspect, the present invention provides a fractional-order memristive bridge circuit for neural synapse weighting, comprising two v-order incremental capacitive fractional memristors, two integrated operational amplifiers, two first resistors, and two A second resistor; among them, v is a positive real number, and the increments of the two v-order incremental capacitive remnants are opposite;

One ends of the two first resistors are grounded, the other ends of the two first resistors are respectively connected to the negative input ends of the two integrated operational amplifiers, one end of the two second resistors is connected in parallel with the pulse input end, and the other ends of the two second resistors are connected to the pulse input end in parallel. One end is respectively connected to the positive input terminals of the two integrated operational amplifiers, the negative poles of the two incremental capacitive shunts are respectively connected to the negative input terminals of the two integrated operational amplifiers, and the positive poles of the two incremental capacitive shunts are respectively Connect the positive inputs of the two integrated op amps.

In another aspect, the present invention provides a fractional-order memristive bridge synapse circuit, including a subtractor circuit, a first inverse scaler circuit, and the above-mentioned fractional-order memristive bridge circuit. The fractional-order memristive bridge circuit has two outputs. The terminals are respectively connected to the two input terminals of the subtractor circuit, and the output terminal of the subtractor circuit is connected to the input terminal of the inverse scaler circuit.

Specifically, the subtractor circuit includes a third integrated operational amplifier, two third resistors and two fourth resistors, two output ends of the fractional-order memristor bridge circuit are respectively connected to one end of the two third resistors, and the two third resistors The other end of the resistor is connected to the positive and negative input terminals of the third integrated operational amplifier, respectively, and one end of the two fourth resistors is connected to the positive and negative input terminals of the third integrated operational amplifier, respectively. The other end of one fourth resistor is grounded, and the other The other end of the fourth resistor is connected to the output end of the third integrated operational amplifier.

Specifically, the first inverse scaler circuit includes a fourth integrated operational amplifier, a fifth resistor, a sixth resistor and a seventh resistor, wherein the seventh resistor is a load resistance of the first inverse scaler circuit; one end of the fifth resistor Connect the output end of the subtractor circuit, the other end of the fifth resistor is connected to one end of the seventh resistor and the negative input end of the fourth integrated operational amplifier, one end of the sixth resistor is grounded, and the other end of the sixth resistor is connected to the fourth integrated operation The positive input end of the amplifier and the output end of the fourth integrated operational amplifier are connected to the other end of the seventh resistor.

In another aspect, the present invention also provides a fractional-order memristive bridge neuron circuit, including a bias pulse terminal, a second inverse scaler circuit, and the above-mentioned fractional-order memristive bridge synapse circuit; the second inverse scaler circuit The structure of the scaler circuit is the same as that of the first inverse scaler circuit in the fractional-order memristive bridge synapse circuit, and the second inverse scaler circuit is the same as the first inverse scaler in all fractional-order memristive bridge synapse circuits. The output terminal of the second inverse scaler circuit is connected to the output terminals of all fractional-order memristive bridge synapse circuits at the same time, and the input terminal of the second inverse scaler circuit is connected to the bias pulse terminal.

The beneficial effects of the present invention are: the existing memristive bridge synaptic circuits are all based on integer-order memristors to achieve neural synapse weighting, because the concept of memristive has been extended from the classical integer-order memristive to fractional-order memristive , therefore, the present invention proposes a fractional-order memristive bridge circuit, and a synaptic circuit and neuron circuit composed of the same. The pulse-based memristive bridge circuit realizes linear weighting of the input signal, while the pulse-based fraction The synaptic weight of the memristive bridge circuit is a nonlinear function with long-term memory, which realizes the nonlinear weighting of the input signal, and is more suitable for describing the synaptic weighting. It can be seen that the final neural synapse weighting circuit based on fractional order memristor of the present invention can describe the cellular mechanism of learning and memory more effectively, and is superior to the traditional neural synapse weighting circuit based on integer order memristor.

Description of drawings

Figure 1 is a circuit diagram of a pulse-based split-memristor bridge;

Figure 2 is a circuit diagram of a split-membrane bridge synapse;

Figure 3 is the circuit diagram of the anti-bridge neuron;

Fig. 4 is the architecture diagram of the memory anti-neural network circuit;

Figure 5 is a graph of the output voltage of a pulse-based shunt bridge;

Figure 6 is a graph of the output voltage of a pulse-based memristive bridge;

FIG. 7 is a graph of the output voltage of a pulse-based shunt bridge circuit, wherein the duty cycle of the input pulse is equal to 50%;

FIG. 8 is a graph of the output voltage of a pulse-based shunt bridge circuit where the duty cycle of the input pulse is equal to 70%. .

Detailed ways

和

)、两个集成运算放大器

和

两个阻值为r_s的第一电阻、两个阻值为r_p的第二电阻。

是负增量分忆抗，而

是正增量分忆抗。两个第一电阻的一端均接地，两个第一电阻的另一端分别连接两个集成运算放大器的负输入端，两个第二电阻的一端并联在脉冲输入端，两个第二电阻的另一端分别连接两个集成运算放大器的正输入端，两个容性分忆抗的负极分别连接两个集成运算放大器的负输入端，两个容性分忆抗的正极分别连接两个集成运算放大器的正输入端。两个集成运算放大器

和

分别构建两个相同的电压-电流转换器，根据基尔霍夫电流定律(KCL)和基尔霍夫电压定律(KVL)，获得以下关系：In order to realize neural synapse weighting through fractional-order memristive, the embodiment first discloses a pulse-based fractional memristive (ie fractional-order memristive) bridge circuit, as shown in FIG. 1 , including two v(v is a positive real number) order capacitive positive and negative incremental fractional reactance (

and

), two integrated operational amplifiers

and

Two first resistors with a resistance value of _rs and two second resistors with a resistance value of _rp .

is the negative incremental fractional resistance, and

is the positive incremental fractional memristance. One ends of the two first resistors are grounded, the other ends of the two first resistors are respectively connected to the negative input ends of the two integrated operational amplifiers, one end of the two second resistors is connected in parallel with the pulse input end, and the other ends of the two second resistors are connected to the pulse input end in parallel. One end is respectively connected to the positive input terminals of the two integrated operational amplifiers, the negative terminals of the two capacitive shunts are respectively connected to the negative input terminals of the two integrated operational amplifiers, and the positive terminals of the two capacitive shunts are respectively connected to the two integrated operational amplifiers of the positive input. Two integrated operational amplifiers

and

Constructing two identical voltage-current converters separately, according to Kirchhoff's current law (KCL) and Kirchhoff's voltage law (KVL), the following relationship is obtained:

是正脉冲或负脉冲信号。无论

的极性是正的或负的，

的分忆抗值的变化趋势与

相反。v₀是

和

两端的初始电压降。基于脉冲的分忆抗桥电路的输出电压

等于B点和A点之间的电压差，因此，从公式(1)-(6)，

可表示为：where the input voltage

is a positive or negative pulse signal. regardless

The polarity is positive or negative,

The change trend of the fractional resistance value of

on the contrary. v ₀ is

and

The initial voltage drop across. Output Voltage of Pulse-Based Memristor Bridge Circuit

is equal to the voltage difference between points B and A, therefore, from equations (1)-(6),

can be expressed as:

可以将基于脉冲的分忆抗桥电路的输出电压

设置为所需的值：Since H(s)=L{h[q(t)]} is the reactance that constitutes the memristive in the incremental capacitive shunt, therefore, the synaptic weight of the pulse-based shunt bridge circuit is a long-term The nonlinear function of memory enables non-volatile storage of weights and nonlinear weighting in artificial neural networks. The shunt bridge circuit includes two positive and negative incremental capacitive shunts. By inputting the programmed pulse

The output voltage of a pulse-based shunt bridge circuit can be

Set to the desired value:

为：The pulse-based shunt-memristor bridge circuit shown in Figure 1 is realized by two v-order positive and negative incremental capacitive shunts. In practical applications, the first resistor r _p and the second resistor _rs can choose different parameter, then the output voltage of the pulse-based thoracic bridge circuit

for:

和

两个阻值为r_t的第三电阻、两个阻值为r_f的第四电阻、一个阻值为

的第五电阻、一个阻值为

的第六电阻、一个阻值为r_L的第七电阻。第三电阻、第四电阻及集成运算放大器

构成减法器，第五电阻、第六电阻第七电阻及集成运算放大器

构成反向比例器，运算放大器

在反相输入端实现电压-电流转换。r_L是负载电阻，

是流过r_L的负载电流。因此，在

和

的单独作用下，获得：As shown in FIG. 2 is the shunt bridge synapse circuit given in the embodiment, including the above pulse-based shunt bridge circuit, two integrated operational amplifiers

and

Two third resistors with resistance value _rt , two fourth resistors with resistance value r _f , and one resistance value

The fifth resistance of , a resistance value of

The sixth resistor, a seventh resistor with a resistance value of r _L. Third Resistor, Fourth Resistor and Integrated Operational Amplifier

Form a subtractor, the fifth resistor, the sixth resistor, the seventh resistor and the integrated operational amplifier

Constitute an inverse scaler, an operational amplifier

Voltage-to-current conversion is achieved at the inverting input. r _L is the load resistance,

is the load current flowing through r _L. Thus, in

and

Under the single action of , obtain:

从公式(7)和(10)，获得：Furthermore, for

From equations (7) and (10), we obtain:

仅取决于

与负载电阻r_L无关。因此，分忆抗桥突触电路实际实现了差分电流源。load current

depends only on

Independent of load resistance r _L. Therefore, the shunt bridge synapse circuit actually realizes a differential current source.

和

)和四个集成运算放大器(

和

)构造第一个分忆抗突触电路。

和

构造第n个分忆抗突触电路，集成运算放大器Aⁿ⁺¹实现单元偏置电路。v_b(t)是单元偏置电压(电压源偏置脉冲)。i_L(t)是流过r_L的负载电流。因此，根据KCL，获得：As shown in FIG. 3, the embodiment provides a fractional memristive bridge neuron circuit, which includes a second inverse scaler circuit and n (n>1) above-mentioned fractional-order memristive bridge synaptic circuits. The structure of the inverse scaler circuit is the same as that of the first inverse scaler circuit in the fractional-order memristive bridge synapse circuit, and the second inverse scaler circuit is the same as the first inverse scaler circuit in all fractional-order memristive bridge synapse circuits. The load resistance r _L is shared with the scaler circuit, the output terminal of the second inverse scaler circuit is connected to the output terminals of all fractional-order memristive bridge synapse circuits at the same time, and the input terminal of the second inverse scaler circuit is connected to the bias pulse terminal . In Figure 3, the two split-resistance (

and

) and four integrated operational amplifiers (

and

) to construct the first discrete anti-synaptic circuit.

and

Construct the n th memristive synapse circuit, and integrate the operational amplifier A ⁿ⁺¹ to realize the unit bias circuit. v _b (t) is the cell bias voltage (voltage source bias pulse). i _L (t) is the load current flowing through r _L. Therefore, according to the KCL, one obtains:

where i∈[1,n] is a positive integer. It can be seen from Fig. 3 and formulas (11)-(14) that each shunt bridge synapse circuit weights the output current respectively, and all the output circuits flow through the load resistance r _L together. Therefore, the following conclusions can be drawn:

As shown in FIG. 4 , the architecture of the memory resistive neural network circuit given in the embodiment is shown. The general architecture of biological neural networks is the repeated connection of each neuron. In a manner similar to biological neural networks, the architecture of a memory-resistant neural network circuit can be realized by applying a memory-resistant bridge neuron circuit. The output of each neuron is connected to another circuit of the transmembrane bridge neuron.

The simulation experiment of the embodiment:

1. Comparison of electrical characteristics between pulse-based split memristive bridge circuit and pulse-based memristive bridge circuit

The pulse-based shunt bridge circuit in Figure 1 uses a flow-controlled capacitive shunt to analyze the circuit characteristics. In particular, it is assumed that the input current constituting the memristor in the incremental capacitive memristor is the same as the input current in the incremental capacitive memristive, and that the current is a pulse signal of amplitude A and frequency f. The memristive value of the memristive in the positive incremental capacitive fractional memristive is:

r _P [q(t)]=K ₁ +K ₂ q(t) (17)

The memristive value of the memristive in the negative incremental capacitive fractional memristive is:

r _N [q(t)]=K ₁ −K ₂ q(t) (18)

输出电流的形状与相应的基于脉冲的分忆抗桥电路的输出电压的形状相同。K ₁ =2000 and K ₂ =5·10 ⁷ were taken in this experiment. By choosing an appropriate voltage source and resistance ( _rs = 1000Ω), the fundamental frequency of the input current f ₀ =5 Hz and the amplitude A = 10 μA. When v=0 and p=0, the incremental capacitive memristive becomes a special case, namely the incremental memristive. Therefore, the output voltages of the pulse-based memristive bridge and the pulse-based memristive bridge are shown in Fig. 5 and Fig. 6, respectively. The pulse-based memristive bridge circuit realizes the linear weighting of the input signal, while the pulse-based memristive bridge circuit realizes the nonlinear weighting operation of the input signal, which is more suitable for describing the weighting of neural synapses. The output current of the mnemonic bridge synaptic circuit is equal to

The shape of the output current is the same as the shape of the output voltage of the corresponding pulse-based DRAM bridge circuit.

2. Simulate LTP and LTD

在兔子的齿状回区域发现了突触传递的长期增强(Long-Term Potentiation，LTP)性质。LTP描述了突触权重的持续增强。LTP的相反过程，即LTD(Long-Term Depression)，是突触权值的持续减弱。正如突触权重的修改被认为是学习和记忆的过程，LTP和LTD被广泛认为是关于学习和记忆的两种主要的细胞机制。基于脉冲的分忆抗桥电路的电气特性可用于描述学LTP和LTD，如图7和图8所示。通过施加正脉冲，分忆抗桥电路的输出电压逐渐增强，出现LTP现象。相反，当施加负脉冲时，分忆抗桥电路的输出电压逐渐减弱，出现LTD现象。当输入脉冲的占空比等于50％时，在一个周期后，输出电压几乎返回到其初始值，如图7所示。当输入电压脉冲的占空比等于70％时，在一个周期后，输出电压会增加，如图8所示。In neuroscience, TVPBliss and T.

Long-Term Potentiation (LTP) properties of synaptic transmission were found in the dentate gyrus region of rabbits. LTP describes a sustained enhancement of synaptic weights. The opposite process of LTP, LTD (Long-Term Depression), is a continuous weakening of synaptic weights. Just as the modification of synaptic weights is thought to be a process of learning and memory, LTP and LTD are widely considered to be the two main cellular mechanisms involved in learning and memory. The electrical characteristics of the pulse-based shunt bridge circuit can be used to describe the LTP and LTD, as shown in Figure 7 and Figure 8. By applying a positive pulse, the output voltage of the memristor bridge circuit gradually increases, and the LTP phenomenon occurs. On the contrary, when a negative pulse is applied, the output voltage of the memristor bridge circuit gradually weakens, and the LTD phenomenon appears. When the duty cycle of the input pulse is equal to 50%, after one cycle, the output voltage almost returns to its initial value, as shown in Figure 7. When the duty cycle of the input voltage pulse is equal to 70%, after one cycle, the output voltage increases, as shown in Figure 8.

Claims (5)

1. A fractional-order memristive bridge circuit for neural synapse weighting, characterized in that it comprises two incremental capacitive fractional memristors, two integrated operational amplifiers, two first resistors and two second resistors; Among them, the increments of the two incremental capacitive fractional reactances are opposite; One ends of the two first resistors are grounded, the other ends of the two first resistors are respectively connected to the negative input ends of the two integrated operational amplifiers, one end of the two second resistors is connected in parallel with the pulse input end, and the other ends of the two second resistors are connected to the pulse input end in parallel. One end is respectively connected to the positive input terminals of the two integrated operational amplifiers, the negative poles of the two incremental capacitive shunts are respectively connected to the negative input terminals of the two integrated operational amplifiers, and the positive poles of the two incremental capacitive shunts are respectively Connect the positive inputs of the two integrated op amps. 2. A fractional-order memristive bridge synapse circuit, characterized in that it comprises a subtractor circuit, a first inverse scaler circuit and the fractional-order memristive bridge circuit of claim 1, and the fractional-order memristive bridge circuit has two outputs. The terminals are respectively connected to the two input terminals of the subtractor circuit, and the output terminal of the subtractor circuit is connected to the input terminal of the inverse scaler circuit. 3. The fractional-order memristive bridge synapse circuit of claim 2, wherein the subtractor circuit comprises a third integrated operational amplifier, two third resistors and two fourth resistors, and the fractional-order memristive bridge circuit The two output terminals are respectively connected to one end of the two third resistors, the other ends of the two third resistors are respectively connected to the positive and negative input terminals of the third integrated operational amplifier, and one end of the two fourth resistors are respectively connected to the third integrated operational amplifier The positive and negative input ends of the , wherein the other end of one of the fourth resistors is grounded, and the other end of the other fourth resistor is connected to the output end of the third integrated operational amplifier. 4. The fractional-order memristive bridge synapse circuit of claim 2, wherein the first inverse scaler circuit comprises a fourth integrated operational amplifier, a fifth resistor, a sixth resistor and a seventh resistor, wherein the first The seventh resistor is the load resistor of the first inverse scaler circuit; one end of the fifth resistor is connected to the output end of the subtractor circuit, and the other end of the fifth resistor is simultaneously connected to one end of the seventh resistor and the negative input end of the fourth integrated operational amplifier , one end of the sixth resistor is grounded, the other end of the sixth resistor is connected to the positive input end of the fourth integrated operational amplifier, and the output end of the fourth integrated operational amplifier is connected to the other end of the seventh resistor. 5. A fractional-order memristive bridge neuron circuit, characterized in that it comprises a bias pulse terminal, a second inverse scaler circuit, and a plurality of fractional-order memristive bridge synaptic circuits according to claim 4; the second inverse The structure of the scaler circuit is the same as that of the first inverse scaler circuit in the fractional-order memristive bridge synapse circuit, and the second inverse scaler circuit is the same as the first inverse scaler circuit in all fractional-order memristive bridge synapse circuits. The scaler circuit shares the load resistance, the output terminal of the second inverse scaler circuit is simultaneously connected to the output terminals of all fractional-order memristive bridge synapse circuits, and the input terminal of the second inverse scaler circuit is connected to the bias pulse terminal.

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