CN111884964A - Frequency synchronization system adapting to VDE multi-modulation system - Google Patents

Frequency synchronization system adapting to VDE multi-modulation system Download PDF

Info

Publication number
CN111884964A
CN111884964A CN202010608584.6A CN202010608584A CN111884964A CN 111884964 A CN111884964 A CN 111884964A CN 202010608584 A CN202010608584 A CN 202010608584A CN 111884964 A CN111884964 A CN 111884964A
Authority
CN
China
Prior art keywords
frequency
signal
synchronization
loop
afc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010608584.6A
Other languages
Chinese (zh)
Other versions
CN111884964B (en
Inventor
荣师洁
李惠媛
向前
张喆
吴红军
叶曦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Aerospace Electronic Communication Equipment Research Institute
Original Assignee
Shanghai Aerospace Electronic Communication Equipment Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Aerospace Electronic Communication Equipment Research Institute filed Critical Shanghai Aerospace Electronic Communication Equipment Research Institute
Priority to CN202010608584.6A priority Critical patent/CN111884964B/en
Publication of CN111884964A publication Critical patent/CN111884964A/en
Application granted granted Critical
Publication of CN111884964B publication Critical patent/CN111884964B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0024—Carrier regulation at the receiver end
    • H04L2027/0026—Correction of carrier offset

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

The invention provides a frequency synchronization system adapting to a VDE multi-modulation system, which comprises a frequency correlation synchronization module and an AFC module, wherein the frequency correlation synchronization module is used for performing coarse synchronization, fine synchronization and fine synchronization on the frequency of a received signal, the AFC module comprises two stages of AFC rings which are connected in series, the first stage of AFC ring is used for performing rapid synchronization processing on an output signal of the frequency correlation module, and the second stage of AFC ring is used for performing accurate tracking compensation on the frequency offset of the output signal of the frequency correlation module. The invention can utilize the frequency correlation synchronization module to carry out three-step estimation of frequency deviation under the scene of unknown modulation system, and utilizes the two-stage AFC loop to accurately estimate the residual frequency deviation of the received signal and carry out tracking compensation, thereby providing accurate frequency synchronization for the signal demodulation of the rear end and having important significance for receiving VDE shore-based and space-based target signals.

Description

Frequency synchronization system adapting to VDE multi-modulation system
Technical Field
The invention relates to the technical field of maritime communication, in particular to a frequency synchronization system suitable for a VDE multi-modulation system.
Background
Reliable maritime communication is an important means for meeting the requirements of normal navigation and operation of ships and guaranteeing the safety of marine navigation. In the development of maritime communications, automatic control systems (AIS) have played a very important role. With the increasing number of AIS users, the AIS system may cause serious problems of information blocking, information loss and the like in a high link load of a VHF frequency band, and a vde (VHF Data exchange) concept is proposed for the international navigation mark organization (IALA), and the concept comprises a shore-based system and a space-based system (satellite), so as to meet different requirements of offshore and offshore vessels, provide high-speed, reliable and globally-covered Data transmission, and comprehensively improve the offshore communication and information service capabilities.
In VDE communication, factors such as Doppler shift caused by relative high-speed motion between a shore base and a ship and between a satellite and the ship cause frequency shift of a received signal relative to a transmitted signal, so that the signal cannot be correctly judged. The carrier frequency synchronization restores the received signal to the waveform state closest to the transmitted signal to improve the demodulation accuracy. Meanwhile, propagation loss of the VDE offshore link, including free space propagation loss, sea surface air absorption loss, sea surface reflection loss, and far communication distance and large loss faced by the VDE satellite link, may result in a low signal-to-noise ratio of the received signal. Further, the VDE received signal is a burst signal, the transmitting end selects different modulation schemes according to the current channel quality to achieve higher transmission efficiency, the modulation system of the burst data frame is unknown to the receiving end, and the frequency synchronization method must have universality. The modulation modes of the VDE system comprise pi/4QPSK, 8PSK and 16QAM, wherein the 16QAM is most sensitive to frequency offset. Therefore, it is important to design a frequency synchronization method suitable for the characteristics of the VDE system.
VDE employs special synchronization codes inserted in the transmitted signal for receiver synchronization. The correlation detection is a way of realizing signal synchronization by comparing the correlation between the received signal and the local synchronization code, and has the characteristics of simplicity, high efficiency and the like. An automatic frequency tracking loop (AFC) is widely used for carrier frequency tracking because of its low complexity and the ability to realize real-time frequency estimation, wherein the best AFC loop implementation under low signal-to-noise ratio is Costas loop and square loop, and these two loops have the same efficiency, but Costas loop uses multiplier and filter to replace squarer of square loop, and the circuit making and debugging of loop are simpler, so Costas loop is more widely used.
Since the VDE belongs to a burst system, the modulation scheme of the received signal is unknown to the receiving end. The device selects high-order modulation transmission data as much as possible according to the channel quality by adopting an adaptive modulation system, and the high-order modulation is more sensitive to frequency deviation; and large frequency deviation is introduced by relative movement between the ship and the shore base and between the ship and the satellite, and the link loss is large.
Disclosure of Invention
The invention aims to provide a frequency synchronization system adaptive to a VDE multi-modulation system, which aims to solve the problem of frequency synchronization of the conventional VDE receiving system when the modulation mode of a burst signal is unknown.
In order to achieve the above object, the present invention provides a frequency synchronization system adapted to a VDE multi-modulation system, including a frequency-dependent synchronization module and an AFC module, where the frequency-dependent synchronization module is configured to perform coarse synchronization, fine synchronization, and fine synchronization on a received signal, and the AFC module includes two stages of AFC loops connected in series, where the first stage AFC loop is configured to perform fast synchronization processing on an output signal of the frequency-dependent synchronization module, and the second stage AFC loop is configured to perform accurate tracking compensation on a frequency offset of the output signal of the frequency-dependent synchronization module.
Preferably, the frequency-dependent synchronization module includes a coarse synchronization module, a fine synchronization module and a fine synchronization module, which are connected in series in sequence, and are respectively configured to perform coarse synchronization, fine synchronization and fine synchronization processing of signal frequency offset on the received signal.
Preferably, the AFC loop includes a mixer, a low-pass filter, a decision device, a phase discriminator, a loop filter, a phase controller, and a voltage-controlled oscillator, which are sequentially connected in a unidirectional annular manner, where the mixer multiplies an input signal by an output signal of the voltage-controlled oscillator to obtain a mixed signal, the mixed signal is low-pass filtered by the low-pass filter and then input to the decision device for performing a decision process, the phase discriminator performs a phase error direction estimation, and the loop filter and the phase controller obtain an updated frequency control word to adjust an output frequency of the voltage-controlled oscillator, so as to implement a frequency compensation on the input signal;
the output signal of the frequency-dependent synchronization module is input to the mixer of the first-stage AFC loop to be multiplied by the output of the voltage-controlled oscillator of the first-stage AFC loop, the output end of the loop filter of the first-stage AFC loop is connected with the input end of the loop filter of the second-stage AFC loop, and the output of the low-pass filter of the second-stage AFC loop is used for obtaining a signal with accurate tracking compensation.
Preferably, the input signal of the primary AFC loop is processed by the data delay module and then input to the mixer of the secondary AFC loop.
Preferably, the decision device is provided with a priori condition: the output signal of the decision device needs to satisfy the signal sampling point before entering the phase discriminator:
Figure BDA0002559814880000031
wherein α is 0.618, QKFor the signal, I, of the mixer input signal multiplied by an in-phase carrier signal generated by the NCO and passed through a low-pass filterKThe input signal to the mixer is the signal multiplied by the quadrature carrier signal generated by the NCO and passed through a low pass filter.
Preferably, the phase detector uses a common Costas loop to perform multiplication phase detection, obtains a direction signal (+1, -1) of a phase error in a manner of sign phase detection, and outputs the direction signal to the loop filter.
Preferably, the loop filter establishes a feedback loop for the Costas loop, and when the result of the phase detector is positive, the loop filter inputs + 1; when the phase detector result is negative, the loop filter inputs-1.
Preferably, the loop filter is a second-order loop filter, wherein the coefficient of the loop filter of the first-order AFC loop is greater than the coefficient of the loop filter of the second-order AFC loop.
Preferably, the phase controller sums the value of the phase error signal from the loop filter with the original accumulated value to generate the frequency control word.
Preferably, the voltage-controlled oscillator controls the frequency and phase of its output signal according to the frequency control word, so as to implement frequency compensation on the received signal.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
the invention provides a frequency synchronization system applicable to a VDE multi-modulation system, which firstly realizes coarse, fine and fine synchronization of frequency offset by adopting a quick and efficient frequency correlation synchronization method; and then, an improved two-stage Costas loop is adopted to respectively realize the rapid synchronization and the accurate tracking compensation of the residual frequency offset, the Costas loop adapts to all three modulation modes of the VDE, including pi/4QPSK, 8PSK and 16QAM, so that a receiver can realize accurate frequency synchronization under the condition of unknown modulation modes to correctly demodulate the original burst frame data.
Drawings
FIG. 1 is a schematic diagram of the system components of the preferred embodiment of the present invention;
FIG. 2 is a block diagram of a common Costas ring according to the present invention;
FIG. 3 is a constellation diagram for 16QAM modulation in VDE;
FIG. 4 is a block diagram of the loop filter of the Costas loop of the present invention;
FIG. 5A is a constellation diagram of a first-level AFC loop input signal frequency-synchronized simulation using 8PSK modulated signals;
FIG. 5B is a constellation diagram of a first-level AFC loop output signal frequency-synchronized simulated using 8PSK modulated signals;
FIG. 5C is a two-stage AFC loop output signal constellation diagram for frequency synchronization simulation of an application example 8PSK modulated signal;
fig. 6A is a constellation diagram of a first-stage AFC loop input signal frequency-synchronized simulated by applying example 16QAM modulated signal;
FIG. 6B is a constellation diagram of an output signal of a first-stage AFC loop simulated by frequency synchronization of a 16QAM modulated signal;
fig. 6C is a two-stage AFC loop output signal constellation diagram simulated using 16QAM modulated signal frequency synchronization.
Detailed Description
While the embodiments of the present invention will be described and illustrated in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed, but is intended to cover various modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
For the convenience of understanding the embodiments of the present invention, the following description will be further explained by taking specific embodiments as examples with reference to the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.
As shown in fig. 1, the present embodiment provides a frequency synchronization system adapted to a VDE multi-modulation system, which includes a receiving end preprocessing module, a frequency correlation synchronization module, and an AFC module. The receiving end preprocessing module is used for processing a received signal into a down-converted VDE zero intermediate frequency signal; the frequency correlation synchronization module is used for carrying out signal frequency offset synchronization processing on the VDE zero intermediate frequency signal, and specifically carrying out frequency coarse synchronization, fine synchronization and fine synchronization on a received signal; the AFC module comprises two stages of AFC loops connected in series, wherein the first stage of AFC loop is used for performing rapid synchronization processing on an output signal of the frequency correlation synchronization module, and the second stage of AFC loop is used for performing accurate tracking compensation on frequency deviation on the output signal of the frequency correlation synchronization module. The receiving end preprocessing module mainly comprises a down-conversion module and a decimation filtering module, and the received signals are processed into down-converted VDE zero intermediate frequency signals through the down-conversion module and the decimation filtering module.
In this embodiment, the frequency-dependent synchronization module includes a coarse synchronization module, a fine synchronization module, and a fine synchronization module, which are connected in series in sequence, and are respectively configured to perform coarse synchronization, fine synchronization, and fine synchronization processing of signal frequency offset on an input VDE zero intermediate frequency signal. Through the arrangement of three-level frequency correlation sub-modules, the two-dimensional search of time delay and reference frequency can be effectively utilized for synchronous estimation, and the time delay and frequency estimation values are extracted by identifying the maximum correlation peak value.
Specifically, since the VDE system employs a method of inserting a special synchronization sequence at a fixed position of a burst data frame for synchronization, a receiving end may perform synchronization by using a correlation detection method. And considering the frequency domain cyclic shift property of Discrete Fourier Transform (DFT), the phase shift of the time domain signal is reflected in the frequency domain as a cyclic shift of the frequency domain signal. Therefore, the following scheme is adopted in the embodiment: and performing discrete Fourier transform on the local synchronous sequence to obtain a local frequency domain synchronous sequence, and storing the local frequency domain synchronous sequence in a receiver. The received time domain signal is transformed to the frequency domain, a signal R (f) (f represents frequency) with the same length as the local frequency domain synchronous sequence is taken out at the possible receiving moment, the signal R (f) and the signal F perform correlation operation with the local frequency domain synchronous sequence and the cyclic shift sequence S (f), and the time delay and frequency offset estimation result is obtained by detecting the peak value of the correlation function. The time delay and frequency estimates can thus be obtained by:
Figure BDA0002559814880000051
according to the cyclic shift theorem of Discrete Fourier Transform (DFT), the change of the time domain phase is reflected in the frequency domain as a cyclic shift of the frequency domain sequence, that is, if:
X(k)＝DFT[x(n)]N0≤k≤N-1，
Y(k)＝X((k+l))NRN(k)，
wherein: x (n) is a time domain signal, n is an integer and is more than or equal to 0 and less than L, and L is the length of the time domain signal; n is the number of DFT points, and the frequency domain sequence X (k) is obtained by carrying out N-point DFT on x (N); y (k) is obtained by performing a cyclic shift of l points on X (k) and truncating, wherein double brackets indicate cyclic shift, and RN(k) K is more than or equal to 0 and less than or equal to N-1; then y (n) is obtained by performing IDFT transform on the frequency domain sequence y (k) and having:
Figure BDA0002559814880000061
in the formula, WN＝e-j2π/NThus, for the native synchronization sequence of the original time domain, S (f) can be transformed by its fourier transform0) (frequency offset f)00) to obtain all other frequency domain synchronization reference sequences, so that the receiver locally only needs to store one synchronization sequence, and other sequences can be obtained by cyclic shifting the synchronization sequence, and the length of the cyclic shift represents the size of the frequency offset, thereby reducing the local storage capacity.
Let the symbol rate be RsThe sampling multiple is M, N sampling values are totally obtained, and then the frequency domain one-bit frequency deviation step length D is obtainedfComprises the following steps:
Figure BDA0002559814880000062
the maximum Doppler frequency offset of a transmitting end and a receiving end of the VDE satellite is fmIf ± 4kHz, in order to traverse all doppler frequency offsets, the frequency domain needs to be cyclically shifted to the left and right by z times:
Figure BDA0002559814880000063
therefore, in order to take account of the calculation amount, the following method is adopted in the present embodiment: firstly, a larger frequency interval Deltax is set1And obtaining a reference frequency set, and performing frequency correlation synchronization on each assumed component in the set to obtain the frequency offset estimation value
Figure BDA0002559814880000064
The frequency deviation estimated value is obtained
Figure BDA0002559814880000065
As the midpoint of the next search, expand Δ x forward and backward12 as search range, at a smaller interval Δ x2Frequency correlation is carried out to obtain the frequency midpoint of the next frequency deviation estimation
Figure BDA0002559814880000066
Then, a smaller frequency interval Deltax is set3Making frequency dependentTo obtain the final frequency offset estimation result
Figure BDA0002559814880000067
The three-level frequency offset estimation is completed step by step in the process, and the coarse, fine and fine synchronization of the frequency is realized.
Referring to fig. 1 again, the AFC loop provided in this embodiment includes a mixer, a low-pass filter, a decision device, a phase detector, a loop filter, a phase controller, and a voltage controlled oscillator (NCO) that are sequentially connected in a unidirectional annular manner. Two AFC loops are connected in series by an AFC module of the system, and the tracking and compensation of residual frequency offset are realized by estimating the signal phase in real time. Specifically, an output signal of the frequency-dependent synchronization module is input to a mixer of the first-stage AFC loop to be mixed with an output of the voltage-controlled oscillator of the first-stage AFC loop, an output end of a loop filter of the first-stage AFC loop is connected with an input end of a loop filter of the second-stage AFC loop, an output signal of the frequency-dependent synchronization module is processed by the data delay module and then is input to the mixer of the second-stage AFC loop to be mixed with an output of the voltage-controlled oscillator of the second-stage AFC loop, and a low-pass filter of the second-stage AFC loop outputs a signal.
Specifically, in the system provided in this embodiment, after entering the AFC loop, the output signal of the frequency-dependent synchronization module is divided into two in-phase and quadrature branches, and the two input signals are multiplied by a voltage-controlled oscillator (NCO) by mixers of the two AFC loops to obtain a mixing signal; the mixing signals pass through a low-pass filter to obtain two paths of low-pass signals, and the two paths of low-pass signals enter a phase discriminator to calculate the phase error direction to carry out phase error direction estimation after entering a decision device to judge true; and then after passing through a loop filter and a phase controller, obtaining a frequency control word to adjust the output frequency of the NCO so as to realize phase compensation on the received signal until the frequency synchronization is recovered, and keeping closed loop feedback and tracking calibration. The receiving end utilizes a structure of connecting two stages of AFC loops in series, namely, utilizes two stages of AFC loops with the same structure but different loop filter coefficients to respectively control the convergence speed and the tracking smoothness (as shown in FIG. 2).
The Costas loop is set to receive signals as follows:
Figure BDA0002559814880000071
wherein, I (t), Q (t) are amplitudes of components of the received signal, fc，
Figure BDA0002559814880000072
Respectively representing the received signal frequency and phase. Let the orthogonal carrier signal generated by the NCO be:
c(t)＝sin(2πfct+θ)，
in the above formula fcAnd θ represent the frequency and phase of the quadrature carrier signal, respectively. The received signal multiplied by the orthogonal carrier signal generated by the NCO and passed through the low pass filter is:
Figure BDA0002559814880000073
the received signal multiplied by the in-phase carrier signal generated by the NCO and passed through the low pass filter is:
Figure BDA0002559814880000074
the product of the two formulas can be obtained:
Figure BDA0002559814880000075
if the above formula is used as a phase discrimination expression, the phase discrimination calculation result is related to not only the phase difference but also the amplitude of the in-phase and quadrature components of the received signal, which may cause the phase discrimination performance to be degraded.
Considering the following phase discrimination expression, the phase discrimination result p is:
p＝sgn(IK×Qk×(IK+Qk)×(IK-Qk))
＝sgn(IK×Qk)×sgn((IK+Qk)×(IK-Qk))。
wherein the content of the first and second substances,
Figure BDA0002559814880000081
when | i (t) | ═ q (t) |,
Figure BDA0002559814880000082
therefore, after the phase discrimination is changed from the direct-decision phase discrimination to the symbol phase discrimination, as long as the signal satisfies the condition of | i (t) | ═ q (t) |, the phase difference direction between the received signal and the NCO output signal can be judged according to the symbol of the phase discrimination expression, and then the frequency compensation is completed by controlling the subsequent loop filter and the orthogonal carrier signal output by the NCO.
The above solution has the following disadvantages: the input signal must satisfy | i (t) | ═ q (t) |. However, in VDE systems, there are three modulation schemes: pi/4QPSK, 8PSK and 16QAM (as shown in FIG. 3), the former two modulation modes can satisfy the condition, but 16QAM does not satisfy the condition, and 16QAM is most sensitive to frequency offset. Meanwhile, for the VDE burst signal, the modulation system of the burst data frame is unknown to the receiving end, and the frequency synchronization method must have universality. For this embodiment, it is proposed to set a priori condition before performing symbol phase discrimination: before an output signal of the decision device enters the phase discriminator, signal sampling points of the output signal need to meet the following requirements:
Figure BDA0002559814880000083
wherein α is 0.618, QKFor the signal, I, of the mixer input signal multiplied by an in-phase carrier signal generated by the NCO and passed through a low-pass filterKThe input signal to the mixer is the signal multiplied by the quadrature carrier signal generated by the NCO and passed through a low pass filter. The present embodiment sets a priori condition before phase detection, and uses the above-mentioned decision formula to make the signal sampling points for phase detection satisfy that the in-phase and quadrature components have equal amplitude values, i.e., | i (t) | q (t) |, so as to avoid the situation of false phase detection that may be caused when symbol phase detection is applied to 16QAM modulation signals in VDE,the symbol phase discrimination efficiency is ensured, and meanwhile, the symbol phase discrimination device has universality.
The phase discriminator uses a general Costas loop to multiply and discriminate the phase, obtains a direction signal of a phase error in a mode of symbol phase discrimination, and outputs the direction signal to the loop filter. Based on the traditional Costas loop multiplication phase discrimination principle, the phase discrimination mode is improved into more efficient symbol phase discrimination, namely, the symbol of a phase discrimination result is extracted, and the direction (+1, -1) of a phase error is identified to compensate the phase.
In this embodiment, the loop filter structure used is as shown in fig. 4. The loop filter is a second-order loop filter, in fig. 4, Ga is a proportionality constant of the second-order loop filter for phase offset, and Gb is an integration constant for adjusting frequency offset. The setting of the above-mentioned constants will affect the capture range, convergence speed, convergence smoothness, and the like of the loop. In this embodiment, the proportionality constant Ga of the loop filter of the first-stage AFC loop is set to 1/28With an integration constant Gb parameter of 1/215(ii) a The proportionality constant Ga of the loop filter of the two-stage AFC loop is 1/29Integration constant Gb is 1/218. The AFC module of the system connects AFC loops using different loop filters in series, so that a phase error signal obtained after convergence of a primary AFC loop is used as an initial value of a secondary AFC loop to enable the secondary AFC loop to quickly converge, and meanwhile, a loop coefficient set value of the secondary AFC is smaller than that of the primary AFC loop and used for adjusting the precision of an output phase error signal, and finally, quick synchronization and stable tracking of frequency deviation are achieved.
After the symbol phase discrimination result (+1, -1) enters the loop filter, the loop filter establishes a feedback loop for the Costas loop to ensure that the signal can be quickly resynchronized when losing lock. When the result of the phase discriminator is positive, the loop filter inputs + 1; when the phase detector result is negative, the loop filter inputs-1. And the input of the loop filter module is a direction signal (+1, -1) output by the phase discrimination module, and the direction signal is used for controlling a phase error signal output by the loop filter. In addition, the convergence speed and the compensation accuracy can be changed by adjusting the coefficients of the loop filter. The loop filter establishes the dynamic characteristic of a feedback loop for the AFC loop, and ensures that the AFC loop can quickly recapture signals when the system is instantaneously unlocked due to noise.
The phase error signal output by the loop filter enters a phase controller, and the phase controller accumulates and sums the value of the phase error signal from the loop filter and the original accumulated value to generate a frequency control word and outputs the frequency control word to a voltage controlled oscillator (NCO).
The voltage controlled oscillator (NCO) controls the frequency and phase of the output signal according to the frequency control word described above to achieve frequency compensation of the received signal.
The following further exemplifies the system working process provided in this embodiment with an application:
taking a VDE satellite uplink as an example, the symbol rate Rs33.6ksps, the sampling multiple is M-4, and N-3584 sampling points are all used, so that the frequency domain frequency offset step size D of one bit is obtainedfComprises the following steps:
Figure BDA0002559814880000101
the maximum Doppler frequency offset of a transmitting end and a receiving end of the VDE satellite is fmIf it is + -4 kHz, in order to traverse all doppler frequency offset cases, it needs to cyclically shift the frequency domain to the left and right by z times,
Figure BDA0002559814880000102
namely, according to S (f) after FFT of the original local synchronous sequence0) And performing 215 times of cyclic shift on the frequency domain to obtain local sequences corresponding to different frequency offsets.
Setting the frequency estimation interval of coarse synchronization as Deltax by three-stage frequency offset estimation1If 375Hz, then for frequency offset within ± 4kHz in VDE, there are 23 local reference frequencies in the reference frequency set, and a frequency estimation is obtained
Figure BDA0002559814880000103
The estimation error can then be limited to
Figure BDA0002559814880000104
Within the range; setting the frequency interval of fine synchronization to Deltax2When the frequency is 37.5Hz, the reference frequency set has 11 reference frequencies, and the estimated value is obtained
Figure BDA0002559814880000105
The estimation error may then be limited to
Figure BDA0002559814880000106
Performing the following steps; to obtain higher estimation accuracy, the fine synchronization frequency interval is set to Δ x31.5Hz, there are 26 reference frequencies in the reference frequency set. Therefore, the method of three-level frequency offset estimation only needs to traverse 60 reference frequencies, the estimation precision is +/-1.5 Hz, and the calculation amount is greatly saved compared with the original 215 types. Further, those skilled in the art can also flexibly adjust the frequency intervals of coarse, fine and fine synchronization according to the requirements of estimated speed and precision.
The general Costas loop module shown in fig. 2 is implemented as follows:
the consideration of signal sampling points entering the VDE phase demodulation module needs to satisfy
Figure BDA0002559814880000111
In the formula, α is 0.618. And the two-stage AFC loop filter coefficients are respectively set to
Ga1＝1/28，Gb1＝1/215，
Ga2＝1/29，Gb2＝1/218。
Matlab is used for simulation, and when the frequency offset of the received signal is-2 kHz and the phase offset is 10 degrees, simulation results are shown in FIGS. 5A, 5B and 5C and FIGS. 6A, 6B and 6C, which are simulation results under 8PSK and 16QAM modulation respectively. It can be seen that the AFC loop not only achieves compensation of the residual frequency offset of the frequency-dependent synchronization module, but also keeps the subsequent signals converged. Therefore, the frequency synchronization system suitable for the VDE multi-modulation system has a good application effect.
The frequency synchronization system suitable for the VDE multi-modulation system can carry out coarse, fine and fine estimation on frequency deviation by adopting a quick and efficient three-level frequency correlation technology under a VDE burst signal; and the two-stage series general improved Costas loop technology is utilized to realize the rapid synchronization and the stable tracking of the frequency, thereby improving the comprehensive processing capability. The system can adapt to all modulation systems of the VDE, so that a receiving end can quickly obtain frequency synchronization on the premise of not knowing a modulation mode of a received signal, and the system has important significance for receiving the target signals of the VDE shore base and the space base.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to make modifications or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A frequency synchronization system adapting to a VDE multi-modulation system is characterized by comprising a frequency correlation synchronization module and an AFC module, wherein the frequency correlation synchronization module is used for carrying out coarse frequency synchronization, fine frequency synchronization and fine frequency synchronization on a received signal, the AFC module comprises two stages of AFC rings which are connected in series, the first stage of AFC ring is used for carrying out rapid synchronization processing on an output signal of the frequency correlation synchronization module, and the second stage of AFC ring is used for carrying out accurate tracking compensation on frequency deviation on the output signal of the frequency correlation synchronization module.
2. The frequency synchronization system according to claim 1, wherein the frequency-dependent synchronization module comprises a coarse synchronization module, a fine synchronization module, and a fine synchronization module, which are connected in series in sequence, and are respectively configured to perform coarse synchronization, fine synchronization, and fine synchronization processing on the received signal with respect to a signal frequency offset.
3. The frequency synchronization system adapted to the VDE multi-modulation system according to claim 1, wherein the AFC loop includes a mixer, a low pass filter, a decision device, a phase detector, a loop filter, a phase controller, and a voltage controlled oscillator, which are sequentially connected in a unidirectional and annular manner, the mixer multiplies an input signal by an output signal of the voltage controlled oscillator to obtain a mixed signal, the mixed signal is low-pass filtered by the low pass filter and then input to the decision device for decision, the phase detector performs phase error direction estimation, and an updated frequency control word is obtained by the loop filter and the phase controller to adjust an output frequency of the voltage controlled oscillator, thereby implementing frequency compensation on the input signal;
the output signal of the frequency-dependent synchronization module is input to the mixer of the first-stage AFC loop to be multiplied by the output of the voltage-controlled oscillator of the first-stage AFC loop, the output end of the loop filter of the first-stage AFC loop is connected with the input end of the loop filter of the second-stage AFC loop, and the output of the low-pass filter of the second-stage AFC loop is used for obtaining a signal with accurate tracking compensation.
4. The frequency synchronization system of claim 3, wherein the input signal of the primary AFC loop is processed by the data delay module and then input to the mixer of the secondary AFC loop.
5. The frequency synchronization system of claim 3, wherein the decision device is configured with a priori conditions: the output signal of the decision device needs to satisfy the signal sampling point before entering the phase discriminator:
Figure FDA0002559814870000021
wherein α is 0.618, QKFor the signal, I, of the mixer input signal multiplied by an in-phase carrier signal generated by the NCO and passed through a low-pass filterKThe input signal to the mixer is the signal multiplied by the quadrature carrier signal generated by the NCO and passed through a low pass filter.
6. The frequency synchronization system of the adaptive VDE multi-modulation system according to claim 3, wherein the phase detector uses a common Costa loop to perform multiplication phase detection, obtains a direction signal (+1, -1) of the phase error by means of sign phase detection, and outputs the direction signal to the loop filter.
7. The frequency synchronization system of claim 6, wherein the loop filter establishes a feedback loop for the Costas loop, the loop filter input +1 when the phase detector result is positive; when the phase detector result is negative, the loop filter inputs-1.
8. The frequency synchronization system according to claim 3, 6 or 7, wherein the loop filter is a second order loop filter, and wherein the coefficients of the loop filter of the first order AFC loop are larger than the coefficients of the loop filter of the second order AFC loop.
9. The frequency synchronization system of the adaptive VDE multi-modulation scheme of claim 3, wherein the phase controller cumulatively sums the value of the phase error signal from the loop filter with an original accumulated value to generate the frequency control word.
10. The frequency synchronization system of claim 9, wherein the voltage-controlled oscillator controls the frequency and phase of its output signal according to the frequency control word to achieve frequency compensation of the received signal.
CN202010608584.6A 2020-06-29 2020-06-29 Frequency synchronization system adapting to VDE multi-modulation system Active CN111884964B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010608584.6A CN111884964B (en) 2020-06-29 2020-06-29 Frequency synchronization system adapting to VDE multi-modulation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010608584.6A CN111884964B (en) 2020-06-29 2020-06-29 Frequency synchronization system adapting to VDE multi-modulation system

Publications (2)

Publication Number Publication Date
CN111884964A true CN111884964A (en) 2020-11-03
CN111884964B CN111884964B (en) 2021-05-04

Family

ID=73157583

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010608584.6A Active CN111884964B (en) 2020-06-29 2020-06-29 Frequency synchronization system adapting to VDE multi-modulation system

Country Status (1)

Country Link
CN (1) CN111884964B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113794670A (en) * 2021-09-18 2021-12-14 上海航天电子通讯设备研究所 Demodulation system for 16QAM (Quadrature amplitude modulation) signals in VDES (vertical double-ended vertical data ES)
CN115174332A (en) * 2022-06-30 2022-10-11 成都天奥信息科技有限公司 Ship/standard load VDES system communication implementation method
WO2023109896A1 (en) * 2021-12-15 2023-06-22 大连海事大学 Improved carrier frequency offset synchronization method for vde-ter system

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471252A (en) * 2002-07-26 2004-01-28 华为技术有限公司 Frequency deviation correction method for base station received signal and Rake receiver
CN101160720A (en) * 2005-03-01 2008-04-09 高通股份有限公司 Dual-loop automatic frequency control for wireless communication
CN102045082A (en) * 2009-10-12 2011-05-04 展讯通信（上海）有限公司 Control method of dual-standby terminal and AFC (automatic frequency control) loop of dual-standby terminal
CN102624419A (en) * 2012-04-23 2012-08-01 西安电子科技大学 Carrier synchronization method of burst direct sequence spread spectrum system
CN110417693A (en) * 2018-04-27 2019-11-05 展讯通信（上海）有限公司 A kind of frequency deviation adaptive tracing compensation method, device and user equipment
CN110649913A (en) * 2018-06-27 2020-01-03 北京松果电子有限公司 Frequency adjustment method and device for crystal oscillator, storage medium and electronic equipment
CN111147413A (en) * 2019-12-31 2020-05-12 东方红卫星移动通信有限公司 Short-time burst demodulation method for low-earth-orbit satellite

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471252A (en) * 2002-07-26 2004-01-28 华为技术有限公司 Frequency deviation correction method for base station received signal and Rake receiver
CN101160720A (en) * 2005-03-01 2008-04-09 高通股份有限公司 Dual-loop automatic frequency control for wireless communication
CN102045082A (en) * 2009-10-12 2011-05-04 展讯通信（上海）有限公司 Control method of dual-standby terminal and AFC (automatic frequency control) loop of dual-standby terminal
CN102624419A (en) * 2012-04-23 2012-08-01 西安电子科技大学 Carrier synchronization method of burst direct sequence spread spectrum system
CN110417693A (en) * 2018-04-27 2019-11-05 展讯通信（上海）有限公司 A kind of frequency deviation adaptive tracing compensation method, device and user equipment
CN110649913A (en) * 2018-06-27 2020-01-03 北京松果电子有限公司 Frequency adjustment method and device for crystal oscillator, storage medium and electronic equipment
CN111147413A (en) * 2019-12-31 2020-05-12 东方红卫星移动通信有限公司 Short-time burst demodulation method for low-earth-orbit satellite

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YANGYANG CAO: "Two stage frequency offset pre-compensation scheme for satellite mobile terminals", 《IEEE》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113794670A (en) * 2021-09-18 2021-12-14 上海航天电子通讯设备研究所 Demodulation system for 16QAM (Quadrature amplitude modulation) signals in VDES (vertical double-ended vertical data ES)
CN113794670B (en) * 2021-09-18 2023-08-22 上海航天电子通讯设备研究所 Demodulation system of 16QAM signal in VDES
WO2023109896A1 (en) * 2021-12-15 2023-06-22 大连海事大学 Improved carrier frequency offset synchronization method for vde-ter system
CN115174332A (en) * 2022-06-30 2022-10-11 成都天奥信息科技有限公司 Ship/standard load VDES system communication implementation method
CN115174332B (en) * 2022-06-30 2023-11-10 成都天奥信息科技有限公司 Ship/standard VDES system communication implementation method

Also Published As

Publication number Publication date
CN111884964B (en) 2021-05-04

Similar Documents

Publication Publication Date Title
CN111884964B (en) Frequency synchronization system adapting to VDE multi-modulation system
US5608764A (en) OFDM synchronization demodulation circuit
US4896336A (en) Differential phase-shift keying demodulator
EP0772330A2 (en) Receiver and method for receiving OFDM signals
CN105245303A (en) High-speed burst demodulation synchronization system
WO2001020863A9 (en) Method and apparatus for carrier phase tracking
CN110300079B (en) MSK signal coherent demodulation method and system
US7184504B2 (en) Receiver having an integrated clock phase detector
EP1589713A2 (en) Quadrature modulator with compensation of I/Q mismatch
JP3077881B2 (en) Demodulation method and demodulation device
JPH03188738A (en) System and apparatus for psk signal demodulation
CN110912847A (en) GMSK signal demodulation method
US5627861A (en) Carrier phase estimation system using filter
JP2008530951A (en) Demodulator and receiver for pre-encoded partial response signals
US6947504B1 (en) Frequency synchronizer
CN111314262B (en) 16QAM carrier synchronization system in low signal-to-noise ratio environment
CN109889461B (en) Low-complexity parallel carrier recovery system and method thereof
US5914985A (en) Digital demodulator
EP1012966B1 (en) Apparatus and method for block phase estimation
WO2014129978A1 (en) Digital auto frequency control for a general purpose if subsystem with multi-modulation schemes
US6748030B2 (en) Differential phase demodulator incorporating 4th order coherent phase tracking
Meng et al. Frequency offset estimation in the intermediate frequency for satellite-based AIS signals
CN111917452B (en) Method and system for inhibiting carrier tracking by large frequency offset
Hinedi NASA's next generation all-digital deep space network breadboard receiver
Maya et al. A high data rate BPSK receiver implementation in FPGA for high dynamics applications

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant