CN111884750B - Synchronous measurement and control network architecture of array system - Google Patents
Synchronous measurement and control network architecture of array system Download PDFInfo
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- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H04J3/02—Details
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- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
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Abstract
An array type system synchronous measurement and control network architecture is a tree network architecture and comprises three levels: the system comprises a measurement and control core layer which is far away from a measurement and control object and consists of one primary measurement and control server, a field control layer which is close to the measurement and control object and consists of a plurality of secondary measurement and control servers, and the measurement and control object is an equipment layer which consists of an array system. The three levels are respectively corresponding to a tree root, a subtree root and a leaf node in the tree network structure. The three levels are in turn cascaded with a signal synchronization network through a data synchronization network based on optical fiber communication. The primary measurement and control server is connected with all the secondary measurement and control servers through a plurality of mutually independent SERDES buses, and each secondary measurement and control server is connected with the corresponding equipment through a plurality of mutually independent SERDES buses, so that a data synchronization network is formed. The first-stage measurement and control server outputs homologous IO signals to all the second-stage measurement and control servers, and the second-stage measurement and control servers output homologous IO signals to all the corresponding devices, so that a signal synchronization network is formed.
Description
Technical Field
The invention relates to an array system synchronous measurement and control network architecture.
Background
In the electromagnetic ejection system, an array pulse generator set is used for providing high-power pulses, so that instantaneous high-voltage and high-current discharge required during electromagnetic ejection is realized. The electromagnetic catapulting system has the advantages that strong electromagnetic interference is caused by pulse high voltage and high current, how to reliably control the synchronous work of the array type pulse generator sets, and how to process the operation data of the array type pulse generator sets in real time in parallel, so that all the generator sets can simultaneously perform instant discharge with the maximum capacity, or different generator sets can be respectively controlled to perform instant discharge sequences, or residual electricity collection and redistribution discharge functions are realized, and the electromagnetic catapulting system is the key for judging whether the electromagnetic catapulting system can successfully launch.
Most of traditional multi-device measurement and control networks are based on serial buses such as CAN, ethernet and serial ports for networking. As shown in fig. 1, common networking methods include a bus network, a ring network, a star network, and the like. The serial buses and the networking mode cannot meet the synchronous measurement and control requirements of the array type pulse generator set. When the array type pulse generator is subjected to bus type networking, only one device can communicate with the measurement and control server at a time, namely all generator controller time division multiplexing buses and the measurement and control server perform data interaction, the communication mode cannot realize synchronous control on all the devices, and if 90 devices are in total communication with the measurement and control server, the time consumed by each device for communication with the measurement and control server is 10 mus, the time consumed by 90 devices is 900 mus, namely the difference between the first device and the last device is 890 mus, which is multiple times of the motor control period. When the array type pulse generator is subjected to ring network networking, data streams pass through all devices in a loop in series, and when the number of the devices is large, the response time of the network is prolonged, and synchronous control of all the devices cannot be realized. When star-shaped network networking is carried out on the array type pulse generator, the measurement and control server positioned in the network center cannot provide enough branches, namely, a measurement and control server product comprising 90 paths of CAN or 90 paths of serial ports is not provided. The network architectures are that one measurement and control server is connected with a plurality of devices, data of all the devices are collected to the measurement and control server for processing, the measurement and control server is heavy in burden, cooperation among different devices is totally dependent on instructions sent by the measurement and control server, and the synchronism is poor; the process cycle of the measurement and control server is mostly millisecond-level and is far longer than the control cycle of the array type pulse generator set, and the real-time control requirement of the array type pulse generator set cannot be met; the indiscriminate one-to-many connection mode brings difficulty to the development of system equipment fault processing software; the traditional connection mode has weak interference resistance and unstable communication.
Disclosure of Invention
The invention aims to overcome the defects that the conventional measurement and control network cannot realize the synchronous control function and the real-time control function of an array system, fault equipment is difficult to process, the anti-interference capability is weak and the like, and provides an array system synchronous measurement and control network architecture.
The invention adopts the following technical scheme:
the invention relates to a three-layer tree network structure comprising a tree root, a plurality of subtree roots and a plurality of leaf nodes, wherein one tree root is directly connected with all subtree roots, all subtree roots are not connected, any subtree root is at least connected with one leaf node, any leaf node can only be connected with one subtree root, all leaf nodes belonging to the same subtree root are not connected, leaf nodes belonging to different subtree roots are not connected, and the leaf nodes are not connected with the tree root. In the invention, a primary measurement and control server far away from a measurement and control object is a tree root, and the level of the primary measurement and control server is named as a measurement and control core layer. The secondary measurement and control server close to the measurement and control object is a subtree root, one secondary measurement and control server is a subtree root, and the level where all the secondary measurement and control servers are located is named as a field measurement and control layer. The measurement and control object, namely the equipment in the array system, is a leaf node, one equipment is a leaf node, and the hierarchy where all the leaf nodes are located is named as an equipment layer. The three layers are cascaded with a signal synchronization network through a data synchronization network based on optical fiber communication. The primary measurement and control server is connected with all the secondary measurement and control servers through a plurality of mutually independent SERDES buses capable of synchronous parallel communication through optical fibers, each secondary measurement and control server is connected with corresponding equipment through a plurality of mutually independent SERDES buses capable of synchronous parallel communication through optical fibers, and a data synchronization network is formed through the connection mode. The first-level measurement and control server outputs homologous IO signals to all the second-level measurement and control servers through optical fibers, the second-level measurement and control servers output homologous IO signals to all corresponding devices through the optical fibers, and a signal synchronization network is formed through the connection mode. When the system is designed, the optical fiber lengths between the primary measurement and control server and all the secondary measurement and control servers are ensured to be equal, and the optical fiber lengths between all measurement and control objects, namely the equipment in the array system, connected with any one secondary measurement and control server are ensured to be equal. Ignoring delay difference caused by different actual propagation paths of light in a plurality of optical fibers with equal length, enabling homologous IO signals to reach each target device at the same time, wherein the homologous IO signals can be used as a synchronous reference of the target devices and can also be used for system emergency stop; in the SERDES interface which is output by each measurement and control server and is executed in parallel, under the coding mode of 8B10B, the data synchronization error between any two paths does not exceed the sending time of two 8B10B codes, and if the SERDES bandwidth is 1.25GBits, the synchronization error does not exceed 16ns, namely, the primary measurement and control server sends command data to all the secondary measurement and control servers at the same time, and the time difference of receiving the data by all the secondary measurement and control servers does not exceed 16ns.
The measurement and control core layer is composed of a first-level measurement and control server and belongs to tree roots in a three-layer tree-type network structure. The measurement and control server comprises a primary embedded industrial personal computer, a PXI board card and a primary synchronous controller; the primary synchronous controller is connected with the PXI board card through optical fibers, and the PXI board card is inserted into the primary embedded industrial personal computer case and is connected with the primary embedded industrial personal computer through a PXI interface. The first-level embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and man-machine interaction functions. And the PXI board card realizes the conversion between the optical interface and the PXI interface. The primary synchronous controller consists of an FPGA board card, an SFP optical module and a low-frequency optical fiber transmitter and is used for realizing synchronous control on all the secondary measurement and control servers. The FPGA board card selects the FPGA with an ARM inner core based on the system on chip as a main control chip. The ARM core executes an algorithm which has high real-time requirement and is related to the functions of an array system, monitors the running states of all secondary measurement and control servers in a field measurement and control layer, switches out a fault secondary measurement and control server, verifies an advanced data algorithm and error code retransmission process management functions, and comprehensively plans the working states of the secondary measurement and control servers in all the field measurement and control layers; the field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification. When N secondary measurement and control servers exist in the three-layer tree network structure, the value range of N is determined by the actual grouping situation of the array system and the maximum number of the transceivers of the FPGA selected by the primary synchronous controller, and the grouping number of the array system is at least 1 less than the number of the transceivers of the FPGA of the selected model; an FPGA board card on a primary synchronous controller is configured with N +1 paths of SERDES interfaces which are mutually independent and can run in parallel, wherein the N paths of SERDES interfaces are connected with N secondary measurement and control servers through optical fibers after being subjected to photoelectric conversion by an SFP optical module, and the rest paths of SERDES interfaces are connected with a PXI board card through optical fibers after being subjected to photoelectric conversion by the SFP optical module; meanwhile, N paths of homologous IO signals are configured on the FPGA board card on the primary synchronous controller, converted by the low-frequency optical fiber transmitter and then connected with N secondary measurement and control servers through optical fibers.
The field measurement and control layer consists of N secondary measurement and control servers, belongs to the subtree root in a three-layer tree network structure, and N is the number of the subtree roots. Each measurement and control server comprises a secondary embedded industrial personal computer, a PXI board card and a secondary synchronous controller; the secondary synchronous controller is connected with the PXI board card through optical fibers, and the PXI board card is inserted into the secondary embedded industrial personal computer case and is connected with the secondary embedded industrial personal computer through a PXI interface. The second-level embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and man-machine interaction functions. And the PXI board card realizes the conversion between the optical interface and the PXI interface. The secondary synchronous controller consists of an FPGA board card, an SFP optical module, a low-frequency optical fiber transmitter and a low-frequency optical fiber receiver and is used for realizing synchronous control, data processing and uploading of all equipment connected with the secondary measurement and control server. And the FPGA board card selects an FPGA with an ARM core based on a system on a chip as a main control chip. The ARM core executes an algorithm which has high real-time requirement and is related to the functions of the array system, monitors the running states of all equipment in the equipment layer, monitors a high-level data verification algorithm and has an error code retransmission process management function, and overall stages of the working states of all the equipment in the equipment layer; the field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification. When the secondary measurement and control server is provided with X devices, the value range of X is determined by the actual number of each group of devices after the array system is grouped and the maximum number of the transceivers of the FPGA selected by the secondary synchronous controller, and the actual number of each group of devices is at least 2 less than the number of the transceivers of the FPGA of the selected model. The FPGA board card is provided with X +2 paths of SERDES interfaces which are mutually independent and can run in parallel, wherein the X path of SERDES interfaces are connected with X equipment through optical fibers after being subjected to photoelectric conversion by an SFP optical module, one path of SERDES interfaces are connected with a primary measurement and control server through optical fibers after being subjected to photoelectric conversion by the SFP optical module, and the other path of SERDES interfaces are connected with a PXI board card through optical fibers after being subjected to photoelectric conversion by the SFP optical module; configuring X paths of homologous IO output signals, converting the signals by a low-frequency optical fiber transmitter, and connecting the signals with equipment in the X array system through optical fibers; configuring an IO input signal, and receiving an IO output signal transmitted from the primary measurement and control server after the IO input signal is converted by the low-frequency optical fiber receiver.
The equipment layer is composed of all equipment in the array system and belongs to leaf nodes in a tree network structure. The equipment consists of an equipment controller and a communication interface board; the device controller reserves a bus interface and an IO input interface; the communication interface board consists of a bus interface, an IO output interface, an FPGA, an SFP optical module and a low-frequency optical fiber receiver; in the communication interface board, a bus interface is connected with the FPGA, the FPGA is connected with the SFP optical module, and an IO output interface is connected with the low-frequency optical fiber receiver; the bus interface of the communication interface board is connected with the reserved bus interface of the equipment controller; an IO output interface of the communication interface board is connected with an IO input interface reserved by the equipment controller; the bus interface of the communication interface board and the bus interface reserved by the device controller must be the same communication protocol, the bus interface CAN be any one of CAN, SPI, I2C, 323, 422 and 485, and is determined by the actually reserved interface of the device controller, and the bus interface protocol on the communication interface board is configured by FPGA on the communication interface board; an FPGA on the communication interface board configures one path of SERDES interface to be connected with the SFP optical module; the FPGA realizes the interconversion of low-speed data and high-speed SERDES protocol data between the communication interface board and the device controller; the SFP optical module is connected with a secondary measurement and control server corresponding to the equipment through an optical fiber; and the low-frequency optical fiber receiver receives the IO signal sent by the secondary measurement and control server, and is directly connected with the IO interface of the communication interface board after photoelectric conversion. Particularly, when the FPGA with the transceiver is used in the equipment controller, a communication interface board is not required for conversion, a DERDES and an IO interface can be configured through the FPGA, and the FPGA is directly communicated with the secondary measurement and control server after being converted by the SFP module and the low-frequency optical fiber receiver.
The invention has the following characteristics:
(1) Optical fiber communication is adopted among all levels, and the anti-interference capability is improved.
(2) The tree network structure avoids the networking among leaf nodes, reduces the complexity of the system, and any leaf node fails without affecting the communication of the leaf nodes belonging to other subtree roots, thereby facilitating the processing of the failed nodes.
(3) The primary synchronous controller and the secondary synchronous controller introduce a multichannel parallel SERDES optical interface and a homologous IO signal, realize synchronous communication of multiple devices, and ensure the synchronous precision of control data of each node.
(4) The FPGA with an ARM inner core based on a system on chip is introduced into the primary synchronous controller and the secondary synchronous controller, the operation period of the ARM is smaller than the operation period of the embedded industrial personal computer, and the real-time control performance of the system is improved.
Drawings
FIG. 1 is a schematic diagram of three common network structures in a measurement and control network;
FIG. 2 is a schematic diagram of a three-level tree network architecture, taking a 90-node array measurement and control network as an example;
FIG. 3 is a connection relationship among a first subtree root, leaf nodes and tree roots, taking a 90-node array measurement and control network as an example;
fig. 4 is an implementation manner of synchronously controlling 15 nodes by a homologous IO port.
Detailed Description
The invention is further illustrated by the following description in conjunction with the figures and the specific examples.
Fig. 2 is a schematic diagram of a synchronous measurement and control network architecture of an array type pulse generator control system according to an embodiment of the present invention. As shown in fig. 2, the device layer of the synchronous measurement and control network is composed of a plurality of array pulse generator controllers and a communication interface board. Each pulse generator controller is matched with a communication interface board, and one pulse generator controller and one communication interface board form one device, namely a measurement and control object. And grouping the devices according to actual requirements. The synchronous measurement and control network aims to realize reliable synchronous high-current high-voltage pulse discharge, residual electricity collection and transfer and residual electricity discharge functions in the array type pulse generator controller group and among different groups. The synchronous measurement and control network architecture has the functions of real-time monitoring, state display and instruction issuing of each device, the functions of device cooperation in the same group and cooperation among different groups, the functions of system fault diagnosis and processing and the function of emergency stop. The equipment layer of the synchronous measurement and control network frame is composed of 90 pieces of equipment, every 6 pieces of equipment form a group, a secondary measurement and control server is distributed for the group, 15 secondary measurement and control servers are totally distributed, all the secondary measurement and control servers form a field measurement and control layer, a primary measurement and control server is distributed for the 15 secondary measurement and control servers, and a measurement and control core layer is formed by the primary measurement and control server. Fig. 3 details a connection relationship between a first group of devices, a secondary measurement and control server corresponding to the first group of devices, and a primary measurement and control server in the synchronous measurement and control network. Fig. 4 is an implementation manner of synchronously controlling 15 devices by a homologous IO port.
The measurement and control core layer is composed of a first-level measurement and control server and belongs to tree roots in a three-layer tree network structure. The measurement and control server comprises a primary embedded industrial personal computer, a PXI board card and a primary synchronous controller; the primary synchronous controller is connected with the PXI board card through optical fibers, and the PXI board card is inserted into the primary embedded industrial personal computer case and is connected with the primary embedded industrial personal computer through a PXI interface. The primary embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and human-computer interaction functions. And the PXI board card realizes the conversion between the optical interface and the PXI interface. The primary synchronous controller consists of an FPGA board card, an SFP optical module and a low-frequency optical fiber transmitter and is used for realizing synchronous control on all the secondary measurement and control servers. The FPGA board card selects an FPGA with an ARM inner core based on a system on chip as a main control chip, the system selects XC7Z035-2FFG900I of Xilinx company, the type of FPGA comprises 16 transceivers, and 16 SERDES can be configured. The ARM inner core executes a secondary measurement and control server cooperation algorithm, monitors the running states of all secondary measurement and control servers in the field measurement and control layer, switches out fault secondary measurement and control servers, a high-level data verification algorithm and an error code retransmission process management function, and overall stages of the working states of the secondary measurement and control servers in all the field measurement and control layers. The field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification. In the system, 16 independent and parallel-running SERDES interfaces are configured on an FPGA board card on a primary synchronous controller, wherein 15 SERDES interfaces are connected with 15 secondary measurement and control servers through optical fibers after being subjected to photoelectric conversion by an SFP optical module, and the remaining SERDES interfaces are connected with a PXI board card through optical fibers after being subjected to photoelectric conversion by the SFP optical module, as shown in FIG. 3. Meanwhile, 15 paths of homologous IO signals are configured on the FPGA board card on the primary synchronous controller, and are converted by the low-frequency optical fiber transmitter and then connected with 15 secondary measurement and control servers through optical fibers, as shown in FIG. 4. The low-frequency optical fiber transmitter is HFBR-1414TZ manufactured by BROADCOM.
15 secondary measurement and control servers form a field measurement and control layer, the secondary measurement and control servers belong to subtree roots in a three-layer tree-type network structure, and the system is provided with 15 subtree roots. Each measurement and control server comprises a secondary embedded industrial personal computer, a PXI board card and a secondary synchronous controller. The secondary synchronous controller is connected with the PXI board card through optical fibers, and the PXI board card is inserted into the secondary embedded industrial personal computer case and is connected with the secondary embedded industrial personal computer through a PXI interface. The second-stage embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and human-computer interaction functions. And the PXI board card realizes the conversion between the optical interface and the PXI interface. The secondary synchronous controller consists of an FPGA board card, an SFP optical module, a low-frequency optical fiber transmitter and a low-frequency optical fiber receiver and is used for realizing synchronous control, data processing and uploading of all equipment connected with the secondary measurement and control server. The FPGA board card selects an FPGA with an ARM core based on a system on a chip as a main control chip, and XC7Z035-2FFG900I of Xilinx company is selected in the system. The ARM core executes a 6-device cooperation algorithm in the group, monitors the running state of 6 devices, performs a high-level data verification algorithm and performs an error code retransmission process management function, and overall stages of the working states of the 6 devices are realized; the field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification. As shown in fig. 3, in this example, the FPGA board card configures 8 independent SERDES interfaces that can operate in parallel, where 6 SERDES interfaces are connected to 6 devices through an optical fiber after being subjected to photoelectric conversion by an SFP optical module, one SERDES interface is connected to the first-level measurement and control server through an optical fiber after being subjected to photoelectric conversion by an SFP optical module, and one SERDES interface is connected to the PXI board card through an optical fiber after being subjected to photoelectric conversion by an SFP optical module; configuring 6 paths of homologous IO output signals, converting the signals by a low-frequency optical fiber transmitter, and connecting the signals with 6 devices through optical fibers; configuring 1 path of IO input signals, and receiving the IO output signals transmitted by the primary measurement and control server after the IO output signals are converted by the low-frequency optical fiber receiver. The low-frequency optical fiber transmitter is HFBR-1414TZ manufactured by BROADCOM. The low-frequency optical fiber receiver is AFBR-2418TZ produced by BROADCOM company.
The 90 devices constitute the device layer. The device belongs to a leaf node in a tree network structure, which in this example comprises 90 leaf nodes. The device in this example consists of a pulse generator controller and a communication interface board. The pulse generator controller reserves an SPI bus interface and an IO input interface; the communication interface board reserves an SPI bus interface and an IO output interface; the pulse generator controller is connected with the communication interface board through the SPI bus interface and the IO interface. The communication interface board is composed of an FPGA, an SFP optical module and a low-frequency optical fiber receiver. In the system, the FPGA selects XC7A12T-1CPG238I of Xilinx company. The FPGA on the communication interface board configures a path of SPI bus to be connected with an SPI bus interface on the interface board; an FPGA on the communication interface board configures one path of SERDES interface to be connected with the SFP optical module; the FPGA realizes the mutual conversion of the low-speed SPI protocol data and the high-speed SERDES protocol data; the SFP optical module is connected with a secondary measurement and control server corresponding to the equipment through optical fibers. And the low-frequency optical fiber receiver receives an IO signal sent by the secondary measurement and control server, is directly connected with an IO interface of the communication interface board after photoelectric conversion and is sent to the pulse generator controller. The low-frequency optical fiber receiver is AFBR-2418TZ produced by BROADCOM company.
Claims (1)
1. The measurement and control network architecture is characterized in that the measurement and control network architecture is a three-layer tree network structure comprising a tree root, a plurality of subtree roots and a plurality of leaf nodes, wherein one tree root is directly connected with all the subtree roots, all the subtree roots are not connected, any subtree root is connected with at least one leaf node, any leaf node can only be connected with one subtree root, all the leaf nodes belonging to the same subtree root are not connected, the leaf nodes belonging to different subtree roots are not connected, and the leaf nodes are not connected with the tree root; one primary measurement and control server far away from the measurement and control object is a tree root, and the level where the primary measurement and control server is located is a measurement and control core layer; the secondary measurement and control server close to the measurement and control object is a subtree root, one secondary measurement and control server is a subtree root, and the level of all the secondary measurement and control servers is a field measurement and control layer; the method comprises the following steps that a measurement and control object, namely equipment in an array system is a leaf node, one piece of equipment is a leaf node, and the level where all the leaf nodes are located is an equipment layer; all the measurement and control objects connected to the same secondary measurement and control server form a group; the measurement and control core layer, the field measurement and control layer and the equipment layer are cascaded with the signal synchronous network through a data synchronous network based on optical fiber communication; the primary measurement and control server is connected with all the secondary measurement and control servers through a plurality of mutually independent SERDES buses capable of synchronous parallel communication through optical fibers, each secondary measurement and control server is connected with corresponding equipment through a plurality of mutually independent SERDES buses capable of synchronous parallel communication through optical fibers, and a data synchronization network is formed through the connection mode; the first-stage measurement and control server outputs homologous IO signals to all the second-stage measurement and control servers through optical fibers, the second-stage measurement and control servers output homologous IO signals to all corresponding devices through the optical fibers, and a signal synchronization network is formed through the connection mode; the lengths of the optical fibers between the primary measurement and control server and all the secondary measurement and control servers are equal, and the lengths of the optical fibers between all measurement and control objects, namely equipment in the array system, connected with any one secondary measurement and control server are equal;
the measurement and control core layer is composed of a primary measurement and control server; the measurement and control server comprises a primary embedded industrial personal computer, a PXI board card and a primary synchronous controller; the primary synchronous controller is connected with a PXI board card through an optical fiber, and the PXI board card is inserted into the primary embedded industrial personal computer case and connected with the primary embedded industrial personal computer through a PXI interface; the first-stage embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and man-machine interaction functions; the PXI board card realizes the conversion between an optical interface and a PXI interface; the primary synchronous controller consists of an FPGA board card, an SFP optical module and a low-frequency optical fiber transmitter and is used for realizing synchronous control on all the secondary measurement and control servers; the FPGA board card selects an FPGA with an ARM kernel based on a system on a chip as a main control chip; the ARM inner core executes an algorithm related to the functions of the array system, monitors the running states of all secondary measurement and control servers in a field measurement and control layer, switches out a fault secondary measurement and control server, verifies an advanced data algorithm and error code retransmission process management functions, and overall stages of the working states of the secondary measurement and control servers in all the field measurement and control layers; the field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification; when N secondary measurement and control servers exist in the three-layer tree network structure, the value range of N is determined by the actual grouping situation of the array system and the maximum number of the transceivers of the FPGA selected by the primary synchronous controller, and the grouping number of the array system is at least 1 less than the number of the transceivers of the FPGA of the selected model; an FPGA board card on the primary synchronous controller is configured with N +1 paths of SERDES interfaces which are mutually independent and can run in parallel, wherein the N paths of SERDES interfaces are connected with N secondary measurement and control servers through optical fibers after being subjected to photoelectric conversion by SFP optical modules, and the rest paths of SERDES interfaces are connected with a PXI board card through optical fibers after being subjected to photoelectric conversion by the SFP optical modules; meanwhile, N paths of homologous IO signals are configured on an FPGA board card on the primary synchronous controller, and are converted by a low-frequency optical fiber transmitter and then connected with N secondary measurement and control servers through optical fibers;
the field measurement and control layer consists of N secondary measurement and control servers; each measurement and control server comprises a secondary embedded industrial personal computer, a PXI board card and a secondary synchronous controller; the secondary synchronous controller is connected with a PXI board card through an optical fiber, the PXI board card is inserted into the secondary embedded industrial personal computer case and is connected with the secondary embedded industrial personal computer through a PXI interface; the second-stage embedded industrial personal computer consists of an embedded industrial personal computer case, namely a host, a display, a keyboard and a mouse, and is used for realizing state and process display and man-machine interaction functions; the PXI board card realizes the conversion between an optical interface and a PXI interface; the secondary synchronous controller consists of an FPGA board card, an SFP optical module, a low-frequency optical fiber transmitter and a low-frequency optical fiber receiver and is used for realizing synchronous control, data processing and uploading of all equipment connected with the secondary measurement and control server; the FPGA board card selects an FPGA with an ARM core based on a system on a chip as a main control chip; the ARM core executes an algorithm which has high real-time requirement and is related to the functions of the array system, monitors the running states of all equipment in the equipment layer, monitors a high-level data verification algorithm and has an error code retransmission process management function, and overall stages of the working states of all the equipment in the equipment layer; the field programmable gate array realizes communication, logic and IO output functions, and performs data interaction and simple data verification; when the secondary measurement and control server is provided with X devices, the value range of X is determined by the actual number of each group of devices after the array system grouping and the maximum transceiver number of the FPGA selected by the secondary synchronous controller, and the actual number of each group of devices is at least 2 less than the number of the selected type of FPGA transceivers; the FPGA board card is provided with X +2 paths of SERDES interfaces which are mutually independent and can run in parallel, wherein the X path of SERDES interfaces are connected with X equipment through optical fibers after being subjected to photoelectric conversion by an SFP optical module, one path of SERDES interfaces are connected with a primary measurement and control server through optical fibers after being subjected to photoelectric conversion by the SFP optical module, and the other path of SERDES interfaces are connected with a PXI board card through optical fibers after being subjected to photoelectric conversion by the SFP optical module; configuring X paths of homologous IO output signals, converting the signals by a low-frequency optical fiber transmitter, and connecting the signals with equipment in the X array system through optical fibers; configuring an IO input signal, and receiving an IO output signal which is converted by a low-frequency optical fiber receiver and sent by a primary measurement and control server;
the equipment layer consists of all equipment in the array system; the equipment consists of an equipment controller and a communication interface board; the device controller reserves a bus interface and an IO input interface; the communication interface board consists of a bus interface, an IO output interface, an FPGA, an SFP optical module and a low-frequency optical fiber receiver; in the communication interface board, a bus interface is connected with the FPGA, the FPGA is connected with the SFP optical module, and an IO output interface is connected with the low-frequency optical fiber receiver; the bus interface of the communication interface board is connected with the reserved bus interface of the equipment controller; an IO output interface of the communication interface board is connected with an IO input interface reserved by the equipment controller; the bus interface of the communication interface board and the bus interface reserved by the device controller must be the same communication protocol, the bus interface CAN be any one of CAN, SPI, I2C, 323, 422 and 485, which is determined by the actually reserved interface of the device controller, and the bus interface protocol on the communication interface board is configured by FPGA on the communication interface board; an FPGA on the communication interface board configures one path of SERDES interface to be connected with the SFP optical module; the FPGA realizes the interconversion of low-speed data and high-speed SERDES protocol data between the communication interface board and the device controller; the SFP optical module is connected with a secondary measurement and control server corresponding to the equipment through an optical fiber; and the low-frequency optical fiber receiver receives the IO signal sent by the secondary measurement and control server, and is directly connected with the IO interface of the communication interface board after photoelectric conversion.
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