CN111884548B - Motor driving circuit and driving method based on capacitor charging and discharging structure - Google Patents

Motor driving circuit and driving method based on capacitor charging and discharging structure Download PDF

Info

Publication number
CN111884548B
CN111884548B CN202010542159.1A CN202010542159A CN111884548B CN 111884548 B CN111884548 B CN 111884548B CN 202010542159 A CN202010542159 A CN 202010542159A CN 111884548 B CN111884548 B CN 111884548B
Authority
CN
China
Prior art keywords
voltage
duty
duty ratio
vduty
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010542159.1A
Other languages
Chinese (zh)
Other versions
CN111884548A (en
Inventor
沈强
冯光涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elownipmicroelectronics Beijing Co ltd
Original Assignee
Elownipmicroelectronics Beijing Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elownipmicroelectronics Beijing Co ltd filed Critical Elownipmicroelectronics Beijing Co ltd
Priority to CN202010542159.1A priority Critical patent/CN111884548B/en
Publication of CN111884548A publication Critical patent/CN111884548A/en
Application granted granted Critical
Publication of CN111884548B publication Critical patent/CN111884548B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
    • H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
    • H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
    • H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
    • H02P7/24—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
    • H02P7/28—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
    • H02P7/285—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only
    • H02P7/29—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices controlling armature supply only using pulse modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P8/00—Arrangements for controlling dynamo-electric motors of the kind having motors rotating step by step
    • H02P8/14—Arrangements for controlling speed or speed and torque
    • H02P8/18—Shaping of pulses, e.g. to reduce torque ripple
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Abstract

The invention discloses a motor driving circuit and a driving method based on a capacitor charging and discharging structure, wherein the circuit comprises: the circuit comprises a 50% duty cycle clock generator, a duty cycle adjustable clock generator, a monostable trigger and an output selector. The invention adopts a method of generating triangular waves by charging and discharging off-chip capacitors to simultaneously generate square waves with 50% duty ratio, square waves with adjustable duty ratio and monostable trigger pulses. The frequency of the continuous clock and the width of the monostable pulse can be set simultaneously by modifying the value of the off-chip capacitance. Accurate output of 50% duty cycle and frequency is achieved through programmable charge-discharge current adjustment and calibration. The circuit structure is simple, the frequency setting is simple and convenient, and the respective repeated setting is avoided. The frequency variation range is wide, and the application range is wider.

Description

Motor driving circuit and driving method based on capacitor charging and discharging structure
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a motor driving circuit and a driving method based on a capacitor charging and discharging structure.
Background
In the field of motor control and driving, PWM clock signals are often used to drive dc motors. The direct current motor has the advantages of good starting and speed regulating performance, wide and smooth speed regulating range, strong overload capacity, small influence by electromagnetic interference, good starting characteristic and speed regulating characteristic, low maintenance cost, energy conservation and environmental protection. But dc motors are relatively expensive and have a short life. Dc motors are typically applied for closed loop control in a feedback loop. The system converts the output analog quantity into a level signal through sensors such as a speed sensor and a water level sensor, amplifies and converts the level control signal to form a level control signal, and inputs the level control signal into a motor driving circuit to control the duty ratio of an output clock signal so as to control the rotating speed of a motor, so that the target analog quantity meets the requirement. For a stepping motor, a driving circuit of the stepping motor mostly adopts monostable output. The step motor is an actuating mechanism for converting electric pulse into angular displacement, when a step driver receives a pulse signal, it drives the step motor to rotate a fixed angle, namely a step angle, according to the set direction, so that the angular displacement of the motor can be controlled by controlling the number of pulses, thereby achieving the purpose of accurate positioning, and simultaneously, the rotating speed and acceleration of the motor can be controlled by controlling the pulse frequency, thereby achieving the purpose of speed regulation. The stepping motor is different from a direct current motor and is an open-loop control mode.
The existing motor driving scheme generally has single function, complex circuit, high cost and large power consumption, and can not cover the requirements of various application systems in a large range due to single type of a supporting motor, thereby increasing the complexity of system design. This is too costly for the current trend of miniaturization and cost reduction of the equipment. Therefore, it is urgently needed to find a low-cost driving circuit to reduce the number of system hardware, realize various functions and performances through simple setting, adapt to and simplify the design of an application circuit, and support enough motor types so as to reduce the cost of the system, miniaturize the system and simplify the application design.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a motor driving circuit and a driving method based on a capacitor charging and discharging structure, which have the advantages of simple circuit structure, simple and convenient frequency setting, avoidance of repeated setting, wide frequency change range and wider application range.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a motor driving circuit based on a capacitor charging and discharging structure comprises: the circuit comprises a 50% duty ratio clock generator, a duty ratio adjustable clock generator, a monostable trigger and an output selector;
the 50% duty cycle clock generator is used for charging and discharging an external capacitor according to different capacitance values of the external capacitor to generate a clock signal CLK with a 50% duty cycle and a triangular wave voltage Vtr, inputting the clock signal with the 50% duty cycle into the output selector and the monostable trigger, and inputting the triangular wave voltage Vtr into the duty cycle adjustable clock generator;
the duty-ratio-adjustable clock generator is used for converting an external control voltage into a duty-ratio reference voltage Vduty within a voltage range determined by a maximum duty ratio and a minimum duty ratio according to a voltage value of the external control voltage Vctl, comparing the triangular wave voltage Vtr with the duty-ratio reference voltage Vduty, outputting a duty-ratio-adjustable clock signal PWM according to a comparison result, and inputting the duty-ratio-adjustable clock signal PWM into the output selector;
the monostable flip-flop is used for generating a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to a level signal input by external control and the clock signal CLK with the 50% duty ratio, and inputting the monostable trigger signal Pulse into the output selector;
and the output selector is used for selecting the output combination of the first pulse output end and the second pulse output end according to the level of the mode selection input.
Further, the motor driving circuit based on the capacitor charging and discharging structure as described above, the 50% duty cycle clock generator, includes: the circuit comprises a charge-discharge capacitor, a current source Iup, a current source Idn, a series switch SWP, a series switch SWN, a first comparator, a second comparator and an RS trigger;
the charge and discharge nodes of the charge and discharge capacitor are connected with the current source Iup, the current source Idn and the duty ratio adjustable clock generator and are used for generating a triangular wave voltage Vtr;
the current source Iup is connected with vdd through the series switch SWP and is used for charging the charge-discharge capacitor;
the current source Idn is connected with gnd through the series switch SWN and is used for discharging the charge and discharge capacitor;
the positive input end of the first comparator is connected with the charge and discharge node of the charge and discharge capacitor, and the negative input end of the first comparator is connected with a reference input voltage VH for judging the polarity of the voltage difference between the triangular wave voltage Vtri and the reference input reference VH;
the negative input end of the second comparator is connected with the charge-discharge node of the charge-discharge capacitor, and the positive input end of the second comparator is connected with a reference input voltage VL for judging the polarity of the voltage difference between the triangular wave voltage Vtri and the reference input voltage VL;
the RS trigger is composed of two NOR gates, wherein the R end of the first NOR gate is connected with the output end of the first comparator, the output end of the first NOR gate is connected with the CLK output end of the 50% duty cycle clock generator, the control end of the series switch SWP and the other input end of the second NOR gate, the S end of the second NOR gate is connected with the output end of the second comparator, the CLK _ B output end of the second NOR gate is connected with the control end of the series switch SWN and the other input end of the first NOR gate, and the RS trigger is used for converting output logics of the first comparator and the second comparator into a clock signal CLK with 50% duty cycle and inputting the clock signal CLK into the monostable trigger.
Further, the motor driving circuit based on the capacitor charging and discharging structure as described above, the 50% duty cycle clock generator is configured to:
when the triangular wave voltage Vtri is 0 and lower than the reference input voltage VL, the output of the second comparator is at a high level, the output of the first comparator is at a low level, and the output of the RS flip-flop is at a high level, so that the series switch SWN is turned off and the series switch SWP is turned on, and the charge-discharge capacitor is charged through the current source Iup;
maintaining the triangular wave voltage Vtr to rise, when the triangular wave voltage Vtr is higher than the reference input voltage VL and lower than the reference input voltage VH, the outputs of the first comparator and the second comparator are both 0, and the RS trigger maintains the output unchanged;
when the triangular wave voltage Vtri is higher than the reference input voltage VH, the first comparator outputs 1, the second comparator outputs 0, and the RS flip-flop outputs a low level, so that the series switch SWP is turned off and the series switch SWN is turned on, and the charge and discharge capacitor is discharged through the current source Idn;
maintaining the triangular wave voltage Vtr to be decreased, when the triangular wave voltage Vtr is higher than the reference input voltage VL and lower than the reference input voltage VH, the outputs of the first comparator and the second comparator are both 0, and the RS trigger maintains the output unchanged;
repeating the above process to realize periodic work and output clock signal CLK with 50% duty ratio and square wave frequency Tclk50Comprises the following steps:
Figure BDA0002539355630000041
if the current source Idn and the current source Iup are both copied to the same reference current source Isrc, the square wave frequency Tclk of the clock signal CLK with 50% duty ratio50Comprises the following steps:
Figure BDA0002539355630000042
wherein, C0And the capacitance value of the charge and discharge capacitor is shown, VH is the voltage value of the reference input voltage VH, VL is the voltage value of the reference input voltage VL, Iup is the current value of the current source Iup, Idn is the current value of the current source Idn, and Isrc is the current value of the reference current source Isrc.
Further, as above, the motor driving circuit based on the capacitor charging and discharging structure, the clock generator with adjustable duty ratio includes: the first negative feedback amplifier, the second negative feedback amplifier, the first resistor, the NFET, the second resistor and the third comparator;
the positive input end of the first negative feedback amplifier is connected with a reference voltage Vdut _ min, the negative input end of the first negative feedback amplifier is connected with the output end of the first negative feedback amplifier, and the output end of the first negative feedback amplifier is connected with one end of the first resistor;
the positive input end of the second negative feedback amplifier is connected with the control end of an external control voltage Vctl, the negative input end of the second negative feedback amplifier is connected with the source electrode of the NFET, and the output end of the second negative feedback amplifier is connected with the grid electrode of the NFET;
the source of the NFET is connected with one end of the second resistor, the other end of the second resistor is grounded, the drain of the NFET is connected with the other end of the first resistor, and the drain of the NFET inputs a duty ratio reference voltage Vduty converted from an external control voltage Vctl into the negative input end of the third comparator;
and the positive input end of the third comparator is connected with the triangular wave voltage Vtri, the negative input end of the third comparator is connected with the drain electrode of the NFET, and the output end of the third comparator is connected with the PWM output end of the duty-ratio-adjustable clock generator and is used for comparing the triangular wave voltage Vtri with the duty-ratio reference voltage Vduty and outputting a duty-ratio-adjustable clock signal PWM according to the comparison result.
Further, the motor driving circuit based on the capacitor charging and discharging structure as described above, the third comparator is configured to:
when the triangular wave voltage Vtri is greater than the duty ratio reference voltage Vduty, the output is 1;
when the triangular wave voltage Vtri is smaller than the duty ratio reference voltage Vduty, the output is 0.
Further, in the above motor driving circuit based on the capacitor charging and discharging structure, the duty ratio reference voltage Vduty is:
Vduty＝(VH-(VH-VL)*min_duty)-Vctl*R1/R2；
the relationship between the Duty ratio Duty of the Duty ratio reference voltage Vduty and the external control voltage Vctl is:
Figure BDA0002539355630000051
when Vctl is 0, Duty is min _ Duty, Vduty is Vduty _ min, Vduty _ min is VH- (VH-VL) min _ Duty;
when Vctl is 1, Duty is max _ Duty, Vduty is Vduty _ max, Vduty _ max is VL + (VH-VL) × (1-max _ Duty);
the Duty ratio of the Duty ratio reference voltage Vduty is a voltage value of the Duty ratio reference voltage Vduty, the Duty ratio of the Duty ratio reference voltage Vduty is a Duty ratio of the Duty ratio reference voltage Vduty, Vctl is a voltage value of an external control voltage Vctl, R1 is a resistance value of a first resistor, R2 is a resistance value of a second resistor, VH is a voltage value of the reference input voltage VH, VL is a voltage value of the reference input voltage VL, Vduty _ min is a voltage value of the reference voltage Vduty _ min, min _ Duty is a set minimum Duty ratio, max _ Duty is a maximum Duty ratio, Vctl is in a range of 0-1V, and Vduty changes within voltage ranges of Vduty _ max and Vduty _ min.
Further, the motor driving circuit based on the capacitor charging and discharging structure as described above, wherein the monostable trigger circuit includes: the trigger circuit comprises a first D trigger, a second D trigger and an AND gate;
the D end of the first D trigger is connected with an external control input, the CK end of the first D trigger is connected with the CLK _ B output end, and the Q end of the first D trigger is connected with the D end of the second D trigger and the first input end of the AND gate;
the D end of the second D trigger is connected with the Q end of the first D trigger, the CK end is connected with the CLK output end,
Figure BDA0002539355630000052
the end of the first input end is connected with the first input end of the AND gate;
and the output end of the AND gate is connected with the Pulse output end of the monostable trigger.
Further, a motor driving circuit based on a capacitor charging and discharging structure as described above, the motor driving circuit includes two operation modes:
when the mode selection input is at a high level, selecting a mode for driving the stepping motor, wherein the first Pulse output end outputs the clock signal CLK with the duty ratio of 50%, and the second Pulse output end outputs the monostable trigger signal Pulse;
when the mode selection input is low level, selecting a mode for driving the direct current motor, wherein the first pulse output end outputs the clock signal PWM with the adjustable duty ratio, and the second pulse output end outputs the clock signal CLK with the 50% duty ratio;
further, the motor driving circuit based on the capacitor charging and discharging structure as described above, the output selector includes: the clock signal PWM with the duty ratio of 50% comprises a CLK input port used for receiving the clock signal CLK with the duty ratio of 50%, a Pulse input port used for receiving the monostable trigger signal Pulse, a PWM input port used for receiving the clock signal PWM with the adjustable duty ratio and a mode selection input port used for receiving off-chip input.
A motor driving method based on a capacitor charging and discharging structure is applied to a motor driving circuit based on a capacitor charging and discharging structure, and comprises the following steps:
(1) the 50% duty cycle clock generator charges and discharges an external capacitor according to different capacitance values of the external capacitor, generates a clock signal CLK and a triangular wave voltage Vtr with 50% duty cycle, inputs the clock signal with 50% duty cycle into an output selector and a monostable trigger, and inputs the triangular wave voltage Vtr into the duty cycle adjustable clock generator;
(2) the clock generator with the adjustable duty ratio converts the external control voltage into a duty ratio reference voltage Vduty within a voltage range determined by the maximum duty ratio and the minimum duty ratio according to the voltage value of the external control voltage Vctl, compares the triangular wave voltage Vtr with the duty ratio reference voltage Vduty, outputs a clock signal PWM with the adjustable duty ratio according to a comparison result, and inputs the clock signal PWM with the adjustable duty ratio into the output selector;
(3) the monostable trigger generates a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to a level signal input by external control and the clock signal CLK with the 50% duty ratio, and inputs the monostable trigger signal Pulse into the output selector;
(4) the output selector selects the output combination of the first pulse output end and the second pulse output end according to the level of the mode selection input.
The invention has the beneficial effects that: the invention adopts a method of generating triangular waves by charging and discharging off-chip capacitors to simultaneously generate square waves with 50% duty ratio, square waves with adjustable duty ratio and monostable trigger pulses. The frequency of the continuous clock and the width of the monostable pulse can be set simultaneously by modifying the value of the off-chip capacitance. Accurate output of 50% duty cycle and frequency is achieved through programmable charge-discharge current adjustment and calibration. The circuit structure is simple, the frequency setting is simple and convenient, and the respective repeated setting is avoided. The frequency variation range is wide, and the application range is wider.
Drawings
Fig. 1 is a schematic structural diagram of a motor driving circuit based on a capacitor charging and discharging structure according to an embodiment of the present invention;
fig. 2 is a detailed structural schematic diagram of a motor driving circuit based on a capacitor charging and discharging structure according to an embodiment of the present invention;
fig. 3 is a waveform diagram of a motor driving circuit based on a capacitor charging and discharging structure in the working process according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
As shown in fig. 1 to 3, a motor driving circuit based on a capacitor charging and discharging structure includes: the circuit comprises a 50% duty ratio clock generator, a duty ratio adjustable clock generator, a monostable trigger and an output selector;
(1) 50% duty cycle clock generator
And the 50% duty cycle clock generator is used for charging and discharging the external capacitor according to different capacitance values of the external capacitor, generating a clock signal CLK with a 50% duty cycle and a triangular wave voltage Vtr, inputting the clock signal with the 50% duty cycle into the output selector and the monostable trigger, and inputting the triangular wave voltage Vtr into the duty cycle adjustable clock generator.
A 50% duty cycle clock generator comprising: charging and discharging capacitor C0Current source Iup, current source Idn, series switch SWP, series switch SWN, first comparator Comp1, second comparator Comp2, andand an RS trigger.
Charging and discharging capacitor C0The charging and discharging node is connected with a current source Iup, a current source Idn and a duty ratio adjustable clock generator; a current source Iup connected to vdd via a series switch SWP for charging and discharging the capacitor C0Charging is carried out; a current source Idn connected with gnd via a series switch SWN for charging and discharging the capacitor C0And discharging is performed.
A first comparator having its positive input connected to the charge-discharge capacitor C0The negative input end of the charge and discharge node is connected with a reference input voltage VH and used for judging the polarity of the voltage difference between the triangular wave voltage Vtri generated by the charge and discharge node and the reference input voltage VH.
A second comparator having its negative input terminal connected to the charge-discharge capacitor C0The positive input end of the charge-discharge node is connected with a reference input voltage VL and used for judging the polarity of the voltage difference between the triangular wave voltage Vtri generated by the charge-discharge node and the reference input voltage VL.
The RS trigger is composed of two NOR gates, the R end of the first NOR gate is connected with the output end of the first comparator, the output end of the first NOR gate is connected with the CLK output end of the 50% duty cycle clock generator, the control end of the series switch SWP and the other input end of the second NOR gate, the S end of the second NOR gate is connected with the output end of the second comparator, the CLK _ B output end of the second NOR gate is connected with the control end of the series switch SWN and the other input end of the first NOR gate, and the RS trigger is used for converting the output logics of the first comparator and the second comparator into a 50% duty cycle clock signal CLK and inputting the clock signal CLK into the monostable trigger.
Specifically, when voltage Vtri is 0, lower than VL, the output of Comp2 is high and the output of Comp1 is low. RS trigger output is high, SWN is off and SWP is on, current source Iup is to charge and discharge capacitor C0Charging is carried out; vtri rises, and when Vtri is higher than VL and lower than VH, the outputs of Comp2 and Comp1 are both 0, and the RS flip-flop maintains the output unchanged. When Vtri is higher than VH, Comp1 outputs 1, Comp2 outputs 0, RS flip-flop outputs low, SWP is off and SWN is on, current source Idn charges and discharges capacitor C0Discharging; vtr decreases, Vtr above VL belowIn VH, the outputs of Comp2 and Comp1 are both 0, and the RS flip-flop keeps the output unchanged. So repeatedly, the clock signal CLK works periodically and outputs 50% duty ratio, and the square wave frequency is:
Figure BDA0002539355630000081
both current source Idn and current source Iup are duplicated in the same reference current source Isrc, which can be a programmable current source, and Idn is also a programmable current source. The duty cycle can be fine tuned by adjusting Idn. When the trimming current value is equal to Iup, a clock signal CLK with 50% duty ratio can be obtained. When trimming Isrc, Iup and Idn are simultaneously increased or decreased to trim the square wave frequency of the clock signal CLK. The method is used for correcting the process deviation in the chip manufacturing, can control the deviation to be +/-1 percent and realizes high precision. The square wave frequency of the clock signal CLK is:
Figure BDA0002539355630000091
charging and discharging capacitor C0Is an off-chip capacitor, charging and discharging a capacitor C0The capacitance value of the frequency converter is changed according to the change of the required frequency of the system, the higher the frequency is, the smaller the capacitance value is, the lower the frequency is, the larger the capacitance value is, and the flexibility of the system design is increased.
(2) Duty ratio adjustable clock generator
And the duty ratio adjustable clock generator is used for converting the external control voltage into a duty ratio reference voltage Vduty within a voltage range determined by the maximum duty ratio max _ duty and the minimum duty ratio min _ duty according to the voltage value of the external control voltage Vctl, comparing the triangular wave voltage Vtri with the duty ratio reference voltage Vduty, outputting a duty ratio adjustable clock signal PWM according to a comparison result, and inputting the duty ratio adjustable clock signal PWM into the output selector.
The adjustable clock generator of duty cycle can become duty cycle clock generator circuit, includes: a first negative feedback amplifier amp1, a second negative feedback amplifier amp2, a first resistor R1, an NFET, a second resistor R2, and a third comparator comp _ PWM;
the positive input end of the first negative feedback amplifier is connected with the reference voltage Vdut _ min, the negative input end is connected with the output end, and the output end is connected with one end of the first resistor R1.
The positive input end of the second negative feedback amplifier is connected with the control end of an external control voltage Vctl, the negative input end of the second negative feedback amplifier is connected with the source electrode of the NFET, and the output end of the second negative feedback amplifier is connected with the grid electrode of the NFET.
The source of the NFET is connected with one end of a second resistor R2, the other end of the second resistor R2 is grounded, the drain of the NFET is connected with the other end of a first resistor R1, and the drain of the NFET inputs a duty ratio reference voltage Vduty converted from an external control voltage Vctl into the negative input end of a third comparator.
This circuit determines the maximum duty cycle max _ duty that can be allowed and converts the external voltage control signal Vctl to a reference voltage signal Vduty that is internally within the range of Vduty _ max and Vduty _ min.
And the positive input end of the third comparator is connected with the triangular wave voltage Vtri, the negative input end of the third comparator is connected with the drain electrode of the NFET, and the output end of the third comparator is connected with the PWM output end of the duty-ratio-adjustable clock generator and is used for comparing the triangular wave voltage Vtri with the duty-ratio reference voltage Vduty and outputting a duty-ratio-adjustable clock signal PWM according to the comparison result.
Specifically, the Vctl voltage is passed through the negative feedback amplifier amp2 and the NFET to make the voltage across resistor R2 equal to Vctrl. The current I at the resistor R2R2Vctl/R1. R1 is in series with R2 so that the current of R1 is equal to the current of R2. Pressure drop V across R1R1Vctl R2/R1. The upper end of R1 is connected to negative feedback amplifier amp 1. Amp1 operates essentially as a power supply with a voltage equal to Vdut _ min, which provides a current IR2. Therefore, the voltage Vduty at the lower end of the resistor R1 is Vduty _ min-Vctl R1/R2. The comparator comp _ PWM detects a voltage difference between the triangular waves Vtri and Vctl-converted voltage Vduty, thereby outputting square wave signals of different duty ratios. When the triangular wave voltage Vtri is greater than Vduty, the comparator comp _ PWM output is 1. When the triangular wave Vtri is smaller than Vduty, the comparator comp _ PWM output is 0. According to the operation principle of the triangular wave voltage Vtri, the time of outputting 1 by computer _ PWM, i.e. Vtri is larger than VdutyTime Thigh＝C0(VH-Vduty)/Isrc. The square wave period being Tclk＝C0*(VH-VL)/Isrc。Duty＝Thigh/Tclk(VH-Vduty)/(VH-VL). When Vctl is equal to 1, we can obtain the desired duty cycle max _ duty, where Vduty _ max is VL + (VH-VL) × (1-max _ duty). When Vctl varies in the range of 0V to 1V, the relationship between the Duty ratio Duty of the output Duty ratio reference voltage Vduty and Vctl does not vary with the square wave frequency, and the following relationship is satisfied:
Figure BDA0002539355630000101
wherein, R1/R2 is (max _ duty-min _ duty) (VH-VL), Vctl is in the range of 0-1V, Vctl is 0V for min _ duty, and Vctl is 1V for max _ duty.
Converting Vctl to Vduty, (VH-VL) min _ duty) -Vctl R1/R2.
When Vctl is 0, min _ duty is assigned, and Vduty _ min is VH- (VH-VL) min _ duty.
Max _ duty corresponds to Vctl being 1, and Vduty _ max is VL + (VH-VL) (1-max _ duty).
Vduty varies within Vduty _ max and Vduty _ min.
The programmable reference voltage Vdut _ min. The external control voltage Vctl (0-1V) is set to its minimum value of 0V. The sum of Vdut _ min plus offset voltage offset1 of amplifier amp1 is equal to VH-min _ duty (VH-VL) by trimming the voltage of Vdut _ min. Thus, the min _ duty can be accurately adjusted to meet the requirement of accuracy, such as a tolerance of ± 1%. Offset voltage offset2 of programmable amplifier amp 2. Setting the external control voltage Vctl to its maximum value of 1V, the voltage of Vduty is made equal to VL + (1-max _ duty) (VH-VL) by trimming the voltage of offset 2. In this way, the max _ duty can be adjusted accurately to meet the requirement, such as ± 1% error. The duty cycle of the Vctl control square wave can be guaranteed to vary within the range of max _ duty and min _ duty by fine tuning.
(3) Monostable trigger
The monostable trigger is used for generating a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to a level signal input by external control and the clock signal CLK with the 50% duty ratio, and inputting and outputting the monostable trigger signal Pulse into and out of the selector;
a monostable flip-flop circuit comprising: a first D flip-flop D1, a second D flip-flop D2, And an AND gate And;
the D end of the first D trigger is connected with an external control input, the CK end is connected with the CLK _ B output end, and the Q end is connected with the D end of the second D trigger and the first input end of the AND gate.
The D end of the second D trigger is connected with the Q end of the first D trigger, the CK end is connected with the CLK output end,
Figure BDA0002539355630000111
the end is connected with the second input end of the AND gate.
And the output end of the AND gate is connected with the Pulse output end of the monostable trigger.
Specifically, when the voltage at the external control input terminal is low, the D terminal of D1 is 0, the Q terminal of D1 is 0, and the D2 is
Figure BDA0002539355630000115
The end is 1. The D terminal of D1 goes high when the voltage at the external control input terminal is high, the Q terminal of D1 goes from low to high when the rising edge of CLK _ B, i.e., the falling edge of CLK, comes, and D2 when the rising edge of the next pulse of CLK comes after half a cycle
Figure BDA0002539355630000112
The terminal changes from high to low. Q terminal of D1 and D2
Figure BDA0002539355630000113
The terminal has half a period and is high at the same time. Coupling the Q terminal of D1 with that of D2
Figure BDA0002539355630000114
The output of AND gate And is a monostable pulse with a pulse width of half the period of CLK. In short, the monostable pulse is the first under CLK from each time the external control input goes from low to highThe falling edge begins one pulse until the rising edge of the next cycle of CLK.
(4) Output selector
And the output selector is used for selecting the output combination of the first Pulse output end and the second Pulse output end according to the level of the mode selection input, if the mode selection input is high level, the first Pulse output end is a clock signal CLK with 50% duty ratio, the second Pulse output end is a monostable trigger signal Pulse, if the mode selection input is low level, the first Pulse output end is a clock signal PWM with adjustable duty ratio, and the second Pulse output end is a clock signal CLK with 50% duty ratio. And meanwhile, the driving capability of the two pulse output ends is enhanced.
An output selector comprising: a CLK input port for receiving a 50% duty cycle clock signal CLK, a Pulse input port for receiving a monostable trigger signal Pulse, a PWM input port for receiving a duty-adjustable clock signal PWM, and a mode select input port for receiving an off-chip input.
The motor driving circuit based on the capacitor charging and discharging structure can comprise two working modes. When the mode selection input is high level, the mode for driving the stepping motor is selected, and the combination of the output ends selects that the Pulse output 1 (the first Pulse output end) is continuous 50% duty cycle clock CLK and the Pulse output 2 (the second Pulse output end) is monostable Pulse. The width of the monostable pulse is the same as the width of the low level of the 50% duty cycle clock. At this time, the duty-cycle tunable clock generator is turned off for low power consumption. In the 50% duty cycle clock generator, the current realizes that the voltage at the capacitor end linearly increases or linearly decreases along with time through charging and discharging of an external capacitor. The two reference voltages VH and VL are set, and the charging current and the discharging current are controlled to periodically charge and discharge the capacitor, so that the generation of periodic square waves is realized, and when the charging current is equal to the discharging current, the square waves with 50% duty ratio can be obtained. According to the square wave with the 50% duty ratio, when the potential of the external control input end is changed from low to high, the monostable trigger starts to work, when the monostable trigger detects the falling edge of the square wave with the 50% duty ratio, the monostable trigger can latch a half period of high level till the rising edge of the next period of the square wave with the 50% duty ratio, and the monostable trigger is used as a monostable signal to be output to the pulse output 2. When the pulse output 2 output is finished to become 0, the monostable flip-flop is set to zero and waits for the next change of the external control input end from low level to high level, so that the external control input end works again. When the mode selection input is low level, the mode for driving the direct current motor is selected, the pulse output 1 is the duty ratio adjustable clock PWM, and the pulse output 2 is the continuous 50% duty ratio clock CLK. The driving capability of the pulse output 1 and the pulse output 2 is enhanced at the same time. The 50% duty cycle clock signal operates as above, and the capacitor terminal generates a triangular wave Vtri due to the periodic charging and discharging of the capacitor by the current source. The maximum duty cycle and the minimum duty cycle of the variable duty cycle square wave clock signal both have their corresponding voltage values Vmax _ duty and Vmin _ duty on the triangular wave. The voltage Vctl of the external voltage control terminal is converted into the continuously variable voltage Vduty within the range of Vmax _ duty and Vmin _ duty by the resistance proportional amplifying circuit. The comparator outputs square wave signals with different duty ratios by comparing the difference value of Vduty and the triangular wave Vtri.
The waveform of the capacitor charging and discharging motor driving operation process in the embodiment of the invention is described in detail below. Fig. 3 is a schematic diagram of a working timing sequence of a motor driving circuit based on a capacitor charging and discharging structure according to an embodiment of the present invention.
(1) A 50% duty cycle square wave CLK.
Start of off-chip capacitance C0Terminal voltage Vtr is less than VL, comparator Comp2 outputs high, and RS flip-flop output CLK is set to 1. The pull-up current starts to work, Vtr starts to rise linearly, and when VL is exceeded but VH is less than VH, the RS flip-flop keeps the output unchanged. When Vtr reaches VH, comparator Comp1 outputs high and RS flip-flop output CLK is reset to 0. The pull-down current starts to operate, and when VL is exceeded but VH is less, the RS flip-flop keeps the output unchanged. The RS flip-flop changes periodically and the rising and falling slopes of Vtri are consistent, so that a square wave signal with 50% duty ratio is obtained. The periodic work is repeated in this way. The frequency is inversely proportional to the capacitance value of the external capacitor, and because the charging and discharging current of the capacitor is fixed, the charging and discharging time of the capacitor is inversely proportional to the capacitance。
(2) Monostable square wave Pulse. The monostable Pulse is a Pulse from the first falling edge of CLK after each low to high on the external control input to the rising edge of the next CLK cycle.
(3) And square wave PWM with adjustable duty ratio.
Vctl is gradually changed from 0 to 1, and Vduty is gradually changed from Vduty _ min to Vduty _ max according to the foregoing conversion formula, and Vduty is gradually decreased. The comparator comp _ PWM compares the magnitudes of Vti and Vduty, and when Vti is larger than Vduty, the output PWM of the comparator comp _ PWM outputs 1, otherwise the PWM outputs 0. As can be seen from the waveform diagram, as Vctl becomes higher and higher, the Vduty voltage is gradually reduced, and the time that Vtri is greater than Vduty becomes longer and longer, so that the comparator comp _ PWM outputs PWM at a high level for a longer time, and PWM outputs PWM at a low level for a shorter time, so as to realize that the duty ratio of the square wave signal PWM output by the comparator becomes larger and larger.
A motor driving method based on a capacitor charging and discharging structure is applied to a motor driving circuit based on a capacitor charging and discharging structure, and comprises the following steps:
(1) the 50% duty cycle clock generator charges and discharges an external capacitor according to different capacitance values of the external capacitor, generates a clock signal CLK and a triangular wave voltage Vtr with 50% duty cycle, inputs the clock signal with 50% duty cycle into an output selector and a monostable trigger, and inputs the triangular wave voltage Vtr into the duty cycle adjustable clock generator;
(2) the duty ratio adjustable clock generator converts the external control voltage into a duty ratio reference voltage Vduty within a voltage range determined by the maximum duty ratio and the minimum duty ratio according to the voltage value of the external control voltage Vctl, compares the triangular wave voltage Vtr and the duty ratio reference voltage Vduty, outputs a duty ratio adjustable clock signal PWM according to a comparison result, and inputs the duty ratio adjustable clock signal PWM into the output selector;
(3) the monostable trigger generates a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to the level signal input by external control and the clock signal CLK with the 50% duty ratio, and the monostable trigger signal Pulse is input into and output from the selector;
(4) the output selector selects the output combination of the first pulse output end and the second pulse output end according to the level of the mode selection input.
The motor driving circuit and the driving method based on the capacitor charging and discharging structure have the following beneficial effects:
(1) the invention adopts a method of generating triangular waves by charging and discharging off-chip capacitors to simultaneously generate a clock with 50% duty ratio, a clock with adjustable duty ratio and monostable starting pulses. The frequency of the 50% duty cycle clock, the frequency of the adjustable duty cycle clock, and the width of the monostable pulse can be set simultaneously by modifying the value of the off-chip capacitance. Accurate output of 50% duty cycle and frequency is achieved through programmable charge-discharge current adjustment and calibration. The circuit structure is simple, the frequency setting is simple and convenient, and the respective repeated setting is avoided. The frequency variation range is wide, and the application range is wider.
(2) The invention adopts a Vctl level conversion method and programmable voltage source adjustment, realizes the accurate adjustment of the clock duty ratio through a simple circuit, and simultaneously has the advantages of simple circuit and power consumption and area saving.
(3) The invention can selectively support the drive of the direct current motor and the stepping motor by selecting the combination of the two outputs, and one chip supports the two motors. This provides great flexibility in system design and reduces system components and cost.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.

Claims (9)

1. A motor drive circuit based on a capacitor charging and discharging structure is characterized by comprising: the circuit comprises a 50% duty ratio clock generator, a duty ratio adjustable clock generator, a monostable trigger and an output selector;
the 50% duty cycle clock generator is used for charging and discharging an external capacitor according to different capacitance values of the external capacitor to generate a clock signal CLK with a 50% duty cycle and a triangular wave voltage Vtr, inputting the clock signal with the 50% duty cycle into the output selector and the monostable trigger, and inputting the triangular wave voltage Vtr into the duty cycle adjustable clock generator;
the duty-ratio-adjustable clock generator is used for converting an external control voltage into a duty-ratio reference voltage Vduty within a voltage range determined by a maximum duty ratio and a minimum duty ratio according to a voltage value of the external control voltage Vctl, comparing the triangular wave voltage Vtr with the duty-ratio reference voltage Vduty, outputting a duty-ratio-adjustable clock signal PWM according to a comparison result, and inputting the duty-ratio-adjustable clock signal PWM into the output selector;
the monostable flip-flop is used for generating a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to a level signal input by external control and the clock signal CLK with the 50% duty ratio, and inputting the monostable trigger signal Pulse into the output selector;
the output selector is used for selecting the output combination of the first pulse output end and the second pulse output end according to the level of the mode selection input;
when the mode selection input is at a high level, selecting a mode for driving the stepping motor, wherein the first Pulse output end outputs the clock signal CLK with the duty ratio of 50%, and the second Pulse output end outputs the monostable trigger signal Pulse;
and when the mode selection input is low level, selecting a mode for driving the direct current motor, wherein the first pulse output end outputs the clock signal PWM with the adjustable duty ratio, and the second pulse output end outputs the clock signal CLK with the 50% duty ratio.
2. A capacitor charging and discharging structure based motor driving circuit as claimed in claim 1, wherein the 50% duty cycle clock generator comprises: the circuit comprises a charge-discharge capacitor, a current source Iup, a current source Idn, a series switch SWP, a series switch SWN, a first comparator, a second comparator and an RS trigger;
the charge and discharge nodes of the charge and discharge capacitor are connected with the current source Iup, the current source Idn and the duty ratio adjustable clock generator and are used for generating a triangular wave voltage Vtr;
the current source Iup is connected with vdd through the series switch SWP and is used for charging the charge-discharge capacitor;
the current source Idn is connected with gnd through the series switch SWN and is used for discharging the charge and discharge capacitor;
the positive input end of the first comparator is connected with the charge and discharge node of the charge and discharge capacitor, and the negative input end of the first comparator is connected with a reference input voltage VH for judging the polarity of the voltage difference between the triangular wave voltage Vtri and the reference input reference VH;
the negative input end of the second comparator is connected with the charge-discharge node of the charge-discharge capacitor, and the positive input end of the second comparator is connected with a reference input voltage VL for judging the polarity of the voltage difference between the triangular wave voltage Vtri and the reference input voltage VL;
the RS trigger is composed of two NOR gates, wherein the R end of the first NOR gate is connected with the output end of the first comparator, the output end of the first NOR gate is connected with the CLK output end of the 50% duty cycle clock generator, the control end of the series switch SWP and the other input end of the second NOR gate, the S end of the second NOR gate is connected with the output end of the second comparator, the CLK _ B output end of the second NOR gate is connected with the control end of the series switch SWN and the other input end of the first NOR gate, and the RS trigger is used for converting output logics of the first comparator and the second comparator into a clock signal CLK with 50% duty cycle and inputting the clock signal CLK into the monostable trigger.
3. A capacitor charging and discharging structure based motor driving circuit as claimed in claim 2, wherein the 50% duty cycle clock generator is configured to:
when the triangular wave voltage Vtri is 0 and lower than the reference input voltage VL, the output of the second comparator is at a high level, the output of the first comparator is at a low level, and the output of the RS flip-flop is at a high level, so that the series switch SWN is turned off and the series switch SWP is turned on, and the charge-discharge capacitor is charged through the current source Iup;
maintaining the triangular wave voltage Vtr to rise, when the triangular wave voltage Vtr is higher than the reference input voltage VL and lower than the reference input voltage VH, the outputs of the first comparator and the second comparator are both 0, and the RS trigger maintains the output unchanged;
when the triangular wave voltage Vtri is higher than the reference input voltage VH, the first comparator outputs 1, the second comparator outputs 0, and the RS flip-flop outputs a low level, so that the series switch SWP is turned off and the series switch SWN is turned on, and the charge and discharge capacitor is discharged through the current source Idn;
maintaining the triangular wave voltage Vtr to be decreased, when the triangular wave voltage Vtr is higher than the reference input voltage VL and lower than the reference input voltage VH, the outputs of the first comparator and the second comparator are both 0, and the RS trigger maintains the output unchanged;
repeating the above process to realize periodic work and output clock signal CLK with 50% duty ratio and square wave frequency Tclk50Comprises the following steps:
Figure FDA0003244745390000031
if the current source Idn and the current source Iup are both copied to the same reference current source Isrc, the square wave frequency Tclk of the clock signal CLK with 50% duty ratio50Comprises the following steps:
Figure FDA0003244745390000032
wherein, C0And the capacitance value of the charge and discharge capacitor is shown, VH is the voltage value of the reference input voltage VH, VL is the voltage value of the reference input voltage VL, Iup is the current value of the current source Iup, Idn is the current value of the current source Idn, and Isrc is the current value of the reference current source Isrc.
4. The motor driving circuit based on the capacitor charging and discharging structure as claimed in claim 1, wherein the clock generator with adjustable duty ratio comprises: the first negative feedback amplifier, the second negative feedback amplifier, the first resistor, the NFET, the second resistor and the third comparator;
the positive input end of the first negative feedback amplifier is connected with a reference voltage Vdut _ min, the negative input end of the first negative feedback amplifier is connected with the output end of the first negative feedback amplifier, and the output end of the first negative feedback amplifier is connected with one end of the first resistor;
the positive input end of the second negative feedback amplifier is connected with the control end of an external control voltage Vctl, the negative input end of the second negative feedback amplifier is connected with the source electrode of the NFET, and the output end of the second negative feedback amplifier is connected with the grid electrode of the NFET;
the source of the NFET is connected with one end of the second resistor, the other end of the second resistor is grounded, the drain of the NFET is connected with the other end of the first resistor, and the drain of the NFET inputs a duty ratio reference voltage Vduty converted from an external control voltage Vctl into the negative input end of the third comparator;
and the positive input end of the third comparator is connected with the triangular wave voltage Vtri, the negative input end of the third comparator is connected with the drain electrode of the NFET, and the output end of the third comparator is connected with the PWM output end of the duty-ratio-adjustable clock generator and is used for comparing the triangular wave voltage Vtri with the duty-ratio reference voltage Vduty and outputting a duty-ratio-adjustable clock signal PWM according to the comparison result.
5. The motor driving circuit based on the capacitor charging and discharging structure as claimed in claim 4, wherein the third comparator is configured to:
when the triangular wave voltage Vtri is greater than the duty ratio reference voltage Vduty, the output is 1;
when the triangular wave voltage Vtri is smaller than the duty ratio reference voltage Vduty, the output is 0.
6. The capacitor charging and discharging structure-based motor driving circuit according to claim 5, wherein the duty ratio reference voltage Vduty is:
Vduty＝(VH-(VH-VL)*min_duty)-Vctl*R1/R2；
the relationship between the Duty ratio Duty of the Duty ratio reference voltage Vduty and the external control voltage Vctl is:
Figure FDA0003244745390000041
when Vctl is 0, Duty is min _ Duty, Vduty is Vduty _ min, Vduty _ min is VH- (VH-VL) min _ Duty;
when Vctl is 1, Duty is max _ Duty, Vduty is Vduty _ max, Vduty _ max is VL + (VH-VL) × (1-max _ Duty);
the Duty ratio of the Duty ratio reference voltage Vduty is a voltage value of the Duty ratio reference voltage Vduty, the Duty ratio of the Duty ratio reference voltage Vduty is a Duty ratio of the Duty ratio reference voltage Vduty, Vctl is a voltage value of an external control voltage Vctl, R1 is a resistance value of a first resistor, R2 is a resistance value of a second resistor, VH is a voltage value of the reference input voltage VH, VL is a voltage value of the reference input voltage VL, Vduty _ min is a voltage value of the reference voltage Vduty _ min, min _ Duty is a set minimum Duty ratio, max _ Duty is a maximum Duty ratio, Vctl is in a range of 0-1V, and Vduty changes within voltage ranges of Vduty _ max and Vduty _ min.
7. The motor driving circuit based on the capacitor charging and discharging structure as claimed in claim 2, wherein the monostable trigger comprises: the trigger circuit comprises a first D trigger, a second D trigger and an AND gate;
the D end of the first D trigger is connected with an external control input, the CK end of the first D trigger is connected with the CLK _ B output end, and the Q end of the first D trigger is connected with the D end of the second D trigger and the first input end of the AND gate;
the D end of the second D trigger is connected with the first D triggerA Q end of the oscillator, CK end is connected with the CLK output end,
Figure FDA0003244745390000051
the end of the first input end is connected with the first input end of the AND gate;
and the output end of the AND gate is connected with the Pulse output end of the monostable trigger.
8. The motor driving circuit based on the capacitor charging and discharging structure as claimed in claim 1, wherein the output selector comprises: the clock signal PWM with the duty ratio of 50% comprises a CLK input port used for receiving the clock signal CLK with the duty ratio of 50%, a Pulse input port used for receiving the monostable trigger signal Pulse, a PWM input port used for receiving the clock signal PWM with the adjustable duty ratio and a mode selection input port used for receiving off-chip input.
9. A motor driving method based on a capacitor charging and discharging structure, which is applied to the motor driving circuit based on the capacitor charging and discharging structure as claimed in any one of claims 1 to 8, and is characterized by comprising the following steps:
(1) the 50% duty cycle clock generator charges and discharges an external capacitor according to different capacitance values of the external capacitor, generates a clock signal CLK and a triangular wave voltage Vtr with 50% duty cycle, inputs the clock signal with 50% duty cycle into an output selector and a monostable trigger, and inputs the triangular wave voltage Vtr into the duty cycle adjustable clock generator;
(2) the clock generator with the adjustable duty ratio converts the external control voltage into a duty ratio reference voltage Vduty within a voltage range determined by the maximum duty ratio and the minimum duty ratio according to the voltage value of the external control voltage Vctl, compares the triangular wave voltage Vtr with the duty ratio reference voltage Vduty, outputs a clock signal PWM with the adjustable duty ratio according to a comparison result, and inputs the clock signal PWM with the adjustable duty ratio into the output selector;
(3) the monostable trigger generates a monostable trigger signal Pulse with the width same as the low level width of the clock signal CLK with the 50% duty ratio according to a level signal input by external control and the clock signal CLK with the 50% duty ratio, and inputs the monostable trigger signal Pulse into the output selector;
(4) the output selector selects the output combination of the first pulse output end and the second pulse output end according to the level of the mode selection input.
CN202010542159.1A 2020-06-15 2020-06-15 Motor driving circuit and driving method based on capacitor charging and discharging structure Active CN111884548B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010542159.1A CN111884548B (en) 2020-06-15 2020-06-15 Motor driving circuit and driving method based on capacitor charging and discharging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010542159.1A CN111884548B (en) 2020-06-15 2020-06-15 Motor driving circuit and driving method based on capacitor charging and discharging structure

Publications (2)

Publication Number Publication Date
CN111884548A CN111884548A (en) 2020-11-03
CN111884548B true CN111884548B (en) 2021-12-03

Family

ID=73157542

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010542159.1A Active CN111884548B (en) 2020-06-15 2020-06-15 Motor driving circuit and driving method based on capacitor charging and discharging structure

Country Status (1)

Country Link
CN (1) CN111884548B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3335322A1 (en) * 1983-09-27 1985-04-04 Schleicher Gmbh & Co Relais-Werke Kg, 1000 Berlin Electronic pulse clock generator with adjustable time delay circuit for timing relays, particularly for a time delay circuit with remote adjustment
EP1638203A1 (en) * 2004-09-21 2006-03-22 Dialog Semiconductor GmbH Oscillator with controlled duty cycle
CN101212214A (en) * 2006-12-28 2008-07-02 松下电器产业株式会社 Triangle wave generating circuit and PWM modulation circuit
JP2009240089A (en) * 2008-03-27 2009-10-15 Sanyo Electric Co Ltd Motor drive circuit
CN101895246A (en) * 2010-06-08 2010-11-24 上海新进半导体制造有限公司 Control pulse generating circuit and regulating system and method of direct current brushless motor speed
CN111030645A (en) * 2019-11-29 2020-04-17 芯创智（北京）微电子有限公司 Digital control wide-range clock duty ratio adjusting system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7746130B2 (en) * 2008-07-14 2010-06-29 Elite Semiconductor Memory Technology, Inc. Triangular wave generating circuit having synchronization with external clock

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3335322A1 (en) * 1983-09-27 1985-04-04 Schleicher Gmbh & Co Relais-Werke Kg, 1000 Berlin Electronic pulse clock generator with adjustable time delay circuit for timing relays, particularly for a time delay circuit with remote adjustment
EP1638203A1 (en) * 2004-09-21 2006-03-22 Dialog Semiconductor GmbH Oscillator with controlled duty cycle
CN101212214A (en) * 2006-12-28 2008-07-02 松下电器产业株式会社 Triangle wave generating circuit and PWM modulation circuit
JP2009240089A (en) * 2008-03-27 2009-10-15 Sanyo Electric Co Ltd Motor drive circuit
CN101895246A (en) * 2010-06-08 2010-11-24 上海新进半导体制造有限公司 Control pulse generating circuit and regulating system and method of direct current brushless motor speed
CN111030645A (en) * 2019-11-29 2020-04-17 芯创智（北京）微电子有限公司 Digital control wide-range clock duty ratio adjusting system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
直流电机变速的PWM波的几种产生方法;肖振兴;《现代信息科技》;20200610(第11期);全文 *

Also Published As

Publication number Publication date
CN111884548A (en) 2020-11-03

Similar Documents

Publication Publication Date Title
US9312844B2 (en) Slope compensation module
KR100968557B1 (en) Voltage rising/falling type switching regulator and operation control method thereof
EP1909379B1 (en) Method and apparatus for pulse width modulation
US8310221B2 (en) Electronic device and method for DC-DC conversion with slope compensation
US9190909B2 (en) Control device for multiphase interleaved DC-DC converter and control method thereof
CN105099186B (en) Minimum on-time control for low load DC/DC converter
TWI470932B (en) Differential amplitude controlled sawtooth generator and method of generating dual differential sawtooth signals
US7579820B2 (en) PWM/PFM control circuit and switching power supply circuit
JP4631916B2 (en) Boost DC-DC converter
WO2019036179A1 (en) Hybrid pulse-width control circuit with process and offset calibration
JP2006006004A (en) Buck-boost dc-dc converter
US10432092B2 (en) Self-calibrated DC-DC converter
US20130335045A1 (en) Power converter with the function of digital error correction
US20170288550A1 (en) Ultrasonic control system and method for a buck-boost power converter
KR100994612B1 (en) Method and system for synchronizing phase of triangular signal
TW201143265A (en) A heterodyne dual slope frequency generation method for the load change of power supply
CN111884548B (en) Motor driving circuit and driving method based on capacitor charging and discharging structure
CN110364134B (en) Buzzer driving circuit
CN210405226U (en) RC oscillating circuit
US7535269B2 (en) Multiplier circuit
US7123179B1 (en) Apparatus and method for duty cycle conversion
CN110798151A (en) Wide-range monotonous linear adjustable frequency clock circuit
CN216216812U (en) Duty ratio regulating circuit, integrated circuit and electronic equipment
KR100960799B1 (en) Oscillator based on jittering
US11855538B2 (en) Out-of-audio (OOA) switching voltage regulator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant