CN111883478B - Contact hole connection method of 1.5T SONOS flash memory device - Google Patents
Contact hole connection method of 1.5T SONOS flash memory device Download PDFInfo
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- CN111883478B CN111883478B CN202010620711.4A CN202010620711A CN111883478B CN 111883478 B CN111883478 B CN 111883478B CN 202010620711 A CN202010620711 A CN 202010620711A CN 111883478 B CN111883478 B CN 111883478B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000000295 complement effect Effects 0.000 claims abstract description 6
- 230000003321 amplification Effects 0.000 claims abstract description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 27
- 238000003860 storage Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 108010001267 Protein Subunits Proteins 0.000 claims description 3
- 230000006872 improvement Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a contact hole connection method of a 1.5T SONOS flash memory device, which comprises the steps of planning a plurality of active areas on a semiconductor substrate, wherein the active areas are in a plurality of mutually parallel strips; a plurality of polysilicon lines which are parallel to each other and are perpendicular to the active regions are arranged above the plurality of active regions, a plurality of contact holes are respectively formed between the polysilicon lines and the semiconductor substrate below the polysilicon lines, and the plurality of contacts Kong Bikai are arranged in the active regions and are positioned in the regions between the active regions; the size of the contact hole is larger than the width of the polysilicon lines, and the widths of the parallel polysilicon lines in the contact hole area become larger so as to meet the requirement of the falling hole size of the contact hole; and every certain number of nodes are spaced, concentrated contact areas of contact holes of one polysilicon line are arranged between the active areas, and the contact hole areas of adjacent polysilicon lines are subjected to complementary local amplification and staggered with each other so as to save the occupied area of the contact hole areas.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing processes, in particular to a contact hole connection method of a 1.5T SONOS flash memory device.
Background
The cell structure of a Silicon-Oxide-Nitride-Oxide-Silicon (S0N 0S) memory comprises a memory cell (cell) tube and a selection tube, wherein the gate dielectric layers of the two devices bear a longitudinal electric field strength which is larger than that of the CMOS devices when the memory works, so that the two devices have larger GIDL leakage currents. The cell tube of the S0N0S memory has a higher concentration of N-type impurity doped in the channel to form a drain region (LDD) that is less doped than the select tube. The selection tube and the cell tube share LDD and HALO ion implantation, so that LDD doping of the two tubes cannot be distinguished; halo ion implantation is a large angle implantation for suppressing channeling and preventing source drain punch-through. Too high an LDD doping of the S0N0S cell can cause gate-induced drain leakage (gate-1nduce drain leakage,GIDL) and channel leakage, as well as interference (disturb) due to too strong longitudinal electric field in the S0N0S dielectric layer.
SONOS technology, which has a low operating voltage and better COMS process compatibility, is widely used in applications of various embedded electronic products such as financial IC cards, automotive electronics, and the like. 2T SONOS (2 transistors) technology is favored for many applications because of its low power consumption. But the inherent disadvantage of the 2T structure is its large chip area loss. The 2T structure comprises a common doped region, a source region and a drain region between two polysilicon gates, so that the polysilicon gates have larger spacing, and therefore, larger area can be occupied. Compared with a 2T SONOS, the area of the SONOS device with the split gate of 1.5T is saved. As shown in fig. 1, the schematic diagram of the cross-sectional structure of a conventional 1.5T SONOS memory is shown, wherein the inside is near SL and the outside is near a select transistor, and in the SONOS device, a select transistor is controlled to select a memory cell, and data is stored in the memory transistor. In the figure, 1 is a silicon substrate, 2 is an ONO memory layer of a memory tube, 3 is a gate dielectric layer of a selection tube, 4 is a polysilicon gate of the memory tube, 5 is a polysilicon gate of the selection tube, 6 is a common source polysilicon line (SL), 7 is an interval oxidation dielectric layer, and 8 is a contact hole (connection bit line BL). Two SONOS devices back-to-back share a centrally placed Source Line (SL), each SONOS device consists of one select pipe (word line WL1, WL 2) and one memory pipe (word line WLs1, WLs 2), and contains two bit lines BL, which require 7 contact holes to be tapped. Conventional contacts Kong Jiefa, as shown in fig. 2, require that the word lines WL and WLs themselves have sufficient width to allow the contact holes to connect and not short to each other, which limits the device size reduction in the X-direction.
Disclosure of Invention
The invention aims to provide a contact hole connection method of a 1.5T SONOS flash memory device, which can save the layout occupation area of a memory unit.
In order to solve the above problems, the contact hole connection method of a 1.5T SONOS flash memory device according to the present invention includes: planning a plurality of active areas on a semiconductor substrate, wherein the active areas are in a plurality of mutually parallel strips; the length and the width of each strip-shaped active area are the same;
a plurality of polysilicon lines which are parallel to each other and are perpendicular to the active regions are arranged above the plurality of active regions, a plurality of contact holes are respectively formed between the polysilicon lines and the semiconductor substrate below the polysilicon lines, and the plurality of contacts Kong Bikai are arranged in the active regions and are positioned in the regions between the active regions;
the size of the contact hole is larger than the width of the polysilicon lines, and the widths of the parallel polysilicon lines in the contact hole area become larger so as to meet the requirement of the falling hole size of the contact hole;
and every certain number of nodes are spaced, concentrated contact areas of contact holes of one polysilicon line are arranged between the active areas, and the contact hole areas of adjacent polysilicon lines are subjected to complementary local amplification and staggered with each other so as to save the occupied area of the contact hole areas.
The semiconductor substrate is a silicon substrate.
The further improvement is that the plurality of active areas each form a memory cell of a 1.5T SONOS flash memory device; the polysilicon lines above the polysilicon lines form the grids of related sub-units, including the grid of the selection tube, the grid of the storage tube and the common source polysilicon line, and the polysilicon lines are also used as wires for connecting the grids of all the sub-units.
A further improvement is that the polysilicon line, or the metal line; metal silicide can also be manufactured above the polysilicon lines to reduce resistance.
The polysilicon lines are further improved, the contact hole area of one polysilicon line is set in the concentrated contact area, the contact hole area of the other polysilicon line adjacent to the polysilicon line is staggered with the contact hole area, and the mutually meshed jigsaw shape is formed, so that the size of each effective contact hole area can be ensured, and the whole layout occupation area of the concentrated contact area is reduced.
The active region is characterized in that devices in the active region are symmetrically arranged and comprise a selection tube and a storage tube, and the selection tube and the storage tube are also arranged on one side of the selection tube and the storage tube which is symmetrical to a common source polycrystalline silicon line; wherein the positions of the selection tube and the symmetrical tube can be interchanged.
The further improvement is that the two ends of the strip-shaped active area are also provided with contact holes, and bit lines of the memory cells are led out.
The further improvement is that two or more contact holes can be arranged on any one or more polysilicon lines in the concentrated contact area so as to meet the process requirement of the cross-layer connection of the subsequent metal lines.
According to the contact hole connection method of the 1.5T SONOS flash memory device, the polysilicon gate of a memory unit or the metal silicide at the top of the polysilicon gate is used as a lead, concentrated contact areas are arranged at a certain number of nodes, the contact areas are connected out through locally amplified contact holes, and particularly the contact holes of control lines (WL and WLS) of a selection tube and a storage tube are made into complementary structures, so that not only is enough hole falling space of the contact holes at the nodes ensured, but also the area of a conventional unit can be saved; in addition, two or more contact holes are designed at WL (or WLS), so that the method can be used for the cross-layer connection of a subsequent metal wire, and the size of the SONOS device in the X direction can be effectively reduced, so that the area of a memory cell is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a 1.5T SONOS flash memory device structure of the present invention.
Fig. 2 is a schematic diagram of a contact hole connection method of a conventional 1.5T SONOS flash memory device.
Fig. 3 is a schematic diagram of a contact hole connection method of a 1.5T SONOS flash memory device according to the present invention.
Fig. 4 is a schematic diagram of a method for connecting a contact hole and a subsequent metal line of the 1.5T SONOS flash memory device according to the present invention.
Description of the reference numerals
Detailed Description
The contact hole connection method of the 1.5T SONOS flash memory device of the invention, as shown in figure 3, comprises the following steps: a plurality of active areas AA are planned on a semiconductor substrate, which may be a silicon substrate or other semiconductor material. The active area AA is in a plurality of mutually parallel strips; the length and the width of each strip-shaped active region are the same.
Above the active regions, there are also several polysilicon lines parallel to each other and perpendicular to the active regions, and also metal lines. A metal silicide can also be fabricated over the polysilicon lines to reduce resistance. A plurality of contact holes are respectively formed between the polysilicon lines and the semiconductor substrate below the polysilicon lines, and the plurality of contacts Kong Bikai are respectively arranged in the active areas and are positioned in the areas between the active areas. The active areas form a storage unit of the 1.5T SONOS flash memory device; the polysilicon lines above the polysilicon lines form the grids of related sub-units, including the grid of the selection tube, the grid of the storage tube and the common source polysilicon line, and the polysilicon lines are also used as wires for connecting the grids of all the sub-units.
In fig. 3, a planar layout is shown, which corresponds to the cross-sectional view shown in fig. 1, and a plurality of polysilicon lines or metal lines vertically arranged in fig. 3 correspond to WLS1, WL1, SL, WL2, WLS2 one by one from left to right in fig. 1, and also referring to fig. 2, two bit lines BL in fig. 1 are not shown in fig. 3.
The size of the contact hole is larger than the width of the polysilicon lines, the parallel polysilicon lines are thinner than the polysilicon lines in the traditional layout design, the line spacing is narrower, the occupied size in the X direction can be reduced, and the width of the polysilicon lines in the contact hole area is enlarged so as to meet the requirement of the falling hole size of the contact hole.
And every certain number of nodes are spaced, concentrated contact areas of contact holes of one polysilicon line are arranged between the active areas, and the contact hole areas of adjacent polysilicon lines are subjected to complementary local amplification and staggered with each other so as to save the occupied area of the contact hole areas.
The polycrystalline silicon wires are arranged in the concentrated contact area, the contact hole area of one polycrystalline silicon wire is set, the contact hole area of the other polycrystalline silicon wire adjacent to the polycrystalline silicon wire is staggered, and the mutually meshed jigsaw appearance is formed, so that the size of each effective contact hole area can be ensured, and the occupied area of the whole layout of the concentrated contact area is reduced.
The active region is symmetrically arranged and comprises a selection tube and a storage tube, and the selection tube and the storage tube are also arranged on one symmetrical side of the common source polysilicon line; wherein the positions of the selection tube and the symmetrical tube can be interchanged. I.e. the locations of the storage tube at 4 and the selection tube at 5 as shown in fig. 1 can be interchanged without affecting the function or performance of the device.
Two or more contact holes can be arranged on any one or more polysilicon lines in the concentrated contact area, so that the process requirement of cross-layer connection of the subsequent metal lines can be met.
In the process of manufacturing a certain memory cell, the layout shown in fig. 3 is used, a contact hole of a common source polysilicon line SL is connected to each 64 active areas AA (32aa+32aa), two WL contact holes and one WLs contact hole are connected to each 64 AA at intervals, and 32AA are arranged between adjacent SL contact holes and WL contact holes at intervals. In the conventional 32AA units, the five polysilicon lines do not need to be connected with the contact holes, so that the size of the X direction (transverse direction) can be greatly reduced, and enough contact hole falling space is ensured in the concentrated contact area with the enlarged special nodes. By adopting the connection method of the contact hole, the size of the X direction can be greatly reduced on the basis of the size of the Y direction of the sacrifice part, and the area of the whole storage area can be further reduced.
As shown in fig. 4, the subsequent metal lines of the memory cell structure are connected to the bit lines BL on the plurality of active areas AA through the lateral metal lines M1. WL1, WLs1, WL2, WLs2 are connected by metal lines in the longitudinal direction, and if the existing contact hole connection method is adopted, four metal lines are required in the longitudinal direction at the same time, which also limits the size of the memory cell in the X direction. By adopting the contact hole connection design of the invention, two contact holes are arranged between adjacent WLS, and metal overwires can be realized through M1, so that the metal wires of WL and WLS are distributed in different layers, namely, the two contact holes of WL are connected into M2 through M1 overlayers, and the contact holes of WLS are connected into M3. Thus, only two metal lines M2 or M3 (vertical dotted outline) are longitudinally arranged in each metal layer, and the dimension of the memory cell in the X direction can be greatly reduced. The metal wire M2 is connected with corresponding WL, and two WL contact holes are connected through the C-shaped metal wire M1 and then connected through the metal wire M2; i.e., WL into M2, WLs into M3. The metal lines M2 and M3 are respectively in different layers even if they are both longitudinally parallel.
According to the contact hole connection method, the concentrated contact areas are arranged at a certain number of nodes, and the contact holes are connected out through the locally enlarged contact holes to be placed in a staggered complementary structure, so that not only is enough hole falling space of the contact holes at the nodes ensured, but also the area of a conventional unit can be saved; in addition, two or more contact holes are designed at WL (or WLS), so that the method can be used for the cross-layer connection of a subsequent metal wire, and the size of the SONOS device in the X direction can be effectively reduced, so that the area of a memory cell is reduced.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A contact hole connection method of a 1.5T SONOS flash memory device comprises the steps of programming a plurality of active areas on a semiconductor substrate, wherein the active areas are in a plurality of mutually parallel strips; the length and the width of each strip-shaped active area are the same;
a plurality of polysilicon lines which are parallel to each other and are perpendicular to the active regions are arranged above the plurality of active regions, a plurality of contact holes are respectively formed between the polysilicon lines and the semiconductor substrate below the polysilicon lines, and the plurality of contacts Kong Bikai are arranged in the active regions and are positioned in the regions between the active regions;
the method is characterized in that: the size of the contact hole is larger than the width of the polysilicon lines, and the widths of the parallel polysilicon lines in the contact hole area become larger so as to meet the requirement of the falling hole size of the contact hole;
and every certain number of nodes are spaced, concentrated contact areas of contact holes of one polysilicon line are arranged between the active areas, and the contact hole areas of adjacent polysilicon lines are subjected to complementary local amplification and staggered with each other so as to save the occupied area of the contact hole areas.
2. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: the active areas form a storage unit of the 1.5T SONOS flash memory device; the polysilicon lines above the polysilicon lines form the grids of related sub-units, including the grid of the selection tube, the grid of the storage tube and the common source polysilicon line, and the polysilicon lines are also used as wires for connecting the grids of all the sub-units.
4. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: optionally, metal silicide can be manufactured above the polysilicon line to reduce resistance; the polysilicon line is a metal line when the polysilicon is replaced by metal.
5. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: the polycrystalline silicon wires are arranged in the concentrated contact area, the contact hole area of one polycrystalline silicon wire is set, the contact hole area of the other polycrystalline silicon wire adjacent to the polycrystalline silicon wire is staggered, and the mutually meshed jigsaw appearance is formed, so that the size of each effective contact hole area can be ensured, and the occupied area of the whole layout of the concentrated contact area is reduced.
6. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: the active region is symmetrically arranged and comprises a selection tube and a storage tube, and the selection tube and the storage tube are also arranged on one symmetrical side of the common source polysilicon line; wherein the positions of the selection tube and the symmetrical tube can be interchanged.
7. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: the two ends of the strip-shaped active area are also provided with contact holes, and bit lines of the memory cells are led out.
8. The method for connecting contact holes of a 1.5T SONOS flash memory device of claim 1, wherein: two or more contact holes can be optionally additionally arranged on any one or more polysilicon lines in the concentrated contact area so as to meet the process requirement of cross-layer connection of the subsequent metal lines.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010620711.4A CN111883478B (en) | 2020-07-01 | 2020-07-01 | Contact hole connection method of 1.5T SONOS flash memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010620711.4A CN111883478B (en) | 2020-07-01 | 2020-07-01 | Contact hole connection method of 1.5T SONOS flash memory device |
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| CN111883478B true CN111883478B (en) | 2024-02-09 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1241817A (en) * | 1998-06-15 | 2000-01-19 | 日本电气株式会社 | Semiconductor memory and manufacturing method thereof |
| US6081444A (en) * | 1998-07-09 | 2000-06-27 | Fujitsu Limited | Static memory adopting layout that enables minimization of cell area |
| CN1302085A (en) * | 1999-12-30 | 2001-07-04 | 现代电子产业株式会社 | Rowed transistor in semiconductor |
| US6271548B1 (en) * | 1996-05-24 | 2001-08-07 | Kabushiki Kaisha Toshiba | Master slice LSI and layout method for the same |
| CN104347634A (en) * | 2013-07-30 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Flash memory cell array |
| CN108364952A (en) * | 2018-01-29 | 2018-08-03 | 上海华力微电子有限公司 | The manufacturing method of flash memory |
-
2020
- 2020-07-01 CN CN202010620711.4A patent/CN111883478B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271548B1 (en) * | 1996-05-24 | 2001-08-07 | Kabushiki Kaisha Toshiba | Master slice LSI and layout method for the same |
| CN1241817A (en) * | 1998-06-15 | 2000-01-19 | 日本电气株式会社 | Semiconductor memory and manufacturing method thereof |
| US6081444A (en) * | 1998-07-09 | 2000-06-27 | Fujitsu Limited | Static memory adopting layout that enables minimization of cell area |
| CN1302085A (en) * | 1999-12-30 | 2001-07-04 | 现代电子产业株式会社 | Rowed transistor in semiconductor |
| CN104347634A (en) * | 2013-07-30 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Flash memory cell array |
| CN108364952A (en) * | 2018-01-29 | 2018-08-03 | 上海华力微电子有限公司 | The manufacturing method of flash memory |
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