CN111882018A - SMD SD NAND Flash IC memory - Google Patents
SMD SD NAND Flash IC memory Download PDFInfo
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- CN111882018A CN111882018A CN202010698966.2A CN202010698966A CN111882018A CN 111882018 A CN111882018 A CN 111882018A CN 202010698966 A CN202010698966 A CN 202010698966A CN 111882018 A CN111882018 A CN 111882018A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/0772—Physical layout of the record carrier
- G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0617—Improving the reliability of storage systems in relation to availability
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Abstract
The invention relates to the technical field of memory cards, and discloses a surface mounted Secure Digital (SD) NAND Flash Integrated Circuit (IC) memory with high scratch resistance, which comprises the following components: the interface circuit is electrically connected with an interface of external equipment; the data transmission circuit is used for receiving data input by external equipment and storing the data; the signal processing circuit is used for processing data; the data transmission circuit comprises an SD NAND Flash controller and a customized SD which are mutually connected, wherein the SD NAND Flash controller is used for receiving data input by external equipment, sequentially inputting the data into the first memory card and the second memory card and storing the sequentially input data; the microcontroller is used for processing data input into the SD NAND Flash controller, collecting data output by the SD NAND Flash controller and processing the data.
Description
Technical Field
The invention relates to the technical field of memory cards, in particular to a surface-mounted SD NAND Flash IC memory.
Background
The traditional T card and SD card are independent finished products packaged by a module, and are inserted, and the golden fingers of the cards are used as contact points for power supply and data transmission. At present, SD NAND Flash is directly attached to a PCB (printed Circuit Board), and a package in a patch IC (integrated Circuit) form is adopted, so that the stability of the SD NAND Flash welded on the PCB is higher. However, the T card and the SD card are fixed in a plug-in type, which results in a reduced lifetime of the memory due to the low endurance of the memory.
Therefore, how to increase the endurance count of the memory becomes a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to solve the technical problem of providing a chip type SD NAND flash IC memory with higher scratch resistance times, aiming at the defect that the service life of the memory is shortened due to low scratch resistance times of the memory in the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a surface mount type SD NAND Flash IC memory is constructed, and the memory comprises:
the interface circuit is electrically connected with an interface of external equipment;
the data transmission circuit is used for receiving data input by the external equipment and storing the data;
a signal processing circuit for processing the data;
the interface circuit comprises a singlechip, and the singlechip is used for generating a clock pulse signal;
the data transmission circuit comprises an SD NAND Flash controller and a customized SD which are connected with each other, wherein the customized SD comprises a first memory card and a second memory card;
the signal input end of the SD NAND Flash controller is connected with the signal output end of the external equipment and is used for receiving the data input by the external equipment and sequentially inputting the data into the first storage card and the second storage card;
the first memory card and the second memory card store the data input in sequence;
the signal processing circuit comprises a microcontroller for processing the data input to the SD NAND flash controller;
and the signal input end of the microcontroller is connected with the signal output end of the SD NAND Flash controller and is used for acquiring and processing the data output by the SD NAND Flash controller.
In some embodiments, a storage interface defined by TF and SD is used for data management or SD/SPI directly connected with MCU can be used, and a Flash management program is built in.
In some embodiments, the data transmission circuit further comprises a first resistor, a second resistor and a third resistor,
one end of the first resistor is connected with a power supply end, and the other end of the first resistor is connected with a bidirectional data end of the SD NANDFlash controller;
one end of the second resistor is connected with a power supply end, and the other end of the second resistor is connected with a response signal end of the SD NANDFlash controller;
the third resistor is arranged between the clock signal end of the customized SD and the clock signal end of the SD NAND Flash controller.
In some embodiments, the data transmission circuit further comprises a first capacitor, a second capacitor and a third capacitor,
one end of the first capacitor is connected with a response signal end of the SD NAND Flash controller;
one end of the second capacitor is connected with the bidirectional data end of the SD NAND Flash controller;
one end of the third capacitor is connected with a clock signal end of the SD NAND Flash controller;
the other ends of the first capacitor, the second capacitor and the third capacitor are respectively connected with a common end.
In some embodiments, the signal processing circuit further comprises a fourth resistor and a fifth resistor connected in parallel,
one end of the fourth resistor and one end of the fifth resistor are connected with a power supply end;
the other end of the fourth resistor is coupled to a signal end of the microcontroller;
the other end of the fifth resistor is coupled to the other signal end of the microcontroller.
In some embodiments, the signal processing circuit further comprises a fourth capacitor and a fifth capacitor connected in parallel,
one end of the fourth capacitor and one end of the fifth capacitor are respectively connected with a power supply signal end of the microcontroller;
one end of the fourth capacitor and one end of the fifth capacitor are respectively connected with a common end.
In some embodiments, the interface circuit further comprises a first transistor, a tenth resistor, and an eleventh resistor,
the base electrode of the first triode is connected with the power supply signal end of the singlechip through the tenth resistor;
one end of the eleventh resistor is connected with the emitting electrode of the first triode and the power signal end respectively;
the other end of the eleventh resistor is connected with the base electrode of the first triode.
In some embodiments, the interface circuit further includes a first crystal oscillator, a sixteenth resistor, and a seventeenth resistor,
wherein the first crystal oscillator is connected in parallel with the seventeenth resistor;
one end of the first crystal oscillator is connected with one crystal oscillator end of the single chip microcomputer;
the other end of the first crystal oscillator is connected with the other crystal oscillator end of the single chip microcomputer through the sixteenth resistor.
In some embodiments, the interface circuit further comprises a seventh capacitor and an eighth capacitor connected in series,
one end of the seventh capacitor is connected with one end of the first crystal oscillator;
and one end of the eighth capacitor is connected with the other end of the first crystal oscillator.
The surface mount type SD NAND flash IC memory comprises an interface circuit which is electrically connected with an interface of external equipment; the data transmission circuit is used for receiving data input by external equipment and storing the data; the signal processing circuit is used for processing data. Compared with the prior art, the built-in FW of the SD NAND Flash controller comprises processing mechanisms such as average reading and writing, bad block management and garbage collection, so that the problems of low erasing and writing resistant times and poor stability of a memory are solved.
The technical scheme has the following beneficial effects:
1. the driver-free (i.e. paste and use) direct connection with the SD/SPI of the MCU can be used, and a Flash management program is built in;
2. the LGA-8 packaging can be realized by machine pasting (high production efficiency/stable welding), and the machine pasting and the hand pasting are both convenient;
3. long erasing life (the erasing life of the built-in SLC/MLC/TLC wafer can reach 5-10 ten thousand times, which is generated by embedding);
4. the test is stable and reliable, and the test passes 1 ten thousand times of random power failure and high and low temperature power failure tests.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1a is a circuit diagram of a data transmission circuit of an embodiment of a surface mount type SD NAND Flash IC memory provided by the present invention;
FIG. 1b is a circuit diagram of another embodiment of a data transmission circuit of a surface mount type SD NAND Flash IC memory provided by the present invention;
FIG. 2 is a signal processing circuit diagram of one embodiment of a surface mount SD NAND Flash IC memory provided in the present invention;
FIG. 3 is an interface circuit diagram of an embodiment of a surface mount SD NAND Flash IC memory provided in the present invention.
Detailed Description
For a more clear understanding of the technical features, objects and effects of the present invention, embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
As shown in fig. 1 a-3, in the first embodiment of the chip on SD NAND Flash IC memory of the present invention, the chip on SD NAND Flash IC memory includes a data transmission circuit (100a, b), a signal processing circuit 200 and an interface circuit 300.
The data transmission circuit (100a, 100b) is used for receiving data input by an external device and storing the data, and the transmission mode can adopt parallel communication and serial communication, wherein the parallel communication transmits each bit of the data at the same time; serial communication causes data to be transferred sequentially, bit by bit.
The signal processing circuit 200 is used for processing data input to the data transmission circuit (100a, 100b) to improve the data transmission rate.
The interface circuit 300 is used to establish an on-line programming SPI mode and an on-system programming function ICP, providing a variety of programming modes for users.
Specifically, the interface circuit 300 is also used for storing and reading card clocks and data, signals such as RST, FUS, PGM and the like required by other types of IC cards are reserved, and the insertion and the extraction of the IC card can be identified through a switch on an IC card adapting socket.
Specifically, the interface circuit 300 is disposed in the memory IC and electrically connected to an interface of an external device (such as a mobile phone, a notebook, or a camera) to establish an SDIO mode or an SPI mode, and establish an initial state for the data transmission circuit (100a, 100b) to collect data.
The signal input end of the data transmission circuit (100a, 100b) is electrically connected with the signal output end of the external equipment, and the data transmission circuit (100a, 100b) is used for receiving data input by the external equipment and storing the data according to the input data.
The signal input end of the signal processing circuit 200 is connected with the signal output end of the data transmission circuit (100a, 100b), and is used for receiving the data output by the data transmission circuit (100a, 100b) and processing the data.
Specifically, the signal processing circuit 200 performs a batch data read test (i.e., data processing). The 2-byte data length is written first, and then the subsequent data streams are read one by the length, which is typically used in conjunction with the CMD _ BULK _ WR _ TEST command for testing the correctness of external devices and data transfer circuits (100a, 100b) for BULK data transfer.
The interface circuit 300 includes a single chip microcomputer U301 for generating a clock signal.
The data transmission circuit (100a, 100b) includes an SD NAND Flash controller U101 and a custom SDU102(a, b) connected to each other, wherein the custom SD U102(a, b) includes a first memory card U102a and a second memory card U102 b.
The SD NAND Flash controller U101 and the custom SD U102(a, b) have a clock signal (corresponding to the CLK terminal), a bidirectional data terminal (corresponding to the DAT terminal), and a response signal terminal (corresponding to the CMD terminal).
Wherein, the clock signal (corresponding to the CLK end) transmits one command bit or data bit in each clock cycle, the frequency can be changed between 0-25MHz in the default speed mode of the SD bus, the bus manager of the SD card can freely generate the frequency between 0-5MHz without any limitation, and the clock frequency can reach up to 208M in the UHS-I speed mode.
The response signal terminal (corresponding to the CMD terminal) is sent to the customized SD card by the SD NAND Flash controller U101, and may be from the controller to a single SD card or to all cards on the SD bus.
The bidirectional data terminal (corresponding to the DAT terminal) can be transmitted from the SD card to the SD NAND Flash controller U101, and can also be transmitted from the SDNAND Flash controller U101 to the SD card.
Specifically, a signal input end of the SD NAND Flash controller U101 is connected to a signal output end of an external device, and is configured to receive data input by the external device.
The signal output terminals (corresponding to CMD, DAT, and CLK) of the SD NAND Flash controller U101 are connected to the signal input terminals (corresponding to CMD, DAT, and CLK) of the custom SDUs 102(a, b), and more specifically, the signal output terminals (corresponding to CMD, DAT, and CLK) of the SD NAND Flash controller U101 are connected to the signal input terminals (corresponding to CMD, DAT, and CLK) of the first memory card U102 a.
The signal output terminals (corresponding to CMD, DAT and CLK) of the SD NAND Flash controller U101 are connected to the signal input terminals (corresponding to CMD, DAT and CLK) of the second memory card U102 b,
the SD NAND Flash controller U101 sequentially outputs the input data to the first memory card U102a and the second memory card U102 b, and the memory cards store the sequentially input data.
Further, the signal processing circuit 200 includes a microcontroller U201 for processing data input to the SD NAND Flash controller U101 to increase the corresponding speed of the input data.
And a signal input end of the microcontroller U201 is connected with a signal output end of the SD NAND Flash controller U101, and is used for acquiring data output by the SD NAND Flash controller U101 and processing the data.
The SD NAND Flash controller U101 is internally provided with FW (firmware Flash) including processing mechanisms such as average reading and writing, bad block management and garbage collection, so that the problems of low erasing and writing resistant times and poor stability of a memory are solved.
The technical scheme has the following beneficial effects:
the driver-free (i.e. paste and use) direct connection with the SD/SPI of the MCU can be used, and a Flash management program is built in;
the LGA-8 packaging can be realized by machine pasting (high production efficiency/stable welding), and the machine pasting and the hand pasting are both convenient;
long erasing life (the erasing life of the built-in SLC/MLC/TLC wafer can reach 5-10 ten thousand times, which is generated by embedding);
the test is stable and reliable, and the test passes 1 ten thousand times of random power failure and high and low temperature power failure tests.
In some embodiments, the TF and the SD are packaged in a patch manner, and a storage interface defined by the TF and the SD is used for data management or directly connected with the SD/SPI of the MCU, and a Flash management program is already built in.
In some embodiments, in order to improve the performance of the data transmission circuit 100a, a first resistor R101, a second resistor R102 and a third resistor R103 may be disposed in the data transmission circuit 100 a.
Specifically, one end of the first resistor R101 is connected to a power supply terminal (corresponding VCC), the other end of the first resistor R101 is connected to a bidirectional data terminal (corresponding DAT terminal) of the SD NAND Flash controller U101, one end of the second resistor R102 is connected to the power supply terminal (corresponding VCC), and the other end of the second resistor R102 is connected to a response signal terminal (corresponding CMD terminal) of the SD NAND Flash controller U101.
The third resistor R103 is disposed between the clock signal terminal (corresponding to the CLK terminal) of the custom SD U102(a, b) and the clock signal terminal (corresponding to the CLK terminal) of the SD nand flash controller U101.
The driving signal input by the power source terminal is input into the SD NAND Flash controller U101 through the first resistor R101 and the second resistor R102 to trigger the SD NAND Flash controller U101 to operate, so that the SD NAND Flash controller U101 transmits data to the customized SD U102(a, b).
In some embodiments, the data transmission circuit 100a further includes a first capacitor C101, a second capacitor C102, and a third capacitor C103. The capacitor is used for eliminating the interference of medium and high frequency signals.
Specifically, one end of the first capacitor C101 is connected to a response signal end (corresponding to the CMD end) of the SD NAND Flash controller U101.
One end of the second capacitor C102 is connected to a bidirectional data terminal (corresponding DAT terminal) of the SD NAND Flash controller U101.
One end of the third capacitor C103 is connected to a clock signal end (corresponding to the CLK end) of the SD NAND Flash controller U101.
The other ends of the first capacitor C101, the second capacitor C102 and the third capacitor C103 are connected to a common terminal, respectively.
In some embodiments, the signal processing circuit 200 further includes a fourth resistor R201 and a fifth resistor R202, wherein the fourth resistor R201 is connected in parallel with the fifth resistor R202.
Specifically, one end of the fourth resistor R201 and one end of the fifth resistor R202 are connected to a power source terminal (corresponding to 3.3V), and a 3.3V power signal is input to the microcontroller U201 through the fourth resistor R201 and the fifth resistor R202 to provide a working power source for the operation thereof.
The other end of the fourth resistor R201 is connected to a signal terminal (corresponding to the SDD2 terminal) of the microcontroller U201.
The other end of the fifth resistor R202 is coupled to another signal terminal (corresponding to the SDD3 terminal) of the microcontroller U201.
In some embodiments, the signal processing circuit 200 further includes a seventh resistor R204, a fourth capacitor C201, and a fifth capacitor C202, wherein the fourth capacitor C201 is connected in parallel with the fifth capacitor C202.
Specifically, one end of the fourth capacitor C201 and one end of the fifth capacitor C202 are respectively connected to a power signal terminal (corresponding to the VCC terminal) of the microcontroller U201.
One end of each of the fourth capacitor C201 and the fifth capacitor C202 is connected to the common terminal.
One end of the seventh resistor R204 is connected to a power supply terminal (corresponding to 3.3V), a power signal terminal (corresponding to VCC terminal) of the microcontroller U201 is connected to the other end of the seventh resistor R204, and a 3.3V input current is input to the microcontroller U201 through the seventh resistor R204 to provide a working power supply for the microcontroller U201.
In some embodiments, the interface circuit 300 further includes a first transistor Q301, a tenth resistor R301, and an eleventh resistor R302. The first transistor Q301 is a PNP transistor, and has switching and amplifying functions.
Specifically, the base of the first triode Q301 is connected to the power signal terminal (corresponding to ic. vcc terminal) of the single chip microcomputer U301 through the tenth resistor R301.
One end of the eleventh resistor R302 is connected to the emitter of the first transistor Q301 and the power signal terminal (corresponding to the VCC terminal), respectively, and the other end of the eleventh resistor R302 is connected to the base of the first transistor Q301.
In some embodiments, the interface circuit 300 further includes a first crystal oscillator X301, a sixteenth resistor R307, and a seventeenth resistor R308, wherein the first crystal oscillator X301 is configured to generate a pulse clock signal.
The first crystal oscillator X301 is connected in parallel with the seventeenth resistor R308, one end of the first crystal oscillator X301 is connected to one crystal oscillator end (corresponding to the XTAL1 end) of the single chip microcomputer U301, and the other end of the first crystal oscillator X301 is connected to the other crystal oscillator end (corresponding to the XTAL2 end) of the single chip microcomputer U301 through the sixteenth resistor R307.
In some embodiments, the interface circuit 300 further includes a seventh capacitor C302 and an eighth capacitor C303.
The seventh capacitor C302 is connected in series with the eighth capacitor C303, one end of the seventh capacitor C302 is connected with one end of the first crystal oscillator X301, one end of the eighth capacitor C303 is connected with the other end of the first crystal oscillator X301, and a pulse clock signal generated by the first crystal oscillator X301 is input to the single chip microcomputer U301.
It should be noted that: the SD NAND Flash is initialized by following the following program example:
1. support initialization votage
The host system may apply an operating voltage to initialize SD NAND Flash,
SD NAND Flash with simple clock over 74 period;
2. selecting run mode (SDIO mode or SPI mode)
When operating in SPI mode, the host should drive 1pin of SD NAND Flash (CD/DAT3) at low level;
CMDO problem, when operating using SDIO mode, the host should drive or detect the SD NAND FlashVF 1p (1 pin pull-up register pulled out) pair ria' omam,
the SD NAND Flash maintains the selected operation mode, except for reissuing CMDO or poweron, and is an SDIO mode initialization program;
3. transmitting ACMD41 with Arg-0 and identifying the working voltage range of the card;
4. applying the indicated operating voltage to the SD NAND Flash
Repeating ACMD41 with the application voltage storage and repeating ACMD41 until the busy bit is cleared.
(bit 31 busy 1) if the response times out, the host may recognize that it is not SD NAND Flash.
5. Issuing CMD2, obtaining card id (cid).
CMD3 is issued and the RCA is obtained,
the RCA value is randomly changed by the access and is not equal to zero;
6. issue CMD7 and move to the transmit state
If necessary, the host may issue ACMD 42 and disable pull-up resistance card detection;
7. issuing ACMD13, polling SD NAND Flash storage state
The SD NAND Flash type value is checked, if the valid 8 bits are "all zeros",
namely the SD NAND Flash,
if not, stopping initialization;
8. issue CMD7 and move to Standby
Issues CMD9 and obtains the CSD,
lsue CMD10, obtaining CID;
9. returning transmission status with CMD7
Issue ACMD6 and select the appropriate bus width;
then, the host can access data between SD NAND Flash as a storage device.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A surface mount type SD NAND Flash IC memory is characterized by comprising:
the interface circuit is electrically connected with an interface of external equipment;
the data transmission circuit is used for receiving data input by the external equipment and storing the data;
a signal processing circuit for processing the data;
the interface circuit comprises a singlechip, and the singlechip is used for generating a clock pulse signal;
the data transmission circuit comprises an SD NAND Flash controller and a customized SD which are connected with each other, wherein the customized SD comprises a first memory card and a second memory card;
the signal input end of the SD NAND Flash controller is connected with the signal output end of the external equipment and is used for receiving the data input by the external equipment and sequentially inputting the data into the first storage card and the second storage card;
the first memory card and the second memory card store the data input in sequence;
the signal processing circuit comprises a microcontroller, and the microcontroller is used for processing the data input into the SD NAND Flash controller;
and the signal input end of the microcontroller is connected with the signal output end of the SD NAND Flash controller and is used for acquiring and processing the data output by the SD NAND Flash controller.
2. The SMD NAND Flash IC memory according to claim 1,
and data management is carried out by adopting a storage interface defined by TF and SD or the SD/SPI of the MCU can be directly connected for use, and a Flash management program is built in.
3. The SMD NAND Flash IC memory according to claim 1,
the data transmission circuit also comprises a first resistor, a second resistor and a third resistor,
one end of the first resistor is connected with a power supply end, and the other end of the first resistor is connected with a bidirectional data end of the SD NAND Flash controller;
one end of the second resistor is connected with a power supply end, and the other end of the second resistor is connected with a response signal end of the SD NAND Flash controller;
the third resistor is arranged between the clock signal end of the customized SD and the clock signal end of the SD NAND Flash controller.
4. The SMD NAND FlashIC memory according to claim 3,
the data transmission circuit further comprises a first capacitor, a second capacitor and a third capacitor,
one end of the first capacitor is connected with a response signal end of the SD NAND Flash controller;
one end of the second capacitor is connected with the bidirectional data end of the SD NAND Flash controller;
one end of the third capacitor is connected with a clock signal end of the SD NAND Flash controller;
the other ends of the first capacitor, the second capacitor and the third capacitor are respectively connected with a common end.
5. The SMD NAND FlashIC memory according to claim 1,
the signal processing circuit further comprises a fourth resistor and a fifth resistor which are connected in parallel,
one end of the fourth resistor and one end of the fifth resistor are connected with a power supply end;
the other end of the fourth resistor is coupled to a signal end of the microcontroller;
the other end of the fifth resistor is coupled to the other signal end of the microcontroller.
6. The SMD NAND FlashIC memory according to claim 5,
the signal processing circuit further comprises a fourth capacitor and a fifth capacitor connected in parallel,
one end of the fourth capacitor and one end of the fifth capacitor are respectively connected with a power supply signal end of the microcontroller;
one end of the fourth capacitor and one end of the fifth capacitor are respectively connected with a common end.
7. The SMD NAND FlashIC memory according to claim 1,
the interface circuit also comprises a first triode, a tenth resistor and an eleventh resistor,
the base electrode of the first triode is connected with the power supply signal end of the singlechip through the tenth resistor;
one end of the eleventh resistor is connected with the emitting electrode of the first triode and the power signal end respectively;
the other end of the eleventh resistor is connected with the base electrode of the first triode.
8. The SMD NAND FlashIC memory according to claim 7,
the interface circuit also comprises a first crystal oscillator, a sixteenth resistor and a seventeenth resistor,
wherein the first crystal oscillator is connected in parallel with the seventeenth resistor;
one end of the first crystal oscillator is connected with one crystal oscillator end of the single chip microcomputer;
the other end of the first crystal oscillator is connected with the other crystal oscillator end of the single chip microcomputer through the sixteenth resistor.
9. The SMD NAND FlashIC memory according to claim 8,
the interface circuit further comprises a seventh capacitor and an eighth capacitor connected in series,
one end of the seventh capacitor is connected with one end of the first crystal oscillator;
and one end of the eighth capacitor is connected with the other end of the first crystal oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010698966.2A CN111882018A (en) | 2020-07-20 | 2020-07-20 | SMD SD NAND Flash IC memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010698966.2A CN111882018A (en) | 2020-07-20 | 2020-07-20 | SMD SD NAND Flash IC memory |
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| Publication Number | Publication Date |
|---|---|
| CN111882018A true CN111882018A (en) | 2020-11-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010698966.2A Pending CN111882018A (en) | 2020-07-20 | 2020-07-20 | SMD SD NAND Flash IC memory |
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2020
- 2020-07-20 CN CN202010698966.2A patent/CN111882018A/en active Pending
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