CN111881073B - Method and device for making FPGA compatible with various hardware and electronic equipment - Google Patents
Method and device for making FPGA compatible with various hardware and electronic equipment Download PDFInfo
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- CN111881073B CN111881073B CN202010760074.0A CN202010760074A CN111881073B CN 111881073 B CN111881073 B CN 111881073B CN 202010760074 A CN202010760074 A CN 202010760074A CN 111881073 B CN111881073 B CN 111881073B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention provides a method and a device for enabling an FPGA (field programmable gate array) to be compatible with various hardware and electronic equipment, wherein the method comprises the following steps: loading an FPGA program, reading a pre-solidified type parameter in a flash memory, wherein the type parameter is used for determining the type of a receiving card connected with the FPGA; determining the type of the receiving card according to the type parameter; and determining the output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode. By applying the scheme provided by the invention, the specific type parameters are solidified in the flash, after the FPGA program is loaded, the type parameters are read back to judge the type of the receiving card, then the corresponding pin output is carried out, and the type of the receiving card is identified through the type parameters, so that the occupation of IO port resources is reduced. After the type of the receiving card is replaced, only the type parameters solidified in the flash before the type parameters are erased, and then the type parameters corresponding to the type of the replaced receiving card are written in the flash, so that the multiple types of receiving cards can be switched randomly.
Description
Technical Field
The invention relates to the technical field of LED control, in particular to a method and a device for enabling an FPGA to be compatible with various hardware and electronic equipment.
Background
At present, due to the characteristics of high visibility, low power consumption and the like, an LED display system is widely applied to various scenes in daily life. In implementation, the LED display system generally consists of an LED display screen body and an LED control system; LED display screens generally comprise: an LED lamp array and an LED driver ic; LED control systems generally comprise: a sending card and a receiving card.
In the LED control system, the types of the existing receiving cards are multiple, and the output interfaces of the receiving cards of different types are different. In the related art, a plurality of IO ports need to be reserved on an FPGA (Field Programmable Gate Array), different types of receiving cards are connected to the reserved IO ports, and then the types of the receiving cards connected to the FPGA can be determined through the IO ports.
Disclosure of Invention
The embodiment of the invention provides a method and a device for enabling an FPGA (field programmable gate array) to be compatible with various hardware and electronic equipment, so as to achieve the technical effect of reducing occupation of IO (input/output) port resources.
In one aspect of the present invention, a method for enabling an FPGA to be compatible with a plurality of hardware is provided, and is applied to an FPGA in an LED control system, where the LED control system further includes: the method comprises the following steps that a memory flash and a receiving card are connected, wherein the memory flash is connected with the FPGA, and the FPGA is connected with the receiving card, and the method comprises the following steps:
loading an FPGA program, and reading a pre-cured type parameter in the flash memory, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA;
determining the type of the receiving card according to the type parameter;
and determining the output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode.
Optionally, the step of loading the FPGA program and reading the pre-cured type parameter in the memory flash includes:
loading an FPGA program to obtain a parameter initial address;
and reading data in the data stored in the flash memory according to the parameter initial address to obtain the pre-cured type parameter.
Optionally, the method further includes: presetting a corresponding relation between a parameter initial address and an initial address of a starting mode for loading the FPGA program;
and when the FPGA program is loaded, obtaining a corresponding parameter initial address according to the initial address corresponding relation.
Optionally, the memory flash includes: the method comprises a first storage area and a second storage area, wherein the first storage area and the second storage area are stored with pre-cured type parameters, and the step of reading the pre-cured type parameters in the memory flash comprises the following steps:
reading the pre-cured type parameters in the first storage area under the condition that the pre-cured type parameters exist in the first storage area;
and reading the pre-cured type parameters in the second storage area under the condition that the pre-cured type parameters do not exist in the first storage area.
In another aspect of the present invention, a device for enabling an FPGA to be compatible with multiple hardware is further provided, where the device is applied to an FPGA in an LED control system, and the LED control system further includes: memory flash and receiving card, wherein, memory flash with the FPGA is connected, FPGA with the receiving card is connected, the device includes:
the reading module is used for loading an FPGA program and reading a pre-cured type parameter in the flash memory, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA;
the determining module is connected with the reading module and used for determining the type of the receiving card according to the type parameter;
and the output module is connected with the determining module and used for determining the output mode of the receiving card according to the determined type of the receiving card and carrying out pin output according to the output mode.
Optionally, the reading module includes:
the loading unit is used for loading the FPGA program to obtain a parameter initial address;
and the first reading unit is connected with the loading unit and used for reading data in the data stored in the flash memory according to the parameter initial address to obtain the pre-cured type parameter.
Optionally, a corresponding relation between a parameter starting address and a starting address for loading the starting mode of the FPGA program is preset;
and the loading unit is also used for obtaining a corresponding parameter initial address according to the initial address corresponding relation when the FPGA program is loaded.
Optionally, the memory flash includes: the reading module comprises:
the second reading unit is used for reading the pre-cured type parameters in the first storage area under the condition that the pre-cured type parameters exist in the first storage area;
and the third reading unit is connected with the second reading unit and used for reading the pre-cured type parameters in the second storage area under the condition that the pre-cured type parameters do not exist in the first storage area.
In another aspect of the present invention, an electronic device is further provided, which includes a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing processor-executable instructions;
and the processor is used for realizing the method that the FPGA is compatible with various hardware when the processor executes the instructions stored in the memory.
According to the method, the device and the electronic equipment for enabling the FPGA to be compatible with various hardware, the type parameter pre-solidified in the flash memory is read by loading the FPGA program, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA; determining the type of the receiving card according to the type parameter; and determining the output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode. By applying the scheme provided by the invention, the specific type parameters are solidified in the flash, after the FPGA program is loaded, the type parameters are read back to judge the type of the receiving card, then the corresponding pin output is carried out, and the type of the receiving card is identified through the type parameters. After the type of the receiving card is replaced, only the type parameters solidified in the flash before the type parameters are erased, and then the type parameters corresponding to the type of the replaced receiving card are written in the flash, so that the multiple types of receiving cards can be switched randomly.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
fig. 1 is a schematic flowchart of a method for enabling an FPGA to be compatible with multiple hardware according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a device compatible with multiple hardware devices and provided by an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
Referring to fig. 1, a schematic flow chart of a method for enabling an FPGA to be compatible with multiple hardware according to an embodiment of the present invention is applied to an FPGA in an LED control system, where the LED control system further includes: the method comprises the following steps that a memory flash and a receiving card are connected, wherein the memory flash is connected with the FPGA, and the FPGA is connected with the receiving card, and the method comprises the following steps:
s100, loading an FPGA program, and reading the pre-cured type parameters in the flash memory.
The type parameter is used for determining the type of a receiving card connected with the FPGA.
An FPGA (Field Programmable Gate Array) is a product of further development based on Programmable devices such as PAL and GAL. The circuit is a semi-custom circuit in the field of application-specific integrated circuits, not only solves the defects of custom circuits, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The receiving card is used for receiving the data sent by the sending card, decoding the data and then providing the decoded data to the LED display screen for displaying.
In implementation, the type parameters may be stored in a storage space of the flash, and each type parameter corresponds to a type of the receiving card. For example, the type parameter may be represented as 000,001,002, which corresponds to the first type of receiving card, the second type of receiving card, and the third type of receiving card, respectively.
In implementation, in order to read the type parameter in the flash memory, the parameter start address of the type parameter may be annotated in a field in the FPGA program, for example, a corresponding relationship between the parameter start address and the start address of the starting mode for loading the FPGA program may be set, so that after the FPGA program is loaded, the corresponding parameter start address may be obtained according to the corresponding relationship between the start addresses, and then the data is read in the data stored in the flash memory according to the hint bits defined by the parameter start address.
And S110, determining the type of the receiving card according to the type parameter.
In practice, the types of receiving cards typically include: monochrome receiver cards, dual color receiver cards, and full color receiver cards.
And S120, determining the output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode.
In implementation, the output modes generally include: a monochrome output mode, a two-color output mode, and a full-color output mode. For example, a single-color indoor screen and a double-color indoor screen generally use 08 ports, and an outdoor screen uses 12 ports; the full-color indoor screen uses 74 mouths, and the full-color outdoor screen uses 75 mouths. Correspondingly, in the monochrome and two-color output mode, 08-port pin output is carried out indoors, and 12-port pin output is carried out outdoors; in the full-color output mode, 74-port pin output is performed indoors, and 75-port pin output is performed outdoors.
In implementation, a mapping relation among a type parameter, a receiving card type, an output mode and a pin output mode can be established in advance, after the type parameter is obtained, the type of the receiving card, the output mode corresponding to the receiving card and a pin required by the receiving card in normal work are obtained by searching the mapping relation, the corresponding pin output is activated to enable the receiving card to normally run, after the receiving card normally runs, the receiving card receives and analyzes video data sent by the sending card, and the analyzed video data is displayed through the LED box body; when the receiving card is damaged, the LED box body is blackened because the data sent by the sending card cannot be received. By means of the method for establishing the mapping relation in advance, after type parameters in the flash memory are read, pins required by the current receiving card when the receiving card works normally can be quickly determined and activated, and the receiving card can be quickly switched.
By applying the scheme provided by the invention, the specific type parameters are solidified in the flash, after the FPGA program is loaded, the type parameters are read back to judge the type of the receiving card, then the corresponding pin output is carried out, and the type of the receiving card is identified through the type parameters, so that the occupation of IO port resources is reduced. After the type of the receiving card is changed, only the type parameters solidified in the flash before the type parameters are erased, and then the type parameters corresponding to the type of the changed receiving card are written in the flash, so that the receiving cards of various types can be switched randomly.
Referring to fig. 2, a schematic structural diagram of an FPGA compatible with multiple hardware devices provided in an embodiment of the present invention is applied to an FPGA in an LED control system, where the LED control system further includes: memory flash and receiving card, wherein, memory flash with the FPGA is connected, FPGA with the receiving card is connected, the device includes:
a reading module 200, configured to load an FPGA program and read a pre-cured type parameter in the memory flash, where the type parameter is used to determine a type of the receiving card connected to the FPGA;
a determining module 210 connected to the reading module 200 for determining the type of the receiving card according to the type parameter;
an output module 220, connected to the determining module 210, for determining an output mode of the receiving card according to the determined type of the receiving card, and performing pin output according to the output mode.
Optionally, the reading module 200 includes:
the loading unit is used for loading the FPGA program to obtain a parameter initial address;
and the first reading unit is connected with the loading unit and used for reading data in the data stored in the flash memory according to the parameter initial address to obtain the pre-cured type parameters.
Optionally, a corresponding relation between a parameter starting address and a starting address for loading the starting mode of the FPGA program is preset;
and the loading unit is also used for obtaining a corresponding parameter initial address according to the initial address corresponding relation when the FPGA program is loaded.
Optionally, the memory flash includes: a first storage area and a second storage area, in which pre-cured type parameters are stored, wherein the reading module 200 includes:
the second reading unit is used for reading the pre-cured type parameters in the first storage area under the condition that the pre-cured type parameters exist in the first storage area;
and the third reading unit is connected with the second reading unit and used for reading the pre-cured type parameters in the second storage area under the condition that the pre-cured type parameters do not exist in the first storage area.
By applying the scheme provided by the invention, the specific type parameters are solidified in the flash, after the FPGA program is loaded, the type parameters are read back to judge the type of the receiving card, then the corresponding pin output is carried out, and the type of the receiving card is identified through the type parameters, so that the occupation of IO port resources is reduced. After the type of the receiving card is replaced, only the type parameters solidified in the flash before the type parameters are erased, and then the type parameters corresponding to the type of the replaced receiving card are written in the flash, so that the multiple types of receiving cards can be switched randomly.
An embodiment of the present invention further provides an electronic device, as shown in fig. 3, including a processor 001, a communication interface 002, a memory 003 and a communication bus 004, where the processor 001, the communication interface 002 and the memory 003 complete mutual communication through the communication bus 004,
a memory 003 for storing a computer program;
the processor 001 is configured to implement the method for the FPGA to be compatible with a plurality of hardware when executing the program stored in the memory 003, and is applied to the FPGA in the LED control system, where the LED control system further includes: the method comprises the following steps that a memory flash and a receiving card are connected, wherein the memory flash is connected with the FPGA, and the FPGA is connected with the receiving card, and the method comprises the following steps:
loading an FPGA program, and reading a pre-cured type parameter in the flash memory, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA;
determining the type of the receiving card according to the type parameter;
and determining the output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode.
By applying the scheme provided by the invention, the specific type parameters are solidified in the flash, after the FPGA program is loaded, the type parameters are read back to judge the type of the receiving card, then the corresponding pin output is carried out, and the type of the receiving card is identified through the type parameters, so that the occupation of IO port resources is reduced. After the type of the receiving card is changed, only the type parameters solidified in the flash before the type parameters are erased, and then the type parameters corresponding to the type of the changed receiving card are written in the flash, so that the receiving cards of various types can be switched randomly.
The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the embodiments of the apparatus and the electronic device, since they are substantially similar to the embodiments of the method, the description is simple, and the relevant points can be referred to only in the partial description of the embodiments of the method.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A method for making an FPGA compatible with various hardware is characterized in that the method is applied to the FPGA in an LED control system, and the LED control system also comprises: the method comprises the following steps that a memory flash and a receiving card are connected, wherein the memory flash is connected with the FPGA, and the FPGA is connected with the receiving card, and the method comprises the following steps:
loading an FPGA program, and reading a pre-cured type parameter in the flash memory, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA, and a preset corresponding relation exists between a parameter starting address of the type parameter and a starting address of an FPGA program starting mode;
determining the type of the receiving card according to the type parameter;
determining an output mode of the receiving card according to the determined type of the receiving card, and carrying out pin output according to the output mode;
wherein the memory flash includes: the method comprises a first storage area and a second storage area, wherein pre-cured type parameters are stored in the first storage area and the second storage area, and the step of reading the pre-cured type parameters in the memory flash comprises the following steps: reading the pre-cured type parameters in the first storage area under the condition that the pre-cured type parameters exist in the first storage area; and reading the pre-cured type parameters in the second storage area under the condition that the pre-cured type parameters do not exist in the first storage area.
2. The method of claim 1, wherein the step of loading the FPGA program and reading the pre-cured type parameters in the memory flash comprises:
loading an FPGA program to obtain a parameter initial address;
and reading data in the data stored in the flash memory according to the parameter initial address to obtain the pre-cured type parameter.
3. The method of claim 2, further comprising: presetting a corresponding relation between a parameter initial address and an initial address of a starting mode for loading the FPGA program;
and when the FPGA program is loaded, obtaining a corresponding parameter initial address according to the initial address corresponding relation.
4. The device for making the FPGA compatible with various hardware is characterized in that the device is applied to the FPGA in an LED control system, and the LED control system further comprises: memory flash and receiving card, wherein, memory flash with the FPGA is connected, FPGA with the receiving card is connected, the device includes:
the reading module is used for loading an FPGA program and reading a pre-solidified type parameter in the flash memory, wherein the type parameter is used for determining the type of the receiving card connected with the FPGA, and a preset corresponding relation exists between a parameter starting address of the type parameter and a starting address of an FPGA program starting mode;
the determining module is connected with the reading module and used for determining the type of the receiving card according to the type parameter;
the output module is connected with the determining module and used for determining the output mode of the receiving card according to the determined type of the receiving card and carrying out pin output according to the output mode;
wherein the memory flash includes: the reading module comprises: the second reading unit is used for reading the pre-cured type parameters in the first storage area under the condition that the pre-cured type parameters exist in the first storage area; and the third reading unit is connected with the second reading unit and used for reading the pre-cured type parameters in the second storage area under the condition that the pre-cured type parameters do not exist in the first storage area.
5. The apparatus of claim 4, wherein the read module comprises:
the loading unit is used for loading the FPGA program to obtain a parameter initial address;
and the first reading unit is connected with the loading unit and used for reading data in the data stored in the flash memory according to the parameter initial address to obtain the pre-cured type parameters.
6. The device of claim 4, wherein a corresponding relationship between a parameter start address and a start address for loading an FPGA program starting mode is preset;
and the loading unit is also used for obtaining a corresponding parameter initial address according to the initial address corresponding relation when the FPGA program is loaded.
7. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;
a memory for storing processor-executable instructions;
a processor adapted to perform the method steps of any of claims 1-3 when executing instructions stored in the memory.
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| CN104050067A (en) * | 2014-05-23 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Method and device for operation of FPGA (Field Programmable Gate Array) in MCU (Microprogrammed Control Unit) chip |
| CN109426625A (en) * | 2017-08-30 | 2019-03-05 | 深圳市道通科技股份有限公司 | A kind of control device and implementation method that more drivings are compatible |
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