CN111880690A

CN111880690A - Noise detection circuit, self-capacitance detection method, touch chip and electronic equipment

Info

Publication number: CN111880690A
Application number: CN202010785296.8A
Authority: CN
Inventors: 唐智; 蒋宏; 陈哲
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2020-08-06
Filing date: 2020-08-06
Publication date: 2020-11-03

Abstract

A noise detection circuit, comprising: the control module is used for controlling the driving module to charge the capacitor to be detected by using the first voltage in a first period, and controlling the counteracting module to charge the counteracting capacitor by using the first voltage in the first period or to connect two ends of the counteracting capacitor with the first voltage; the control module controls the offset module to enable the first end of the capacitor to be detected to be connected with the first end of the offset capacitor in the second time period; the control module controls the charge transfer module to convert the charges of the capacitor to be detected and the offset capacitor in a third time period to generate output voltage; the first period, the second period, and the third period are consecutive in time, the charge transfer module includes an amplifier; the inverting input end of the amplifier is connected with the first voltage; the processing module is used for determining the size of the noise at least according to the output voltage. The capacitance detection circuit improves the accuracy of noise detection.

Description

Noise detection circuit, self-capacitance detection method, touch chip and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of touch control, in particular to a noise detection circuit, a self-capacitance detection method, a touch control chip, a capacitive touch control system and an electronic device.

Background

The principle of self-capacitance detection is that a capacitance formed between a detection electrode and a system ground is called self-capacitance detection or self-capacitance detection, and when no object such as a finger approaches or touches the electrode to cause an external electric field, a capacitance is also formed between the detection electrode and the system ground, and the capacitance has a basic capacitance or an initial capacitance. When a finger approaches or touches the detection electrode, the capacitance between the detection electrode and the system ground becomes large, and the relevant touch operation of the user can be judged by detecting the variation of the capacitance. In practical use, the capacitance detection system is subject to various interferences, which mainly include power supply noise, common mode interference, digital signal interference, and other space coupling interference. When the self-capacitance detection is interfered, the accuracy of the self-capacitance detection is greatly reduced, and therefore, various measures need to be taken to reduce the noise interference according to the noise characteristics, for example, the working frequency of the self-capacitance detection is replaced. Therefore, how to accurately detect the noise is very important. The common method for detecting noise in the prior art is to count the jitter values of multi-frame data of a self-contained detection circuit under various driving frequencies, determine the noise under the driving frequency according to the jitter values, and when the jitter values are small, the noise is small, and when the jitter values are large, the noise is large. This method requires statistics of jitter values, which takes a long time, and also, for noise interference, the phase of noise is often unpredictable, so that the noise characteristics cannot be accurately represented by merely judging the noise level from the jitter values.

Disclosure of Invention

The embodiment of the application provides a noise detection circuit, a self-capacitance detection method, a touch chip, a capacitance touch system and an electronic device, aiming at the problem of low noise measurement accuracy in the prior art.

A first aspect of embodiments of the present application provides a noise detection circuit, comprising: the device comprises a control module, a driving module, a counteracting module, a charge transfer module and a processing module; the driving module is connected with the counteracting module, the counteracting module is connected with the charge transfer module, the charge transfer module is connected with the processing module, and the control module is connected with the driving module, the counteracting module and the charge transfer module;

the control module is used for controlling the driving module to charge the capacitor to be detected by using the first voltage in a first period, and controlling the counteracting module to charge the counteracting capacitor by using the first voltage in the first period or to connect two ends of the counteracting capacitor with the first voltage;

the control module controls the offset module to enable the first end of the capacitor to be detected to be connected with the first end of the offset capacitor in the second time period;

the control module controls the charge transfer module to convert the charges of the capacitor to be detected and the offset capacitor in a third time period to generate output voltage;

the first period, the second period, and the third period are consecutive in time, the charge transfer module includes an amplifier; the inverting input end of the amplifier is connected with the first voltage;

the processing module is used for determining the size of the noise at least according to the output voltage.

In a possible implementation form according to the first aspect, the first voltage is a common mode voltage.

According to the first aspect, in a possible implementation manner, the driving module includes a first switch unit, and the control module is further configured to control the first switch unit to be in a closed state, so that the driving module charges the capacitor to be tested by using a first voltage in a first period;

when the first switch unit is in a closed state, the first end of the capacitor to be tested is connected with a first voltage; and the second end of the capacitor to be tested is connected with the ground voltage.

According to the first aspect, in a possible implementation manner, the cancellation module includes a second switch unit and a cancellation capacitor, and the control module is further configured to control the second switch unit to be in a closed state at a first period;

when the second switch unit is in a closed state, the cancellation capacitor is charged, a first end of the cancellation capacitor is connected with a first voltage, and a second end of the cancellation capacitor is connected with a ground voltage; alternatively, the first and second electrodes may be,

when the second switch unit is in a closed state, the first end of the offset capacitor is connected with the first voltage, and the second end of the offset capacitor is connected with the first voltage.

According to the first aspect, in a possible implementation manner, the cancellation module further includes a third switching unit, and the control module is further configured to control the third switching unit to be in a closed state in a second period of time so that the first end of the capacitor to be measured is connected to the first end of the cancellation capacitor;

when the third switching unit is in a closed state, the first end of the offset capacitor is disconnected from the first voltage, and the first end of the capacitor to be tested is disconnected from the first voltage.

According to the first aspect, in a possible implementation manner, when the charges of the capacitor to be measured and the cancellation capacitor are converted, the first end of the capacitor to be measured, the first end of the cancellation capacitor, and the non-inverting input terminal of the amplifier are connected.

According to the first aspect, in one possible implementation, the control module controls the charge transfer module such that the charge transfer module is reset during a fourth period; the first period, the second period, the third period, and the fourth period are consecutive in time.

According to the first aspect, in a possible implementation manner, the charge transfer module further includes a fourth switching unit, and the fourth switching unit is in a closed state in a third time period so as to convert charges of the capacitor to be measured and the cancellation capacitor to generate an output voltage; the fourth switching unit is in an off state at a fourth period to reset the charge transfer module.

According to the first aspect, in a possible implementation manner, in a first time period, the voltage of the capacitor to be measured is increased to a first voltage, the voltage of the cancellation capacitor is increased to the first voltage, or the voltage of the cancellation capacitor is 0; in a second period, the connection state of the second end of the offset capacitor is the same as that of the second end of the offset capacitor in the first period; the output voltage of the charge transfer module increases or decreases to 0 during the first and second periods, and decreases or increases to 0 during the fourth period.

According to a first aspect, in one possible implementation, a processing module comprises a filter, an analog-to-digital converter, and a digital signal processor; the filter filters the output voltage of the charge transfer module; the analog-to-digital converter performs analog-to-digital conversion on the filtered output voltage; the digital signal processor is used for demodulating the output voltage after the analog-to-digital conversion, and the reference frequency used for demodulation is the reciprocal of the noise detection period; the noise detection period is equal to integral multiple of the noise detection half period, and the noise detection half period is the sum of the first time interval, the second time interval, the third time interval and the fourth time interval; or the noise detection half period is the sum of the first period, the second period and the third period.

According to the first aspect, in one possible implementation manner, the determining, by the processing module, the magnitude of the noise according to at least the output voltage includes: the processing module determines the amplitude of the noise according to the output voltage of the charge transfer module in the noise detection period.

According to the first aspect, in one possible implementation, the driving module includes a thirteenth switching unit, a fourteenth switching unit, and a nineteenth switching unit; the control module is also used for controlling the thirteenth switching unit, the fourteenth switching unit and the nineteenth switching unit to carry out noise detection or self-capacitance detection; when the noise detection is carried out, the control module is used for controlling the nineteenth switch unit so that the first end of the capacitor to be detected is connected with the first voltage in the first period; when the self-capacitance detection is carried out, the control module is used for controlling the thirteenth switch unit and the fourteenth switch unit so that the first end of the capacitor to be detected is connected with the ground voltage or the power supply voltage; and the second end of the capacitor to be tested is connected with the ground voltage.

According to the first aspect, in one possible implementation manner, the cancellation module includes a fifteenth switching unit, a sixteenth switching unit, a twentieth switching unit, a seventeenth switching unit, an eighteenth switching unit, and a twenty-first switching unit; the control module is also used for controlling a fifteenth switching unit, a sixteenth switching unit, a twentieth switching unit, a seventeenth switching unit, an eighteenth switching unit and a twenty-first switching unit to carry out noise detection or self-capacitance detection; when the noise detection is carried out, the control module is used for controlling the twentieth switching unit and the twenty-first switching unit to enable the first end and the second end of the cancellation capacitor to be connected with a first voltage in a first period, or to enable the first end of the cancellation capacitor to be connected with the first voltage and the second end of the cancellation capacitor to be connected with a ground voltage in the first period; when the self-capacitance detection is carried out, the control module is used for controlling the fifteenth switching unit, the sixteenth switching unit, the seventeenth switching unit and the eighteenth switching unit so that the first end and the second end of the offset capacitor are connected with the ground voltage or the power supply voltage.

According to the first aspect, in a possible implementation manner, the cancellation module further includes a fifth switch unit, and the control module is further configured to control the fifth switch unit so that the first end of the capacitor to be measured is connected to the first end of the cancellation capacitor in the second period and the third period, and the first end of the capacitor to be measured is disconnected from the first end of the cancellation capacitor in the first period.

According to the first aspect, in a possible implementation manner, the device further includes a power supply switching module, the power supply switching module is connected to the control module, the driving module and the cancellation module, the power supply switching module is configured to switch the first voltage, so that the control module controls the driving module, the cancellation module, the charge transfer module and the processing module to perform self-capacitance detection or noise detection, and when the self-capacitance detection is performed, the control module is further configured to control the cancellation capacitor to perform charge cancellation processing on the capacitor to be detected.

According to the first aspect, in a possible implementation manner, when performing self-capacitance detection, the power supply switching module is configured to switch two first voltages connected to a first end of a capacitor to be detected to a power supply voltage and a ground voltage, respectively; the power supply switching module is also used for switching two first voltages connected with the first end of the offset capacitor into a power supply voltage and a ground voltage respectively; the power supply switching module is further used for switching the two first voltages connected with the second end of the cancellation capacitor into a power supply voltage and a ground voltage respectively.

According to the first aspect, in a possible implementation manner, when performing noise detection, the power supply switching module is configured to switch a power supply voltage and a ground voltage connected to a first end of a capacitor to be detected to a first voltage; the power supply switching module is also used for switching the power supply voltage and the ground voltage which are connected with the first end of the offset capacitor into a first voltage; the power supply switching module is further used for switching the power supply voltage and the ground voltage connected with the second end of the cancellation capacitor into a first voltage.

According to the first aspect, in one possible implementation, the driving module, the cancelling module and the charge transfer module each comprise at least one switching unit; when noise detection is carried out, the time sequence of the switch units of the driving module, the counteracting module and the charge transfer module is the same as that of the switch units of the driving module, the counteracting module and the charge transfer module when self-capacitance detection is carried out.

In a possible implementation form according to the first aspect, the amplifier is a single-ended amplifier.

In a possible implementation form according to the first aspect, the amplifier is a fully differential amplifier.

A second aspect of an embodiment of the present application provides a self-contained detection method, including: detecting an amplitude of noise of a noise detection circuit operating at a first frequency using the noise detection circuit as described above in relation to the first aspect; if the amplitude of the noise is lower than a preset noise threshold value, the self-capacitance detection circuit performs capacitance detection at a first frequency.

According to the second aspect, in one possible implementation, the period of the self-capacitance detection is equal to the reciprocal of the first frequency, the self-capacitance detection circuit performs the capacitance detection at the first frequency, and the period of the self-capacitance detection is equal to the noise detection period.

In a possible implementation form according to the first aspect, the noise detection period is equal to an integer multiple of a noise detection half period, the noise detection half period being a sum of the first time period, the second time period, the third time period and the fourth time period.

In a possible implementation form according to the first aspect, the noise detection period is twice the noise detection half period.

In a possible implementation form of the first aspect, when the self-capacitance detection circuit operates at the first frequency, the processing module performs demodulation at the first frequency to obtain the self-capacitance value.

According to the first aspect, in a possible implementation manner, during self-capacitance detection, in a ninth time period, a capacitor to be detected and a cancellation capacitor are charged, and in a tenth time period, the capacitor to be detected and the cancellation capacitor are subjected to charge cancellation; in the eleventh time period, the charges of the capacitor to be measured and the counteracting capacitor are subjected to charge transfer; in a twelfth period, the charge transfer module is reset; in the thirteenth time period, discharging the capacitor to be detected and charging the cancellation capacitor; in a fourteenth time period, carrying out charge cancellation on the capacitor to be detected and the cancellation capacitor; in a fifteenth time period, carrying out charge transfer on the charges of the capacitor to be measured and the offset capacitor; in a sixteenth period, the charge transfer module is reset; the lengths of the ninth period, the tenth period, the eleventh period and the twelfth period are respectively equal to the lengths of the thirteenth period, the fourteenth period, the fifteenth period and the sixteenth period; the lengths of the ninth, tenth, eleventh, and twelfth periods are equal to the lengths of the first, second, third, and fourth periods, respectively.

A third aspect of embodiments of the present application provides a touch chip including the noise detection circuit as described in the first aspect.

A fourth aspect of embodiments of the present application provides a capacitive touch system, including the touch chip and the touch sensor as described in the third aspect above.

A fifth aspect of embodiments of the present application provides an electronic device, which is characterized by the touch chip as described in the third aspect above.

The embodiment of the application provides a noise detection circuit, a self-capacitance detection method, a touch chip, a capacitive touch system and an electronic device, wherein a capacitor to be detected is charged by a first voltage in a first period, and the offset capacitor is charged with the first voltage or both ends of the offset capacitor are connected with the first voltage, in the second time interval, the first end of the capacitor to be measured is connected with the first end of the offset capacitor, in the third time interval, the charge transfer module converts the charges of the capacitor to be measured and the offset capacitor to generate output voltage, the processing module determines the noise according to the output voltage at least, in addition, the inverting input end of the amplifier is connected with the first voltage, so that when noise is detected, the charge change of the capacitor to be detected and the counteracting capacitor can accurately reflect the size of the noise, and the noise can be detected more accurately.

Drawings

Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:

fig. 1A is a schematic structural diagram of a noise detection circuit according to an embodiment of the present disclosure;

fig. 1B is a schematic structural diagram of another noise detection circuit provided in the embodiment of the present application;

fig. 1C is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 1D is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 2A is a timing diagram of the noise detection circuit in fig. 1A, 1B, 1C, and 1D according to an embodiment of the present disclosure;

fig. 2B is a timing diagram of the noise detection circuit shown in fig. 1A, 1B, 1C, and 1D according to an embodiment of the present disclosure;

FIG. 2C is a waveform diagram of Vx and Vout in the noise detection circuit obtained by simulation according to the embodiment of the present application;

fig. 3 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram of the operation of the noise detection circuit of FIG. 3 according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a self-capacitance detection circuit according to an embodiment of the present application;

fig. 7 is a timing diagram of the self-capacitance detection circuit of fig. 6 in operation according to the embodiment of the present application, and is also a timing diagram of the noise detection circuit of fig. 8 in operation;

fig. 8 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present application;

fig. 10 is a noise frequency response diagram obtained by simulation when the self-capacitance detection circuit operates according to the embodiment of the present application and a noise frequency response diagram detected by the noise detection circuit;

fig. 11 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

FIG. 12 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 11 according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of another self-capacitance detection circuit provided in the embodiment of the present application;

fig. 14 is a timing diagram of the self-capacitance detection circuit of fig. 13 according to an embodiment of the present disclosure;

fig. 15A is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 15B is a schematic structural diagram of another noise detection circuit according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present application;

FIG. 17 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 16 according to an embodiment of the present application;

fig. 18 is a schematic structural diagram of another noise detection circuit according to an embodiment of the present application;

FIG. 19 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 18 according to an embodiment of the present application;

fig. 20 is a flowchart of a self-contained detection method according to an embodiment of the present application;

FIG. 21 is a flowchart of another self-contained test method provided in the embodiments of the present application;

FIG. 22 is a flowchart of a self-contained test method according to an embodiment of the present application;

FIG. 23 is a flowchart of another self-contained test method according to an embodiment of the present application;

fig. 24 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of another capacitive touch system according to an embodiment of the present application.

Detailed Description

It is not necessary for any particular embodiment of the invention to achieve all of the above advantages at the same time.

In the technical solution provided in the embodiment of the present application, the noise detection circuit includes: the device comprises a control module, a driving module, a counteracting module, a charge transfer module and a processing module, wherein the driving module is connected with the counteracting module, the counteracting module is connected with the charge transfer module, the charge transfer module is connected with the processing module, the control module is connected with the driving module, the counteracting module and the charge transfer module, the control module is used for charging a capacitor to be tested by controlling the driving module at a first time interval with a first voltage, and the control module is used for controlling the counteracting module so that the counteracting capacitor is charged by the first voltage at the first time interval or both ends of the counteracting capacitor are connected with the first voltage; the control module is also used for controlling the counteracting module to enable the first end of the capacitor to be detected to be connected with the first end of the counteracting capacitor in the second time period;

the control module is also used for controlling the charge transfer module to convert the charges of the capacitor to be detected and the offset capacitor in a third time period to generate an output voltage; the processing module is used for determining the size of the noise according to the output voltage. The charge transfer module comprises an amplifier; the inverting input end of the amplifier is connected with the first voltage; the first time interval, the second time interval and the third time interval are continuous in time; in this embodiment, the capacitance to be detected and the cancellation capacitance are processed by using the first voltage, so that before the charge transfer module transfers the charges of the cancellation capacitance and the capacitance to be detected, the voltage of the connection point of the cancellation capacitance and the capacitance to be detected is equal to the first voltage connected to the inverting input terminal of the amplifier, so as to accurately detect the noise.

The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.

As shown in fig. 1A, the noise detection circuit includes a control module 100, a driving module 102, a cancellation module 103, a charge transfer module 104, and a processing module 105. The control module 100 may be configured to perform charging processing on the capacitance Cx to be detected by controlling the driving module 102 with the first voltage Vmm, and perform charging processing on the cancellation capacitance Cc by controlling the cancellation module 103 with the first voltage Vmm, and in addition, the control module 100 may be configured to control the cancellation module 103 such that the first end of the cancellation capacitance Cc is connected to the first end of the capacitance Cx to be detected, and the second end of the capacitance Cx to be detected is grounded and the second end of the cancellation capacitance Cc is grounded. In this embodiment, the cancellation module 103 may also be referred to as a compensation module, because some basic capacitances exist in the capacitor itself during the self-capacitance detection, so that charge cancellation is performed between the cancellation capacitor and charges stored in the capacitor to be detected to cancel the basic capacitances, there is a cancellation capacitor during the self-capacitance detection, and in this embodiment, the capacitor Cc may also be used as a cancellation capacitor in the self-capacitance detection circuit, so the capacitor Cc may be referred to as a cancellation capacitor here, and the module 103 may be referred to as a cancellation module. The charge transfer module 104 may be configured to convert charges of the capacitance Cx to be measured and the offset capacitance Cc to generate an output voltage Vout; the processing module 105 may be configured to determine noise affecting the capacitor under test from the output voltage Vout.

The control module 100 is respectively connected with the driving module 102, the counteracting module 103 and the charge transfer module 104, the driving module 102 is connected with the counteracting module 103, the counteracting module 103 is connected with the charge transfer module 104, and the processing module 105 is connected with the charge transfer module 104. The control module 100 may include a programmable sequential logic circuit for controlling the on/off of the switching unit of the noise detection circuit.

As shown in FIG. 1A, the driving module 102 includes a first switching unit K₁(in the case of a single switch implementation), the control module 102 is further configured to control the first switch unit K₁In a closed state, the driving module 102 charges the capacitor Cx to be measured with the first voltage Vmm for a first period of time. Further, a first switching unit K₁When the capacitor is in a closed state, the first end of the capacitor Cx to be measured is electrically connected with the first endAnd a voltage Vmm, wherein the second end is electrically connected to GND, and the voltage value of the first voltage Vmm is higher than GND. It is understood that the first voltage Vmm is set in the operating voltage range of the charge transfer module, which is illustrated as GND to Vcc in the present embodiment, and therefore, the first voltage Vmm may be set to be greater than GND and less than Vcc. If the operating voltage of the charge transfer module is in the range of (-Vcc) to Vcc, the first voltage Vmm may be set to be greater than-Vcc and less than Vcc.

As shown in fig. 1A, the cancellation module 103 includes a second switch unit K₂(taking a single switch implementation as an example) and a third switching unit K₃(in the example of a single switch implementation), a second switching unit K₂And a third switching unit K₃May be in different closed states. In particular, the control module 100 may be used to control the second switching unit K₂In a closed state and the third switching unit K₃In an off state so that the cancellation capacitor is charged with the first voltage for a first period. The control module 100 may be configured to control the second switching unit K₂Is in an off state and the third switching unit K₃In the closed state. In particular, the second switching unit K₂Is in an off state and the third switching unit K₃In a closed state, so that the first end of the offset capacitance Cc is connected to the first end of the capacitance Cx to be measured during the third period. The second end of the cancellation capacitor Cc and the second end of the capacitor Cx to be measured are both grounded, and this embodiment is described by grounding the second end of the cancellation capacitor Cc, it should be noted that in this embodiment, the second end of the cancellation capacitor Cc may also be connected to the first voltage Vmm.

Further, assuming that the interference source 101 is shown in fig. 1, it should be noted that the interference source 101 is only illustrated for simulating interference and is only illustrated for facilitating understanding, for example, the interference source is represented by a voltage source and a coupling capacitor Cn in series, and the interference couples noise into the circuit through the coupling capacitor Cn, it is understood that the interference source includes at least one noise source, and the interference source may also be represented in other forms, for exampleFor example, the voltage source may be used as a noise source, and the current source may also be used as a noise source, which is not limited in this embodiment. The control module 100 controls the second switching unit K₂In an off state and the third switching unit K₃And when the interference exists, although the voltage of the capacitance Cx to be measured at the end moment of the first time interval is Vmm, the voltage Vx of the connection point of the offset capacitance Cc and the capacitance Cx to be measured changes in the second time interval due to the influence of noise, the offset capacitance Cc and the capacitance Cx to be measured are charged or discharged at the same time in the second time interval, and therefore, when the noise exists, the voltage Vx of the connection point of the offset capacitance Cc and the capacitance Cx to be measured is not Vmm.

As shown in fig. 1A, a fourth switch unit K is disposed between the charge transfer module 104 unit and the cancellation module 103₄(taking a single switch implementation as an example), correspondingly, the control module 100 further controls the fourth switch unit K₄And in a closed state, the charge transfer module 104 is electrically connected with the capacitance Cx to be measured and the offset capacitance Cc, so as to convert the charges of the capacitance Cx to be measured and the offset capacitance Cc to generate the output voltage Vout.

In this embodiment, the charge transfer module 104 is illustrated by taking a fully differential amplifier as an example, and further, the non-inverting input terminal of the fully differential amplifier may be connected to the fourth switch K₄Electrically connected, the inverting input of the fully differential amplifier is connected to a first voltage Vmm. In the fully differential amplifier, feedback resistors R are arranged between a non-inverting input end and an inverting output end and between the inverting input end and the non-inverting output end_fAnd a feedback capacitor C_f. The feedback resistor R_fAnd a feedback capacitor C_fAre connected in parallel. In this embodiment, the non-inverting input terminal may also be referred to as a non-inverting input terminal, and the inverting input terminal may also be referred to as a inverting input terminal. Referring to fig. 1A, the inverting output of the Fully Differential Amplifier (full Differential Amplifier) is marked with a circle, and the non-inverting output of the Fully Differential Amplifier is not marked with a circle. A single-ended amplifier may also be used in place of the fully differential amplifier in this embodiment.

In this embodiment, the first switch unit K₁A second switch unit K₂A third switching unit K3, a fourth switching unit K₄The single pole single throw switch is taken as an example for explanation. The state of the switch is shown in fig. 2A, a high level indicates that the switch is closed, and a low level indicates that the switch is opened (off), which will be further described with reference to the state of the switch in fig. 2A.

FIG. 2A is a timing diagram illustrating the operation of the noise detection circuit of FIG. 1A according to an embodiment of the present disclosure; for convenience of illustration, use phi₁、φ₂、φ₃Can indicate the state of the switch, in particular phi₁Denotes a first switching unit K₁And a second switching unit K₂State of (c), phi₂Denotes a third switching unit K₃State of (c), phi₃Denotes a fourth switching unit K₄The state of (1). the time period t1-t4 constitutes the control signal phi₁、φ₂、φ₃The period of (c), t1+ t2+ t3+ t4, may be understood as a noise detection half period. In the following, two noise detection half cycles are taken as an example, and the main technical processes in each time period are briefly described as follows:

period t 1: charging the capacitor Cx to be measured and the offset capacitor Cc by using a first voltage Vmm;

period t 2: the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc, the first end of the capacitor to be measured is disconnected with the first voltage Vmm, and the first end of the offset capacitor is disconnected with the terminal Vmm;

period t 3: performing charge transfer, and converting the charges of the capacitor Cx to be measured and the offset capacitor Cc into voltage signals;

period t 4: the fully differential amplifier is reset.

Period t 5: charging the capacitor Cx to be measured and the offset capacitor Cc by using a first voltage Vmm;

period t 6: the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc, the first end of the capacitor to be measured is disconnected with the first voltage Vmm, and the first end of the offset capacitor is disconnected with the terminal Vmm;

period t 7: performing charge transfer, and converting the charges of the capacitor Cx to be measured and the offset capacitor Cc into voltage signals;

period t 8: the fully differential amplifier is reset.

It is understood that the operations of the first to fourth periods (t1-t4) are completely repeated for the fifth to eighth periods (t5-t 8). The first period to the fourth period may be referred to as a noise detection half period, and after sampling the output voltage of the noise detection half period, the magnitude of the noise may be determined according to the output voltage of the noise detection half period. The noise detection circuit carries out noise detection according to the noise detection method in the time period from t1 to t8, and the detected noise is more accurate.

A first period (t1), a first switching unit K₁A second switch unit K₂Conducting (i.e. in a closed state), the third switching unit K₃The fourth switching unit K4 is disconnected, the first ends of the capacitor Cx to be measured and the offset capacitor Cc are connected with the first voltage Vmm, the second end of the capacitor Cx to be measured and the second end of the offset capacitor Cc are connected with GND, the capacitor Cx to be measured and the offset capacitor Cc are charged simultaneously, and external interference cannot inject charges caused by noise into the capacitor to be measured or the offset capacitor. At the end of the time period t1, the voltage of the capacitor Cx to be measured is Vmm, and the voltage of the offset capacitor Cc is Vmm. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the charge amount Q1 stored in the capacitor Cx to be measured is Vmm Cx, and the charge amount Q2 stored in the offset capacitor Cc is Vmm Cc.

Second period (t2), first switch unit K₁A second switch unit K₂Off, third switching unit K₃And when the fourth switching unit K4 is closed, the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc, and the second end of the capacitor Cx to be measured and the second end of the offset capacitor Cc are both grounded. When no noise exists (under an ideal condition), Vmm x Cx + Vmm Cc ═ Vx Cx + (Vx-0) × Cc is established according to the charge conservation law, and the voltage Vx of the capacitor Cx to be measured is Vmm; if noise exists, the charges stored in the capacitor Cx to be tested and the offset capacitor Cc are changed, the capacitor Cx to be tested and the offset capacitor Cc are charged or discharged simultaneously, the voltage Vx of the capacitor Cx to be tested is not equal to Vmm, for example, Vx>Vmm or Vx<Vmm are provided. At the second placeDuring the time period, the interference source can inject charges caused by noise into the capacitance to be measured and the cancellation capacitance.

Third period (t3), first switch unit K₁A second switch unit K₂Off, third switching unit K₃Closed, fourth switching unit K₄And (5) closing. I.e. it can be understood that the other switches remain in the same state as the second period, except for the fourth switching unit K₄And (5) closing. In the third time period, the charges stored in the capacitance to be measured and the offset capacitance in the second time period can be transferred to the charge transfer module, and meanwhile, noise can affect the charge transfer module through Cn. According to the voltage Vx of the capacitor Cx to be measured at the end time of t2, the following conditions exist:

and if Vx is greater than Vmm, transferring the charge to the charge transfer module by the capacitor Cx to be measured and the offset capacitor Cc at the same time until the voltage Vx of the capacitor Cx to be measured reaches Vmm.

If Vx is Vmm, there is no process of transferring the charge to the charge transfer module by the capacitance to be measured Cx and the offset capacitance Cc, which indicates that the circuit is not affected by noise at this time.

If Vx<Vmm, the charge transfer module will pass through the feedback network (R)_fAnd C_fComposition) charges the capacitance Cx to be measured and the offset capacitance Cc until the voltages of the capacitance Cx to be measured and the offset capacitance Cc both reach Vmm. In this embodiment, the charge transfer module includes a feedback network, and the feedback form of the feedback network includes, but is not limited to, resistive feedback, resistive-capacitive feedback, or pure-capacitive feedback.

In the third period (t3), the frequency, amplitude, and phase of the interference source all affect the polarity and magnitude of the output voltage Vout of the charge transfer module. Therefore, the output voltage of the charge transfer module is determined by the charges stored in the capacitance Cx to be measured and the cancellation capacitance Cc at time t2, and the charges directly entering the charge transfer module from the interference source during time t 3. It is understood that the greater the noise, the greater the output voltage of the charge transfer module, and if no noise is present, the output voltage of the charge transfer module is 0.

According to the output voltage of the charge transfer module in the period t3, whether the circuit is disturbed or not can be judged. If Vout is 0, it indicates that the circuit is not affected by noise. If Vout ≠ 0, it indicates that the circuit is affected by noise and disturbed. In the present embodiment, the first period, the second period, and the third period are continuous in time.

During a fourth time period (t4), the control module controls the charge transfer module such that the charge transfer module is reset during the fourth time period; fourth switch unit K₄The disconnection resets the amplifier in the charge transfer module, outputting the voltage V_outBecomes 0. In addition, it should be noted that there may be no t4 period, i.e., the t4 stage may be omitted. When the t4 stage is set, the fourth switching unit and the first switching unit K in the charge transfer module 104 may be lowered₁Or a second switching unit K₂At the same time, the dead time t4 may be increased to avoid the fourth switching unit and the first switching unit K in the charge transfer module 104₁Or a second switching unit K₂And meanwhile, the amplifier is conducted, so that the amplifier can work normally to the maximum extent. It is understood that if the fourth period is omitted, the eighth period is correspondingly omitted, the first period to the third period may be referred to as a noise detection half period, and after the output voltage of the noise detection half period is sampled, the magnitude of the noise may be determined according to the output voltage of the noise detection half period. The fifth period to the seventh period (t5-t7) completely repeat the operations of the first period to the third period (t1-t3), and the noise may be determined according to the output voltages of the two noise detection half periods after sampling the two noise detection half periods, that is, the noise may be determined according to the output voltages of the t1+ t2+ t3+ t5+ t6+ t 7. In the present embodiment, the first period, the second period, the third period, and the fourth period are consecutive in time.

During a period t4, the fourth switching unit K₄And when the switch is opened, other switches can be in any states. Other switches may also remain in the same state as at time t 3. In particular, the first switching unit K₁A second switch unit K₂And a third switching unit K₃May be in an off state. In addition, for the t4 period, the third billing unit K₃It is also possible to have the first switching unit K in the closed phase, i.e. in the phase t4, as shown in fig. 2B₁The first stepTwo switch units K₂In the off state, the third switching unit K₃In the closed state, the fourth switching unit K₄And (5) disconnecting. Fourth switch unit K₄The disconnection resets the amplifier in the charge transfer module and the output voltage Vout becomes 0.

As can be seen from the above, in the absence of noise, the voltages of the capacitance to be measured Cx and the offset capacitance Cc at the end of the t2 time period or at the end of the t3 time period are determined to be V_mmIn the presence of noise, the voltages of the capacitance to be measured Cx and the compensation capacitance Cc at the end of the period t2 are not V_mmIn the period t3, charges are transferred, that is, charges are transferred from the capacitor to be detected and the cancellation capacitor to the charge transfer module, and the amount of noise affects the amount of transferred charges, so that the noise detection circuit can accurately measure the noise affecting the capacitor to be detected, so as to adjust the self-capacitance detection scheme, and improve the self-capacitance detection scheme or further correct the self-capacitance detection result according to the detected noise affecting the capacitor to be detected.

In addition, the embodiment provides a method for detecting noise, wherein the noise detection result is not influenced by the approach or touch of a finger, and the noise can be accurately detected even in the case of the touch of the finger. Specifically, if a finger touches the electrode, it can be understood that there is a finger capacitance Ct connected in parallel with the capacitance Cx to be measured, and in the first period, the charge amount Q1 stored in the capacitance Cx to be measured is Vmm × Cx, the charge amount Q2 stored in the offset capacitance Cc is Vmm × Cc, and the charge amount Q3 stored in the finger capacitance Ct is Vmm × Ct. In the second period, assuming that there is no noise, according to the charge conservation law, Vmm × Cx + Vmm × Cc + Vmm × Ct is true to Vx (Cx + Ct) + (Vx-0) × Cc, and the voltage Vx of the capacitor Cx to be measured is Vmm, then in the third period, the output voltage of the charge transfer module is 0, that is, when there is no noise, there is a finger touch or no finger touch, and the output voltage of the charge transfer module is 0. In addition, when noise exists, the voltage of the connection point of the offset capacitor and the capacitor to be measured is still Vx1 in the second time period on the assumption that a finger touches the noise, the amount of electric charge for which the conversion process generates the output voltage in the third period is Qx1 ═ (Vx1-Vmm) × (Cx + Cc + Ct), for the self-capacitance detection, assuming that there is noise and there is a finger touch, in the eleventh period of the self-capacitance detection, the amount of electric charge converted by the disturbance to generate the output voltage is Qx2 ═ (Vx2-Vmm) × (Cx + Cc + Ct), when the interference source is the same, Vx1 is Vx2, and therefore, the result of detecting noise by the noise detection circuit of the present embodiment can be free from the influence of the approach of a finger or the touch, and the noise detection circuit can accurately test the magnitude of interference received by the self-capacitance detection circuit regardless of the touch of the finger, thereby confirming whether the self-capacitance detection is to be performed by the self-capacitance detection circuit.

In addition, the circuit shown in fig. 1A may also be used for self-capacitance detection, specifically, when the circuit shown in fig. 1A is used for self-capacitance detection, the first voltage connected to the first switch unit is switched to the power supply voltage Vcc, the first voltage connected to the second switch unit is switched to GND, the capacitor to be measured and the offset capacitor have the same size, and when the circuit shown in fig. 1A is used as a self-capacitance detection circuit, the timings of all the switch units are the same as the timing of the noise detection circuit, that is, the self-capacitance detection may also be performed with reference to the timing shown in fig. 2A.

Based on the disclosure of the foregoing embodiments, in this embodiment, during noise detection, a common mode voltage may be used to process a capacitance to be detected and a cancellation capacitance, taking the self-capacitance detection circuit shown in fig. 6 as an example, during self-capacitance detection, a negative phase input terminal of an amplifier in the charge transfer module 603 is connected to the common mode voltage, so if during noise detection, the negative phase input terminal of the amplifier in the charge transfer module 104 may also be connected to the common mode voltage, there is no need to add an additional switch to switch the common mode voltage and the first voltage, that is, during noise detection and self-capacitance detection, the negative phase input terminal of the amplifier is connected to the common mode voltage, and when the first voltage is the common mode voltage, the noise detection and the self-capacitance detection have substantially the same circuit dynamic range. In addition, because common-mode voltage is arranged in a common circuit, the common-mode voltage is used for processing the capacitance to be measured and the offset capacitance, and other first voltages are avoided, so that power management is simplified.

In this embodiment, as shown in fig. 1B, the first voltage Vmm may be a common mode voltage Vcm, Vcc being a positive power supply voltage, and the common mode voltage being half of Vcc, which may also be referred to as a common mode operating voltage. It can be understood that, during the self-capacitance detection, the inverting input terminal of the amplifier of the charge transfer module 104 is connected to the common mode voltage, therefore, in this embodiment, when the first voltage is the common mode voltage, the noise detection circuit and the self-capacitance detection circuit may use the same charge transfer module 104, that is, at the inverting input terminal of the charge transfer module 104, there is no need to add a switch unit, so that during the self-capacitance detection, the switch unit is connected to the common mode voltage, and during the noise detection, the switch is connected to the first voltage. In addition, the control module, the driving module, the cancellation module, the charge transfer module and the processing module in fig. 1B are the same as or similar to those described in the foregoing embodiments, and a timing chart of a switching unit included in the control module can also refer to fig. 2A, and the following description takes one cycle of a control signal as an example, and main technical processing in each period is briefly described as follows:

period t 1: charging the capacitor Cx to be measured and the offset capacitor Cc by using the common-mode voltage Vcm;

period t 2: the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc, the first end of the capacitor Cx to be measured is disconnected with the common-mode voltage Vcm, and the first end of the offset capacitor Cc is disconnected with the common-mode voltage Vcm. Period t 3: performing charge transfer, and converting the charges of the capacitor Cx to be measured and the offset capacitor Cc into voltage signals;

period t 4: the fully differential amplifier is reset.

After t4, there may be t5 to t8 to repeat the operation of t1 to t4, that is, the magnitude of the noise may also be determined according to 2 times of the output voltage of the noise detection half cycle, specifically, if the purpose is to detect the magnitude of the noise of the self-contained detection circuit with the operating frequency of f1, the demodulation frequency of the self-contained detection circuit is also f1, the magnitude of the noise may be determined according to the output voltage of 1/f1 in this time period, for example, 1/f1 may be equal to t1+ t2+ t3+ t4, or may be 1/f1 ═ 2(t1+ t2+ t3+ t4), and if the self-contained detection circuit can acquire the self-contained value within the time length of t1+ t2+ t3+ t4, the noise detection circuit may determine the noise detected by the output voltage of t4+ t4+ t4+ t4 in this time length; for another example, if the self-capacitance detection circuit can obtain the self-capacitance value through the time length of 2(t1+ t2+ t3+ t4), the noise detection circuit may determine the noise level of the self-capacitance detection circuit through the output voltage at the time length of 2(t1+ t2+ t3+ t 4).

Period t1, first switching unit K₁A second switch unit K₂Conducting (i.e. in a closed state), the third switching unit K₃And the fourth switching unit K4 is disconnected, the first ends of the capacitor Cx to be tested and the offset capacitor Cc are both connected with the common-mode voltage Vcm, the second end of the capacitor Cx to be tested and the second end of the offset capacitor Cc are both connected with GND, and the capacitor Cx to be tested and the offset capacitor Cc are charged simultaneously. When the time period t1 is over, the voltage of the capacitor Cx to be measured is the common-mode voltage Vcm, and the voltage of the offset capacitor Cc is the common-mode voltage Vcm. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the charge amount Q1 stored in the capacitance Cx to be measured is Vcm Cx, and the charge amount Q2 stored in the offset capacitance Cc is Vcm Cc.

Period t2, first switching unit K₁A second switch unit K₂Off, third switching unit K₃And when the fourth switching unit K4 is closed, the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc, and the second end of the capacitor Cx to be measured and the second end of the offset capacitor Cc are both grounded. When no noise exists (under an ideal condition), according to the charge conservation law, Vcm Cx + Vcm Cc (Vx Cx + Vx-0) Cc is established, and the voltage Vx Vcm of the capacitor Cx to be measured can be obtained; if noise exists, the charges stored in the capacitor Cx to be tested and the offset capacitor Cc are changed, the capacitor Cx to be tested and the offset capacitor Cc are charged or discharged simultaneously, the voltage Vx of the capacitor Cx to be tested is not equal to Vcm, for example, Vx>Vcm or Vx<Vcm。

Period t3, first switching unit K₁A second switch unit K₂Off, third switching unit K₃And when the voltage Vx of the capacitor Cx to be measured is closed, the fourth switch unit K4 is closed, and the following conditions exist according to the voltage Vx of the capacitor Cx to be measured:

and if Vx is larger than Vcm, transferring the charge to the charge transfer module by the capacitor Cx to be tested and the offset capacitor Cc at the same time until the voltage Vx of the capacitor Cx to be tested reaches Vcm.

If Vx is equal to Vcm, the process of transferring the charge to the charge transfer module by the capacitor Cx to be tested and the offset capacitor Cc does not exist, and the output voltage V of the charge transfer module_outIs 0, this time it means that the circuit is not affected by noise.

If Vx<Vcm, the charge transfer module will pass through the feedback network (R)_fAnd C_fComposition) charges the capacitance Cx to be measured and the offset capacitance Cc until the voltages of the capacitance Cx to be measured and the offset capacitance Cc both reach Vcm.

Period t4, first switching unit K₁A second switch unit K₂And a third switching unit K₃Is in an off state, and the fourth switching unit K₄And is turned off, so that the amplifier in the charge transfer module is reset and the output voltage Vout becomes 0, it is understood that, since the output voltage Vout may not be 0 in the third period, the output voltage Vout may not be 0 but gradually becomes 0 in a certain tendency in the fourth period.

As can be seen from the above description, in the absence of noise, the voltages of the capacitance to be detected Cx and the cancellation capacitance Cc at the end of the t2 time period or the end of the t3 time period are determined to be Vcm, in the presence of noise, the voltages of the capacitance to be detected Cx and the cancellation capacitance Cc at the end of the t2 time period are not determined to be Vcm, in the t3 time period, charges are transferred, and the magnitude of the noise affects the number of the charges transferred, so that the noise detection circuit can accurately measure the noise affecting the capacitance to be detected, so as to adjust the self-capacitance detection scheme, improve the self-capacitance detection scheme, or further correct the result of the self-capacitance detection.

Based on the disclosure of the above embodiment, in this embodiment, as shown in fig. 1C, the control module 100 is configured to control the driving module 102 to perform charging processing on the capacitance Cx to be measured by using the first voltage Vmm, and unlike in fig. 1A, the control module 100 is configured to control the cancellation module 103 to connect both ends of the cancellation capacitance Cc to the first voltage Vmm. In addition, the control module 100 controls the cancellation module 103 so that the first end of the cancellation capacitance Cc and the first end of the capacitance Cx to be measured are connected in the second period and the third period. The second end of the capacitor Cx to be measured is grounded, and the second end of the offset capacitor is connected with the first voltage Vmm. In addition, the control module, the driving module, the cancellation module, the charge transfer module and the processing module in fig. 1C are the same as or similar to those described in the foregoing embodiments, and a timing chart of a switching unit included in the control module can also refer to fig. 2A, and the following description takes one cycle of a control signal as an example, and main technical processing in each period is briefly described as follows:

period t 1: charging the capacitor Cx to be measured by using a first voltage Vmm, wherein the first end and the second end of the offset capacitor Cc are both connected with a first voltage Vmm;

period t 2: the first end of the capacitance to be measured Cx is connected to the first end of the offset capacitance Cc, the first end of the capacitance to be measured Cx is disconnected from the first voltage Vmm, and the first end of the offset capacitance Cc is disconnected from the first voltage Vmm.

period t 4: the fully differential amplifier is reset.

Period t1, first switching unit K₁A second switch unit K₂Conducting (i.e. in a closed state), the third switching unit K₃The fourth switching unit K4 is disconnected, the first ends of the capacitor Cx to be measured and the offset capacitor Cc are connected with the first voltage Vmm, the second end of the capacitor Cx to be measured is connected with GND, the second end of the offset capacitor Cc is connected with the first voltage Vmm, and the capacitor Cx to be measured is charged in the first period. At the end of the time period t1, the voltage of the capacitor Cx to be measured is the first voltage Vmm, and the voltage of the offset capacitor Cc is 0. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the charge amount Q1 stored in the capacitance Cx to be measured becomes Vcm Cx, and the charge amount Q2 stored in the offset capacitance Cc becomes 0 Cc.

Period t2, first switching unit K₁A second switch unit K₂Off, third switching unit K₃The fourth switch unit K4 is turned off, the first end of the capacitor Cx to be tested is connected with the first end of the offset capacitor Cc, and the second end of the capacitor Cx to be tested is grounded to offsetA second terminal of capacitor Cc is coupled to first voltage Vmm. When no noise exists (under an ideal condition), Vmm Cx +0 Cc (Vx-Vmm) Cc is established according to the charge conservation law, and the voltage Vx-Vmm of the capacitor Cx to be measured can be obtained; if noise exists, the charges stored in the capacitor Cx to be tested and the offset capacitor Cc are changed, the capacitor Cx to be tested and the offset capacitor Cc are charged or discharged simultaneously, the voltage Vx of the capacitor Cx to be tested is not equal to Vmm, for example, Vx>Vmm or Vx<Vmm。

Period t3, first switching unit K₁A second switch unit K₂Open, third switching unit K₃Closed, fourth switching unit K₄And closing, wherein the following conditions exist according to the voltage Vx of the capacitor Cx to be measured:

and if Vx is greater than Vmm, transferring the charge to the charge transfer module by the capacitor to be measured Cx and the offset capacitor Cc at the same time until the voltage Vx of the capacitor to be measured Cx reaches Vcm.

If Vx is equal to Vcm, there is no process of transferring charge to the charge transfer module by the capacitance to be measured Cx and the offset capacitance Cc, and the output voltage Vout of the charge transfer module is 0, which indicates that the circuit is not affected by noise.

Period t4, first switching unit K₁A second switch unit K₂And a third switching unit K₃Is in an off state, and the fourth switching unit K₄Off, so that the amplifier in the charge transfer module is reset and the output voltage Vout becomes 0.

Based on the disclosure of the foregoing embodiment, in this embodiment, as shown in fig. 1D, different from fig. 1C, the first voltage is a common mode voltage Vcm, and in addition, the control module, the driving module, the cancellation module, the charge transfer module and the processing module in fig. 1D are the same as or similar to those described in the foregoing embodiment, a timing diagram of a switching unit included in the embodiment may also refer to fig. 2A, and a cycle of a control signal is taken as an example to be described below, and main technical processes in each period are briefly described as follows:

period t 1: charging the capacitor Cx to be measured by using the common-mode voltage Vcm, and connecting a first end and a second end of the offset capacitor with the common-mode voltage Vcm;

period t 2: the first end of the capacitor Cx to be detected is connected with the first end of the offset capacitor Cc, the first end of the capacitor Cx to be detected is disconnected with the common-mode voltage Vcm, and the first end of the offset capacitor Cc is disconnected with the common-mode voltage Vcm;

period t 4: the fully differential amplifier is reset.

Period t1, first switching unit K₁A second switch unit K₂Conducting (i.e. in a closed state), the third switching unit K₃And the fourth switching unit K4 is disconnected, the first ends of the capacitor Cx to be detected and the offset capacitor Cc are both connected with the common-mode voltage Vcm, the second end of the capacitor Cx to be detected is connected with GND, and the second end of the offset capacitor Cc is connected with the common-mode voltage Vcm. In the first period, the capacitance Cx to be measured is charged. And when the time period t1 is over, the voltage of the capacitor Cx to be measured is Vcm, and the voltage of the offset capacitor Cc is 0. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the charge amount Q1 stored in the capacitance Cx to be measured becomes Vcm Cx, and the charge amount Q2 stored in the offset capacitance Cc becomes 0.

Period t2, first switching unit K₁A second switch unit K₂Off, third switching unit K₃Closed and the fourth switching unit K4 open. When no noise exists (under an ideal condition), according to the charge conservation law, Vcm Cx +0 ═ Vx Cx + (Vx-Vcm) × Cc is established, and the voltage Vx ═ Vcm of the capacitor Cx to be measured can be obtained; if noise exists, the charges stored in the capacitor Cx to be tested and the offset capacitor Cc are changed, the capacitor Cx to be tested and the offset capacitor Cc are charged or discharged simultaneously, the voltage Vx of the capacitor Cx to be tested is not equal to Vcm, for example, Vx>Vcm or Vx<Vcm。

Period t3, first switching unit K₁A second switch unit K₂Off, third switching unit K₃Closed, fourth switching unit K4 closedAccording to the magnitude of the voltage Vx of the capacitor Cx to be measured, the following conditions exist:

If Vx is equal to Vcm, the process of transferring the charge to the charge transfer module by the capacitor Cx to be tested and the offset capacitor Cc does not exist, and the output voltage V of the charge transfer module _out0, which indicates that the circuit is free of noise.

the case of the period t4 is similar to the previous embodiment and is not described here.

Taking the simulated waveform as an example to describe each time period Vx and Vout, please refer to fig. 2C, where v (x) represents the voltage Vx of the first end of the capacitor to be measured or the first end of the cancellation capacitor in fig. 2C, and v (out) represents the output voltage Vout of the charge transfer module. The first voltage Vmm is 1.5V for example.

In a period t1, the capacitance Cx to be measured and the offset capacitance Cc are charged with the first voltage Vmm, or in a period t1, the capacitance Cx to be measured is charged with the first voltage Vmm, and the first and second ends of the offset capacitance are connected to the first voltage Vmm. In both cases, Vx is Vmm, and at this time, the fourth switching unit is in an off state, and the output voltage Vout is 0;

in a period t2, the first terminal of the capacitor to be tested Cx is connected to the first terminal of the cancellation capacitor Cc, and the interference source affects the charge amounts of the capacitor to be tested and the cancellation capacitor, so that the voltage of Vx is not Vmm, for example, Vx < Vmm, and the output voltage Vout is 0 because the fourth switching unit is in the off state;

in a period t3, performing charge transfer, converting charges of the capacitor Cx to be detected and the offset capacitor Cc into voltage signals, gradually returning the voltages of the capacitor Cx to be detected and the offset capacitor Cc to a first voltage Vmm, enabling the fourth switching unit to be in a closed state, and outputting a voltage Vout >0 when Vx is less than Vmm in a period t 3;

in a period t4, the fully differential amplifier is reset, the fourth switching unit is in an off state, and Vout gradually returns to 0;

in a stage t5, the capacitance Cx to be measured and the cancellation capacitance Cc are charged by using the first voltage Vmm, or in a period t1, the capacitance Cx to be measured is charged by using the first voltage Vmm, and the first terminal and the second terminal of the cancellation capacitance are connected to the first voltage Vmm. In both cases, Vx is Vmm, at which time the fourth switching unit is in the off state and the output voltage gradually returns to 0, and if the output voltage has returned to 0 during the fourth period, the output voltage Vout remains at 0 during the fifth period;

in a period t6, the first end of the capacitor Cx to be tested is connected with the first end of the offset capacitor Cc, the interference source influences the charge amount of the capacitor Cc to be tested and the offset capacitor, therefore, the voltage of Vx is not Vmm, for example, Vx > Vmm, and the output voltage Vout gradually returns to 0 because the fourth switching unit is in an off state, and if the output voltage has returned to 0 in the fifth period, the output voltage Vout is kept at 0 in the sixth period;

in a period t7, performing charge transfer, converting charges of the capacitance Cx to be detected and the offset capacitance Cc into voltage signals, gradually returning the voltages of the capacitance Cx to be detected and the offset capacitance Cc to the first voltage, enabling the fourth switching unit to be in a closed state, when the period t6 begins, Vx is greater than Vmm, outputting a voltage Vout <0, and gradually increasing the subsequent Vout to be greater than 0 due to the influence of the interference source in the period;

during a period t8, the fully differential amplifier is reset, the fourth switching unit is in the off state, and Vout gradually returns to 0.

In this embodiment, the time period t1 is less than 2us, the time period t2 is about 1us, specifically, the time period t2 is less than 1us, the time period t3 is about 2us, and the time period t4 is less than 1 us. Therefore, the length of each time interval is short, noise can be obtained through a quick test, 5us can realize noise measurement, namely the noise detection half period can be 5us, and the noise detection circuit can work under the condition that f is 1/(5us) is 0.2 to 10 in the condition that 5us is about⁶Noise level in Hz, if the measured noise amplitude is less than the preset noise thresholdThe value of f is 0.2 x 10 for the self-capacitance detection circuit⁶The operating frequency in Hz is detected as self-capacitance. The noise can be measured by 10us, namely the noise detection period is 10us, and the noise detection circuit can work at f 1/(10us) 10us in about 10us⁵If the measured noise amplitude is smaller than the preset noise threshold, the self-capacitance detection circuit may use f equal to 10⁵The operating frequency in Hz is detected as self-capacitance. In other embodiments, the sum of the first period, the second period, the third period, and the fourth period may also be less than 10us, for example, the sum of the first period, the second period, the third period, and the fourth period may also be less than 5 us.

Based on the disclosure of the foregoing embodiments, in this embodiment, as shown in fig. 3, the interference source 301, the driving module 302, the charge transfer module 304, and the processing module 305 are the same as or similar to those of the foregoing embodiments, and no further description is provided herein, in this embodiment, the first voltage is taken as a common mode voltage Vcm for an example to describe, and the control module 300 is configured to control the driving module 302 to perform charging processing on the capacitor to be tested by using the common mode voltage, and control the cancellation module 303 to enable the first end and the second end of the cancellation capacitor to be connected to the common mode voltage.

As shown in fig. 3, the cancellation module 303 includes a second switch unit K₂(taking a single switch implementation as an example), in this embodiment, the second switch unit K2 is a switch with three contacts, and the second end of the cancellation capacitor Cc is connected to Vcm. In particular, the control module 300 controls the second switching unit K₂In the contact 1 (the contact of the second switch unit is connected to the contact 1), the first end of the cancellation capacitor Cc is connected to Vcm, so that the cancellation capacitor Cc is connected to Vcm at both ends of the first period. Specifically, the second switching unit K during the second and third periods₂And the offset capacitor Cc is positioned at a contact point 2 (the contact of the second switch unit is connected with the contact point 2), and the first end of the offset capacitor Cc is connected with the first end of the capacitor Cx to be measured. The second terminal of the cancellation capacitor Cc is connected to Vcm. Specifically, in the fourth period, the second switching unit K₂At the contact 3 (the contact of the second switch unit is connected with the contact 3), the first end of the offset capacitor Cc is floating, i.e. it can be understood thatThe offset capacitor Cc is disconnected with the capacitor Cx to be measured, and the offset capacitor Cc is not connected to the circuit.

When the control module 300 controls the second switch unit K₂When the contact is at the contact 2, the capacitance Cx to be measured and the offset capacitance Cc form a closed branch, when the stage t2 is finished, the stored charge amounts of the capacitance to be measured and the offset capacitance Cc are different, and due to the influence of noise, the voltage Vx of the connection point of the offset capacitance Cc and the capacitance Cx to be measured changes, and then the offset capacitance Cc and the capacitance Cx to be measured can be charged or discharged, so when the stage t2 is finished, the voltage of the connection point of the offset capacitance Cc and the capacitance Cx to be measured is not Vcm.

In this embodiment, the first switch unit K₁A second switch unit K₂And a fourth switching unit K₄See the description of fig. 4. FIG. 4 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 3 according to an embodiment of the present application; as shown in FIG. 4, the time period t1-t4 constitutes one cycle of the control signals φ 1, φ 2, φ 3. The brief description of the time period t1-t4 is as follows:

period t 1: charging the capacitor Cx to be measured by using a common-mode voltage, and connecting two ends of the offset capacitor Cc with the common-mode voltage;

period t 2: the first end of the capacitor Cx to be detected is connected with the first end of the offset capacitor Cc, the first end of the capacitor Cx to be detected is disconnected with the common-mode voltage, and the first end of the offset capacitor Cc is disconnected with the common-mode voltage;

period t 3: carrying out charge transfer, and converting the charges stored by the measuring capacitor Cx and the offset capacitor Cc into voltage signals;

period t 4: the fully differential amplifier is reset.

Period t1, first switching unit K₁On (in a closed state), the second switching unit K₂Connected to contact 1 (second switching unit in first closed state) the fourth switching unit K4 is open. The capacitor Cx to be measured is charged, and the two ends of the offset capacitor Cc are connected with the common-mode voltage. And when the time period t1 is over, the voltage of the capacitor Cx to be measured is Vcm, and the voltage of the offset capacitor Cc is 0. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the electricity stored in the capacitance Cx to be measuredThe charge amount Q1 becomes Vcm Cx, and the charge amount Q2 stored in the compensation capacitor Cc becomes 0.

Period t2, first switching unit K₁Off, second switching unit K₂Connected to contact 2 (second switching unit in second closed state) the fourth switching unit K4 is open. When no noise exists (under an ideal condition), Vcm + Cx +0 ═ Vx + Cc (Vx-Vcm) is established, and the voltage Vx ═ Vcm of the capacitor Cx to be measured can be obtained; if there is noise, the charges stored in the capacitance to be measured Cx and the offset capacitance Cc change, and it can be understood that, in the stage t2, if there is noise, the capacitance to be measured Cx is charged and the offset capacitance Cc is charged, or the capacitance to be measured Cx is discharged and the offset capacitance Cc is discharged. That is, if there is noise, the voltage Vx of the capacitance Cx to be measured is not equal to Vcm, Vx>Vcm or Vx<Vcm。

Period t3, first switching unit K₁Remains off, second switching unit K₂A fourth switching unit K connected to the contact 2₄And closing, wherein the following conditions exist according to the voltage Vx of the capacitor Cx to be measured:

If Vx is equal to Vcm, there is no process of transferring the charge to the charge transfer module by the capacitance to be measured Cx and the offset capacitance Cc, and the output voltage Vout of the charge transfer module is 0, which means that there is no noise.

Period t4, first switching unit K₁Off, second switching unit K₂Is connected to the contact 3 and the fourth switching unit K₄When the second switch unit is disconnected and connected to the contact 3, which may also be referred to as the second switch unit being in an off state or an open state, the charge transfer module 304 is reset at stage t4, and the output voltage Vout becomes 0. In addition, during a period t4, the second switching unit K₂Can also be connected with the contact 2, i.e. the main bodyIn an embodiment, the contact 3 may not be present.

As can be seen from the above description, in the absence of noise, the voltage of the capacitance Cx to be detected at the end of the time period t2 is determined to be Vcm, in the presence of noise, the voltages of the capacitance Cx to be detected and the offset capacitance Cc at the end of the time period t2 are not determined to be Vcm, and in the time period t3, charges are transferred, and the amount of noise affects the number of charge transfers, so that the noise detection circuit can accurately measure the noise affecting the capacitance to be detected, so as to adjust the self-capacitance detection scheme, improve the self-capacitance detection scheme according to the detected noise affecting the capacitance to be detected, or further correct the result of self-capacitance detection.

Based on the disclosure of the above embodiments, in this embodiment, as shown in fig. 5, the noise detection circuit, the interference source 501, the driving module 502, the charge transfer module 504, and the processing module 505 of this embodiment are the same as or similar to those of the foregoing embodiments, and are not repeated here. Different from fig. 3, the second terminal of the cancellation capacitor in the cancellation module is grounded, and correspondingly, the first switch unit K₁A second switch unit K₂And a fourth switching unit K₄Can be seen in fig. 4, described below in connection with a specific time period.

Period t 1: charging the capacitor Cx to be measured and the cancellation capacitor Cc by using the common-mode voltage;

period t 4: the fully differential amplifier is reset.

Period t1, first switching unit K₁On (i.e. in a closed state), the second switching unit K₂Is connected with the contact 1 (the second switch unit is in the first closed state), the fourth switch unit K4 is disconnected, the capacitor Cx to be measured is charged, and the offset capacitor Cc is charged. At the end of the period t1,the voltage of the capacitor Cx to be measured is Vcm, and the voltage of the offset capacitor Cc is Vcm. In addition, since the fourth switching unit K4 is turned off, the output voltage Vout of the charge transfer module is 0. At this time, the charge amount Q1 stored in the capacitance Cx to be measured is Vcm Cx, and the charge amount Q2 stored in the offset capacitance Cc is Vcm Cc.

Period t2, first switching unit K₁Off, second switching unit K₂Connected to contact 2 (second switching unit in second closed state) the fourth switching unit K4 is open. When no noise exists, according to the charge conservation law, the voltage Vx of the capacitor Cx to be measured is obtained by establishing Vcm Cx + Vcm Cc (Vx-0) Cc; if noise exists, the charges stored in the capacitor Cx to be tested and the offset capacitor Cc are changed, the voltage Vx of the capacitor Cx to be tested is not equal to Vcm, for example, Vx>Vcm or Vx<Vcm. In addition, the cases of the t3 time period and the t4 time period are the same as or similar to the previous embodiments, and are not repeated here.

With reference to the foregoing embodiments, in this embodiment, the control module is further configured to switch the first voltage, so that the control module controls the driving module, the cancellation module, the charge transfer module, and the processing module to perform self-capacitance detection. The following description is made with reference to the capacitance detection circuit, and please refer to the timing diagrams of the self-capacitance detection circuit shown in fig. 6 and the capacitance detection circuit shown in fig. 7. In the self-capacitance detection circuit shown in fig. 6, Vss may be equal to GND or-Vcc when self-capacitance detection is performed, and if Cc is Cx/3 when Vss is GND, the circuit completely cancels out; when Vss is-Vcc, the circuit cancels if Cc is Cx/5. The circuit reaches a complete offset state, the basic capacitance of the capacitor Cx to be detected can be completely offset, and when a touch occurs, the capacitance of the capacitor Cx to be detected is increased on the basis of the basic capacitance, and the output voltage V is_OUTIs caused entirely by touch. Therefore, the detection sensitivity of the self-contained detection circuit is highest in this state.

Taking the ninth time period to the sixteenth time period (t9-t16) as an example to explain with reference to fig. 7, when performing self-capacitance detection, in the ninth time period, the capacitor to be measured and the cancellation capacitor are charged, and in the tenth time period, the capacitor to be measured and the cancellation capacitor are charge-cancelled; in the eleventh time period, the charges of the capacitor to be measured and the counteracting capacitor are subjected to charge transfer; in a twelfth period, the charge transfer module is reset; the ninth period, tenth period, eleventh period, twelfth period may correspond to a charging time, a cancelling time, a charge transfer time, a dead time, respectively. In the thirteenth time period, discharging the capacitor to be detected and charging the cancellation capacitor; in a fourteenth time period, carrying out charge cancellation on the capacitor to be detected and the capacitor; in a fifteenth time period, carrying out charge transfer on the charges of the capacitor to be measured and the offset capacitor; in a sixteenth period, the charge transfer module is reset; the thirteenth period, the fourteenth period, the fifteenth period, the sixteenth period may also correspond to a charging time, a cancellation time, a charge transfer time, and a dead time, respectively. The ninth, tenth, eleventh, twelfth periods have lengths equal to the thirteenth, fourteenth, fifteenth, and sixteenth periods, respectively. At the time of self-capacitance detection, there is a movement of charge in time t10, that is, the charge of the capacitor to be measured moves to the cancellation capacitor, or the charge of the cancellation capacitor moves to the capacitor to be measured. If t2 is not set during noise detection, when a time period of t3 is entered, only the charges of the interference source are transferred to the charge transfer module, and the charges of the cancellation capacitor and the capacitor to be detected are not transferred to the charge transfer module, while during self-capacitance detection, the charges generated by the charging or discharging of the cancellation capacitor and the capacitor to be detected by the interference source are transferred to the charge conversion module, therefore, during noise detection, t2 is also set, so that the noise obtained by testing can be closer to the noise during self-capacitance detection, the detection is more accurate, and the noise measured during noise detection can be kept as consistent as possible with the noise during self-capacitance detection; during the self-capacitance detection, when the stage t11 is entered, the charge of the cancellation capacitor and the capacitor to be detected is transferred to the charge transfer module.

The control module 600, the driving module 601, the cancellation module 603, the charge transfer module 603, and the processing module 604 in fig. 6 are similar to the previous embodiments, and the processing module 604 is configured to detect the output voltage of the charge cancellation module 603, calculate the self-capacitance variation of the capacitance Cx to be measured before and after the touch, and finally obtain a digital quantity for representing the variation. In addition, in combination therewithThe technical principle of fig. 7 can be obtained through analysis, and is not described herein again, it should be noted that the period T in fig. 7 represents a detection period of self-capacitance detection, that is, it is required to pass through T1-T8 to complete self-capacitance detection, or it is required to pass through T9-T16 to obtain a capacitance value of self-capacitance detection. The detection period T being the control signal phi₁、φ₂、φ₃Twice the period of (c). Based on the self-capacitance detection circuit shown in fig. 6, how to detect noise in fig. 8 will be described in detail below.

Referring to the noise detection circuit shown in fig. 8, in the present embodiment, in order to save circuit area, the noise detection circuit and the self-capacitance detection circuit may share a part of the circuit. The number of switching cells of the noise detection circuit shown in fig. 8 is the same as the number of switching cells of the self-capacitance detection circuit shown in fig. 6.

In the noise detection circuit shown in fig. 8, for the driving module, the second end of the capacitor to be tested is grounded, and the first switching unit K of the two switching units of the driving module₁And a fifth switching unit K₅Are used for controlling whether the first end of the capacitor to be tested is connected with the common mode voltage. First switch unit K in driving module in this embodiment₁And a fifth switching unit K₅Or may be realized by only one switch unit, and the embodiment is realized by only two switch units K₁、K₅The description is given for the sake of example to facilitate understanding of how the noise detection circuit and the self-capacitance detection circuit are realized to share one circuit. In the noise detection, the driving module in fig. 8 can be understood as the switching unit K in the driving module in fig. 6₅The Vcc and GND of the 1 and 2 contacts are obtained by switching to common-mode voltage; in the case of self-contained detection, the drive module in fig. 6 can be understood as the drive module in fig. 8 with the fifth switching unit K₅The common mode voltage of the connection is switched to Vcc and GND.

In the noise detection circuit of fig. 8, for the cancellation module, the switch unit in the cancellation module is used to control whether the first end and the second end of the cancellation capacitor are connected to the common mode voltage, wherein the switch unit K is used to control whether the common mode voltage is connected to the first end and the second end of the cancellation capacitor₂And the control circuit is also used for controlling whether the first end of the offset capacitor is connected with the first end of the capacitor to be detected. Noise detection circuitThe cancellation block in (1) may be understood as a result of switching a power supply (including Vss — Vcc, and GND) of the cancellation block in the self-capacitance detection circuit of fig. 6 to a common-mode voltage. When performing self-capacitance detection, the cancellation module in fig. 6 may be understood as obtained by switching the common mode voltage connected to the sixth switching unit of the cancellation module in fig. 8 to Vss and Vcc, switching the common mode voltage connected to the seventh switching unit in the cancellation module to Vcc and Vss, and switching the common mode voltage connected to the eighth switching unit in the cancellation module to Vcc and GND.

The charge transfer module 804 and the processing module 805 in the noise detection circuit of fig. 8 are the same as or similar to those in the previous embodiment, and the description of this embodiment is omitted.

The specific structure of the noise detection circuit shown in fig. 8 is specifically described below, and the number of the switch units in fig. 8 is the same as that of the switch units in fig. 6, except that the voltage sources connected to some of the switch units are switched to the common mode voltage, as described above. Unlike the noise detection circuits of fig. 1A, 1B, 1C, 1D, and 3, the noise detection circuit of the present embodiment adds a switching unit so that the noise detection circuit can multiplex the switching unit of the self-capacitance detection circuit. The driving module 802 includes a first switch unit K₁And a fifth switching unit K₅The cancellation module 803 includes a second switch unit K₂And a sixth switching unit K₆Seventh switching unit K₇And an eighth switching unit K₈And a ninth switching unit K₉The charge transfer module 804 includes a fourth switching unit K₄. In the present embodiment, the second switching unit K₂The fifth switch unit K₅And a sixth switching unit K₆Seventh switching unit K₇The eighth switching unit K₈And a ninth switching unit K₉Taking a single switch implementation as an example, it is embodied as a single pole double throw switch, which has

contacts

1, 2, respectively, having two closed states, respectively referred to as a first closed state and a second closed state, the first closed state being when switched to contact 1 and the second closed state being when switched to contact 2. Further, the control module 800 is further used for controlling the switch K₁～K₂、K₄～K₉The control module 800 may be a programmable sequential logic circuit. Control the first switching unit K₁The on-off signal is recorded as phi₁(alternatively referred to as a first control signal) controlling the second switching unit K₂And a ninth switching unit K₉The on-off signal is recorded as phi₂(alternatively referred to as a second control signal) controlling the switch K₄The on-off signal is recorded as phi₃(alternatively referred to as a third control signal) controlling the fifth switching unit K₅Eighth switching unit K₈The on-off signal is recorded as phi₄(or fourth control signal). Namely, the second switch unit and the ninth switch unit are synchronously controlled to switch between the closed states by the second control signal, and the fifth switch unit and the eighth switch unit are synchronously controlled to switch between the closed states by the fourth control signal, so that the capacitor to be detected, the offset capacitor are processed, and the charge transfer module performs charge transfer, thereby realizing noise detection or self-capacitance detection.

In this example. When K in FIG. 8₁Is closed and K₅In the first closed state or the second closed state, the driving module 802 in fig. 8 is similar to the driving module 302 in fig. 3 in the time period t1, that is, the capacitor Cx to be measured is charged. When the switch K in FIG. 8₆In a first closed or second closed state, and K₉In a first closed state, K₇When in the first or second closed state, cancellation module 803 in fig. 8 is similar to cancellation module 303 in fig. 3 in time period t1, i.e., the first and second ends of cancellation capacitor Cc are both connected to the common mode voltage; when the switch K in FIG. 8₆In a first closed or second closed state, and K₉In a second closed state, K₈In the first or second closed state, cancellation module 803 in fig. 8 is also similar to cancellation module 303 in fig. 3 in time period t1, i.e., the first and second ends of cancellation capacitor Cc are both connected to the common mode voltage. Referring to fig. 8, when the first switch unit K is turned on₁In a closed state and the fifth switching unit K₅In a first closed stateWhen the capacitor Cx is in the second closed state, the first end of the capacitor Cx to be detected is connected with the common-mode voltage; when the second switch unit K₂In the first closed state, the sixth switching unit K₆In a first closed state or a second closed state, K₉In a first closed state, K₇When the offset capacitor is in a first closed state or a second closed state, the first end and the second end of the offset capacitor are connected with the common-mode voltage; when the second switch unit K₂In the first closed state, the sixth switching unit K₆In a first closed state or a second closed state, K₉In a second closed state, K₈When the capacitor is in the first closed state or the second closed state, the first end and the second end of the offset capacitor are connected with the common mode voltage. When the second switch unit K₂In the second closed state, the ninth switching unit K₉In the first closed state and the seventh switching unit K₇When the capacitor is in the first closed state or the second closed state, the first end of the offset capacitor Cc is connected with the first end of the capacitor Cx to be measured, and the second end of the offset capacitor Cc is connected with the common-mode voltage. When the second switch unit K₂In the second closed state, the ninth switching unit K₉In the second closed state and the eighth switching unit K₈When the capacitor is in the first closed state or the second closed state, the first end of the offset capacitor Cc is connected with the first end of the capacitor Cx to be measured, and the second end of the offset capacitor Cc is connected with the common-mode voltage.

The operation principle of the noise detection circuit in fig. 8 is described below with reference to the timing chart corresponding to fig. 7 in fig. 8. Fig. 7 is a timing diagram of the noise detection circuit in fig. 8 according to the present embodiment, that is, the timing of the noise detection circuit may be the same as the timing of the self-capacitance detection circuit; as shown in FIG. 7, the t1-t4 time period and the t5-t8 time period constitute a detection cycle, and the main technical processes for each time period are briefly described as follows:

period t 1: charging the capacitor Cx to be measured, and connecting common-mode voltage to two ends of the offset capacitor Cc;

period t 2: the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc;

period t 3: performing charge transfer, and converting the charge of the capacitor Cx to be measured and the charge of the offset capacitor Cc into voltage signals;

period t 4: resetting the charge transfer module;

period t 5: charging the capacitor Cx to be measured, and connecting common-mode voltage to two ends of the offset capacitor Cc;

period t 6: the first end of the capacitor Cx to be measured is connected with the first end of the offset capacitor Cc;

period t 7: performing charge transfer, and converting the charge of the capacitor Cx to be measured and the charge of the offset capacitor Cc into voltage signals;

period t 8: the charge transfer module is reset, and the output voltage signal is 0.

As shown in fig. 7, the first control signal Φ₁-third control signal Φ₃Has a signal frequency of the fourth control signal phi₄Twice as much, in the present embodiment, for the noise detection circuit, the first control signal Φ₁-third control signal Φ₃Is equal in frequency to the fourth control signal phi₄Is not limited. Because the first control signal phi is detected during self-capacitance detection₁-third control signal Φ₃Has a signal frequency of the fourth control signal phi₄Twice as much as for convenience, to avoid applying a fourth control signal phi₄Reset, the first control signal phi can also be set at the time of noise detection₁-third control signal Φ₃Has a signal frequency of the fourth control signal phi₄Twice, in particular, the fourth control signal Φ₄May be a square wave with a 50% duty cycle. In this embodiment, t1 is t5, t2 is t6, t3 is t7, and t4 is t 8; the detailed time sequence process is as follows:

period t1, first switching unit K₁On, the fifth switching unit K₅And a sixth switching unit K₆Seventh switching unit K₇A second switch unit K₂And a ninth switching unit K₉In the first closed state, the fourth switching unit K₄Turning off to make the first end of the capacitor Cx to be measured connected with Vcm and the second end connected with GND, connecting the first end of the offset capacitor with Vcm and connecting the second end of the offset capacitor with Vcm, and finally charging the capacitor Cx to be measured. At the end of the period t1, the voltage of the capacitor Cx to be measured is Vcm (i.e., Vcm-GND), and the voltage of the cancellation capacitor Cc is 0 (i.e., Vcm-Vcm equals 0). At this time, the charge amount Q1 stored in the capacitance Cx to be measured is (Vcm-Vcm) × Cx, and the charge amount Q2 stored in the offset capacitance Cc is (Vcm-Vcm) × Cc is 0. At the same time, since the fourth switching unit K₄Off, therefore, the output voltage Vout of the charge transfer module 804 is 0.

Period t2, first switching unit K₁And a fourth switching unit K₄A second switch unit K which is turned off under the control of the first control signal and the third control signal respectively₂And a ninth switching unit K₉A fifth switching unit K connected to the contact 2 to be in a second closed state under the control of a second control signal₅Eighth switching unit K₈And the capacitor Cx to be measured is connected with the offset capacitor Cc under the control of the fourth control signal and is connected to the contact 1 to be in the first closed state. According to the charge conservation law, when Vcm Cx +0 ═ Vx Cx + (Vx-Vxm) × Cc is established, the voltage Vx ═ Vcm of the capacitor to be measured can be obtained. It should be noted that, if there is noise, for example, the interference source 801 simulates interference, and the interference source 801 affects the capacitance Cx to be measured and the offset capacitance Cc, so that the voltage Vx of the capacitance Cx to be measured is not equal to Vcm, it can be understood that the interference of the interference source 801 causes the capacitance to be measured and the offset capacitance to be charged or discharged, so that the voltage Vx of the capacitance Cx to be measured is greater than or less than Vcm.

Period t3, fourth switching unit K₄And when the other switches are turned on, the state of the other switches is kept consistent with the state in the time period t2, and if the voltage Vx of the capacitor Cx to be measured is greater than or less than Vcm, charge transfer is carried out among the capacitor Cx to be measured, the offset capacitor Cc and the charge transfer module 142.

Period t4, fourth switching unit K₄When turned off, the other switches may keep the state of the t3 period consistent, the charge transfer module 804 is reset, the output voltage Vout of the charge transfer module 804 becomes 0, and the t4 period may be referred to as a dead time period.

the t5-t8 time period is similar to the t1-t4 time period and is not repeated here.

In the above working process, charge transfer may occur in the time periods t3 and t7, charges of the capacitance to be measured and the offset capacitance may be transferred to the charge transfer module, and according to the voltage Vx across the capacitance Cx to be measured at the end of the time periods t2 and t6, there are several cases:

if Vx>V_CMThe capacitor Cx and the offset capacitor Cc to be tested transfer charges to the charge transfer module 804 at the same time until the voltage of the capacitor Cx to be tested reaches the common mode voltage V_CM. In this process, the output voltage Vout of the charge transfer module 804 is a negative voltage, but Vout may also gradually become a positive voltage due to the influence of the interference source.

If Vx is equal to V_CMIf the charge transferred between the capacitance Cx to be measured and the offset capacitance Cc and the charge transfer module 804 is 0, the output voltage Vout of the charge transfer module 804 is also 0, and at this time, the circuit reaches a complete offset state.

If Vx<V_CMThe charge transfer module 142 will pass through the feedback network (R)_fAnd C_f) Charging the capacitor Cx and the offset capacitor Cc to be measured until the voltage of the capacitor Cx and the offset capacitor Cc to be measured reaches the common-mode voltage V_CM. In this process, the output voltage Vout of the charge transfer module 804 is a positive voltage, but Vout may also gradually become a negative voltage due to the influence of the interference source.

The output voltages of the charge transfer modules 804 are filtered by filters in the processing module 152, for example, Anti-aliasing filters (AAF), and the filtered output voltages are sent to Analog-to-digital converters (ADC) for sampling, and then quadrature-demodulated by a digital signal PROCESSOR (DIGITAL SIGNAL PROCESSOR, DSP), where the reference frequency used for demodulation can be understood as the operating frequency of the noise detection circuit. The demodulated raw data is sent to a Central Processing Unit (CPU) for noise calculation to obtain the magnitude, e.g., amplitude, of the noise.

Based on the disclosure of the above embodiments, in the present embodiment, when detecting noise, the noise detection period is T1+ T2+ T3+ T4, and it can be understood that if the operating frequency of self-capacitance detection is 1/T, the reference frequency used for demodulation in the digital signal processor is 1/T. When the operating frequency of the self-contained test is 1/(2T), it is necessary to detect 2T, and when 2T is T1+ T2+ T3+ T4+ T1+ T2+ T3+ T4, the reference frequency used for demodulation in the digital signal processor after filtering the output voltage of the charge transfer module during 2T is 1/(2T), so that the frequency response of the noise detection circuit at the preset operating frequency to noise (interference) can be tested. When there is no period T4, i.e. the period T4 can be omitted, T1+ T2+ T3 changes the reference frequency used for demodulation, so as to demodulate the frequency response of the accurate noise.

In combination with the disclosure of the foregoing embodiments, in the present embodiment, the amplifier may also be a single-ended amplifier, for example. Referring to fig. 9, the charge transfer module 904 includes a single-ended amplifier, and a negative input terminal of the single-ended amplifier is connected to the first voltage. The interference source 901, the driving module 902, the cancelling module 903, the charge transfer module 904, and the processing module 905 are the same as or similar to those in the foregoing embodiments, and the timing sequence thereof is the same as that in fig. 1A in the foregoing embodiments, and are not described herein again. Fig. 10 is a frequency response graph (solid gray line) of the self-capacitance detection circuit to the preset noise when the electrode is not touched by a finger, which is obtained by simulation, and a frequency response graph (broken black line) of the noise detection circuit of the present embodiment to the same preset noise, wherein it can be understood that the frequency response refers to applying a signal with a specific frequency to a circuit/system to detect the degree of response of the system to the signal with the specific frequency; alternatively, a signal in a frequency range is applied, and the degree of response of the detection system to the signal in the frequency range, i.e., a frequency response diagram, can characterize the circuit characteristics. Specifically, the frequency of the interference source with the frequency of 10 to 500kHz may be set to perform frequency sweeping, that is, the preset noise may be described by taking the frequency sweeping of the interference source with the frequency of 10 to 500kHz as an example, when there is no finger touch, the frequency response graph measured by the self-contained detection circuit shown in fig. 6 is represented by a gray solid line, the frequency response graph measured by the noise detection circuit shown in fig. 8 is represented by a black dotted line, and the circuits shown in fig. 6 and 8 both adopt the timing sequence shown in fig. 7. When there is no finger touch, the Frequency Response (Frequency Response) of Vout of the self-capacitance detection circuit and Vout of the noise detection circuit is substantially the same. The reason why the amplitude of the two is different and the noise in the self-capacitance detection circuit is larger is that there is a capacitance reference value at the time of self-capacitance detection so that the energy of noise after IQ (in-phase and quadrature) demodulation does not change, but there is no capacitance reference value in the noise detection circuit and therefore the energy after IQ demodulation is reduced. In fig. 10, the horizontal axis represents frequency, and the vertical axis represents the magnitude of noise obtained by measurement. At each frequency point, the noise magnitude measured by the noise detection circuit can accurately represent the noise magnitude detected by the self-capacitance detection circuit, and from the goodness of fit of the two curves, the noise detection circuit provided by the embodiment can truly feed back the noise during self-capacitance detection.

With reference to the disclosure of the foregoing embodiment, the circuit provided in this embodiment may perform noise detection or self-capacitance detection, as shown in fig. 11, the control module 1100, the charge transfer module 1104 and the processing module 1105 are the same as or similar to those of the foregoing embodiment, and details are not repeated here, on the basis shown in fig. 6, a tenth switching unit is added to the driving module 1102 for controlling whether the first end of the capacitor to be detected is connected to the common-mode voltage, and an eleventh switching unit and a twelfth switching unit are added to the cancellation module 1103, where the eleventh switching unit is used for controlling whether the first end of the cancellation capacitor is connected to the common-mode voltage, the twelfth switching unit is used for controlling whether the second end of the cancellation capacitor is connected to the common-mode voltage, and the tenth switching unit, the eleventh switching unit and the twelfth switching unit are added on the basis of fig. 6 in order to detect noise, it may be switched to the noise detection circuit shown in fig. 3 or fig. 5. As shown in FIG. 11, increasing the enable signal EN controls the switch unit K₅、K₆、K₇、K₈、K₉When EN is high, these switches are enabled, the control signal of the corresponding switch unit is high and then connected to the contact 1, and when EN is low, these switches are disabled and in an off or high impedance state, and no matter how the corresponding control signal changes, these switches are not enabledThe fifth switch unit, the sixth switch unit, the seventh switch unit, the eighth switch unit and the ninth switch unit are controlled by adding an enable signal EN to the

contacts

1 and 2 so that EN is high during self-capacitance detection, the switches are enabled and connected to the

contacts

1 and 2, and the corresponding control signals are shown in FIG. 7. phi which is not shown in FIG. 7 during self-capacitance detection₅And phi₆Can be kept low, i.e. K₁₀、K₁₁、K₁₂And switching off to avoid influencing self-capacitance detection. When EN is low, K₅、K₆、K₇、K₈、K₉These switches are not enabled, and thus, K₅、K₆、K₇、K₈、K₉Are in an open state, i.e. not connected to contact 1, not connected to contact 2, even if K₅、K₆、K₇、K₈、K₉Also connected to contact 1 or 2, K is low due to the enable signal EN₅、K₆、K₇、K₈、K₉Connection to contact 1 or 2 does not work either, phi₁Can keep up with phi₅With the same timing, since K₅Not enabled, i.e. K₅In the off state, then at the time of noise detection, phi₁The timing of (A) being such that any timing does not affect the detection of noise, e.g. K₁Can be always turned off; when EN is low, Φ₆Always high, i.e. K₁₁、K₁₂Always connected to a common mode voltage. When EN is low, noise detection is performed, the timing of the switching unit can be referred to as shown in fig. 12, T in fig. 12 represents the period of self-capacitance detection, and the self-capacitance can be measured only after the time period T1-T8.

In this embodiment, the enable signal EN is added to control the switch unit K₅、K₆、K₇、K₈、K₉Enabling or not enabling is only an embodiment, and in addition, a switch unit K may be added₅、K₆、K₇、K₈、K₉Instead of enabling the signal, e.g. contact 3, when switching sheetYuan K₅、K₆、K₇、K₈、K₉When the contact 3 is contacted, the switch unit K₅、K₆、K₇、K₈、K₉The disconnection, which may be idle, i.e. not touching contact 1, nor contact 2, for example, may be referred to the second switching unit K in fig. 3 disclosed in the previous embodiment₂Of the contact 3.

In the present embodiment, the content of the foregoing embodiments is described with reference to the capacitance detection circuit, please refer to the timing diagrams of the self-capacitance detection circuit shown in fig. 13 and the capacitance detection circuit shown in fig. 14. The control module 1300, the driving module 1302, the cancellation module 1303, the charge transfer module 1304, and the processing module 1305 in fig. 13 are similar to those in the previous embodiments, and the technical principle thereof can be obtained by combining the timing diagram of fig. 14 and the similar analysis described above, and will not be described again here. Based on the self-capacitance detection circuit shown in fig. 13, how the noise detection circuit shown in fig. 15A detects noise is specifically described below.

Referring to the noise detection circuit shown in fig. 15A, in this embodiment, in order to save circuit area, the noise detection circuit and the self-capacitance detection circuit may share the same switch units, and the number of the switch units of the noise detection circuit is the same as that of the self-capacitance detection circuit shown in fig. 13.

In the noise detection circuit shown in fig. 15A, for the driving module, the second end of the capacitor to be tested is grounded, and the thirteenth switching unit K is used as two switching units of the driving module₁₃And a fourteenth switching unit K₁₄Are used for controlling whether the first end of the capacitor to be tested is connected with the common mode voltage. Thirteenth switching unit K in driving module in this embodiment₁₃And a fourteenth switching unit K₁₄The noise detection circuit and the self-capacitance detection circuit can be realized by only one switch unit, and the embodiment takes the sharing switch unit as an example to explain, so as to facilitate understanding how the noise detection circuit and the self-capacitance detection circuit share one circuit. In the noise detection circuit, the driving module in fig. 15A may be understood as switching Vcc connected to the thirteenth switching unit in the driving module in fig. 13 to a common mode voltage, and switching Vcc connected to the tenth switching unit in the driving module in fig. 13 to a common mode voltageThe GND connected with the four switch units is also switched to the common mode voltage. For the driving module of the noise detection circuit, when self-capacitance detection is required, the common-mode voltage connected with the thirteenth switching unit and the fourteenth switching unit is switched to Vcc and GND.

In the noise detection circuit of fig. 15A, for the cancellation module, the switch unit in the cancellation module is used to control whether the first end and the second end of the cancellation capacitor are connected to the common mode voltage, wherein the second switch unit K is used to control whether the common mode voltage is connected to the first end and the second end of the cancellation capacitor₂And the control circuit is also used for controlling whether the first end of the offset capacitor is connected with the first end of the capacitor to be detected. Compared with the self-capacitance detection circuit shown in fig. 6, the cancellation module in the noise detection circuit can be understood as switching the power supply (including Vcc, GND) of the cancellation module in the self-capacitance detection circuit to a common-mode voltage, i.e. to the fifteenth switching unit K₁₅Sixteenth switching unit K₁₆Seventeenth switching unit K₁₇And an eighteenth switching unit K₁₈The connected power supply is switched to a common mode voltage. For the cancellation module of the noise detection circuit, when the self-capacitance detection is needed, it will be connected to the fifteenth switch unit K₁₅Sixteenth switching unit K₁₆Seventeenth switching unit K₁₇And an eighteenth switching unit K₁₈The connected common mode voltages are switched to GND, Vcc, and GND corresponding to fig. 13, respectively.

The charge transfer module 1504 and the processing module 1505 in the noise detection circuit of fig. 15A are the same as or similar to those in the previous embodiments, and the description of this embodiment is omitted. In the noise detection, the timing diagram corresponding to fig. 15A may be fig. 14, and the following will exemplarily explain the operation principle of the noise detection circuit in fig. 15A in combination with the timing diagram.

FIG. 14 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 15A according to an embodiment of the present application; as shown in fig. 14, two periods T1-T4 constitute a noise detection cycle, T in fig. 14 represents a cycle of detecting self-capacitance, and the following brief description of the main technical processes for each period is as follows:

period t 4: the charge transfer module is reset, and the output is 0;

it is understood that the noise detection circuit in fig. 15A can be equivalent to the noise detection circuit in fig. 1C, and the timing chart shown in fig. 2A or 2B, specifically, the first control signal Φ in fig. 2A or 2B, can also be obtained according to fig. 14₁Can be understood as the first control signal Φ in fig. 14₁And a second control signal phi₂The second control signal Φ 2 in fig. 2A can be understood as the third control signal Φ in fig. 14 by performing an or operation₃Third control signal Φ in FIG. 2A₃Can be understood as the sixth control signal Φ in fig. 14₆. The reason why the timing sequence set in fig. 15A is the same as the timing sequence set in the self-capacitance detection circuit is that noise detection can be achieved by merely switching the power supplies connected to some of the switch units in fig. 13 without changing the timing sequence of the switch units in noise detection. As shown in fig. 14, the third control signal Φ₃And a sixth control signal phi₆Has a signal frequency of the first control signal phi₁Second control signal phi₂And a fourth control signal phi₄And a fifth control signal phi₅Twice as much. In this embodiment, for the noise detection circuit, the first control signal Φ₁Second control signal phi₂And a fourth control signal phi₄And a fifth control signal phi₅The detailed timing process is as follows:

period t1, thirteenth switching unit K₁₃On, the fifteenth switching unit K₁₅Seventeenth switching unit K₁₇In a closed state, a fourteenth switching unit K₁₄Sixteenth switching unit K₁₇Eighteenth switching unit K₁₈A second switch unit K₂Turning off the capacitor to be detected Cx, connecting Vcm to the first end of the capacitor to be detected Cx and connecting GND to the second end of the capacitor to be detected Cx, and connecting Vcm to the first end of the offset capacitor and connecting GND to the second end of the offset capacitorAnd the end is connected with Vcm, so that the capacitor Cx to be measured is charged. At the end of the period t1, the voltage of the capacitor Cx to be measured is Vcm (i.e., Vcm-GND), and the voltage of the cancellation capacitor Cc is 0 (i.e., Vcm-Vcm equals 0). At this time, the charge amount Q1 stored in the capacitance Cx to be measured is (Vcm-Vcm) × Cx, and the charge amount Q2 stored in the offset capacitance Cc is (Vcm-Vcm) × Cc is 0. At this time, since the sixth switching unit K₆Off, therefore, the output voltage Vout of the charge transfer module 1504 is 0.

Period t2, thirteenth switching unit K₁₃And a fourteenth switching unit K₁₄And a fifteenth switching unit K₁₅Sixteenth switching unit K₁₆Seventeenth switching unit K₁₇Off, second switching unit K₂Eighteenth switching unit K₁₈And in a closed state, the capacitance Cx to be measured is connected with the offset capacitance Cc. When no noise exists, the charge conservation law establishes that Vcm Cx + 0-Vx Cx + (Vx-Vxm) Cc, and the voltage Vx-Vcm of the capacitor to be measured is obtained. It should be noted that, if noise exists, for example, the interference source 1501 is used to simulate interference, and the interference source 1501 influences the capacitance Cx to be measured and the offset capacitance Cc, so that the voltage Vx of the capacitance Cx to be measured is not equal to Vcm, it can be understood that the interference of the interference source 1501 may charge or discharge the capacitance to be measured and the offset capacitance, so that the voltage Vx of the capacitance Cx to be measured is greater than or less than Vcm.

Period t4, fourth switching unit K₄The other switches are opened, the state of the other switches is kept consistent in the period t3, in addition, the second switch unit can be closed, the charge transfer module 1504 is reset, and the output voltage Vout of the charge transfer module 804 becomes 0.

In the above working process, the charge transfer occurs in the time period t3, and according to the voltage Vx across the capacitance Cx to be measured at the end of the time period t2, there are several situations:

if Vx>V_CMThe capacitance Cx to be measured and the offset capacitance Cc are simultaneously transferred to the charge transfer module 1504Shifting charges until the voltage of the capacitor Cx to be measured reaches the common mode voltage V_CM. In this process, the output voltage Vout of the charge transfer module 1504 is a negative voltage, but the output of the charge transfer module 1504 may also be a positive voltage due to the influence of interference sources on the charge transfer module.

If Vx is equal to V_CMIf the charge transferred between the capacitance Cx to be measured and the offset capacitance Cc and the charge transfer module 1504 is 0, the output voltage Vout of the charge transfer module 1504 is also 0, and at this time, the circuit reaches a complete offset state.

If Vx<V_CMThe charge transfer module 1504 may pass through a feedback network (R)_fAnd C_f) Charging the capacitor Cx and the offset capacitor Cc to be measured until the voltage of the capacitor Cx and the offset capacitor Cc to be measured reaches the common-mode voltage V_CM. In this process, the output voltage Vout of the charge transfer module 1504 is a positive voltage, but the output of the charge transfer module 1504 may also be a negative voltage due to the influence of interference sources on the charge transfer module.

The output voltage of the charge transfer module 1504 is filtered by the AAF in the processing module 1505, sent to the ADC for sampling, then subjected to quadrature demodulation by the DSP, and the obtained raw data is sent to the CPU for noise calculation to obtain the noise level.

With reference to the foregoing embodiment, in this embodiment, the charge transfer module may also include a capacitance feedback and switch unit, please refer to fig. 15B, and a corresponding timing diagram thereof may refer to fig. 14, and it is different from fig. 15A that the feedback network of the charge transfer module includes a feedback capacitance Cf and a switch unit, specifically, the feedback network includes two feedback capacitances Cf, a twenty-fourth switch unit and a twenty-fifth switch unit, and the twenty-fourth switch unit and the twenty-fifth switch unit share the same control signal Φ₇Where it is to be noted that₇May be in a closed state at time t1, or may be in a closed state at time t2, at time t4In the closed state, phi at the stage t3₇In the off state. In this embodiment, the twenty-fourth switching unit and the twenty-fifth switching unit are provided to realize resetting of the feedback capacitor, and avoid a situation where the output voltage is constant after saturation due to too much charge accumulation. Phi is a₇Reference may be made to the timing sequence of FIG. 14, where φ is only closed during time t1₇Can be understood as phi₁And phi₂The logic or operation is performed, and other modules and timings in this embodiment are the same as or similar to those in the foregoing embodiment, and are not described herein again.

In conjunction with the foregoing embodiments, in the present embodiment, a circuit as shown in fig. 16 is provided, which can perform both self-capacitance detection and noise detection. The control module 1600, the driving module 1602, the cancellation module 1603, the charge transfer module 1604 and the processing module 1605 in fig. 16 are similar to the foregoing embodiments, and in addition, the technical principle thereof can be obtained by combining the corresponding timing diagram of fig. 17 and the similar analysis, and the details are not repeated herein. Based on the self-capacitance detection circuit shown in fig. 13, how the noise detection circuit shown in fig. 16 detects noise and how self-capacitance detection is performed will be described in detail below.

Referring to the noise detection circuit shown in fig. 16, in the present embodiment, in order to save circuit area, the noise detection circuit shown in fig. 16 adds three switch units, namely a nineteenth switch unit K, on the basis of the self-capacitance detection circuit shown in fig. 13₁₉Twentieth switch unit K₂₀And twenty-first switching unit K₂₁Thus, when noise detection is performed, the nineteenth switching unit K₁₉Twentieth switch unit K₂₀And twenty-first switching unit K₂₁Will selectively turn on the common mode voltage, when performing the self-capacitance detection, the nineteenth switch unit K₁₉Twentieth switch unit K₂₀And twenty-first switching unit K₂₁Will be turned off, and the states of the switching units in the respective modules are controlled by the control module 1600 to achieve noise detection and self-capacitance detection.

In the noise detection circuit of fig. 16, for the driving module, the second terminal of the capacitor to be tested is grounded, and the driving module is drivenAnd the nineteenth switch unit of the movable module is used for controlling whether the first end of the capacitor to be tested is connected with the common-mode voltage or not. The control module 1600 in fig. 16 can control the thirteenth switch module, the fourteenth switch module and the nineteenth switch module to respectively control whether the first end of the capacitor Cx to be detected is connected to Vcc, GND and Vcm, so as to complete noise detection according to the timing sequence of fig. 17, and in addition, can also complete self-capacitance detection according to the timing sequence of fig. 14, and when completing self-capacitance detection according to the timing sequence of fig. 14, the nineteenth switch unit K is used to complete self-capacitance detection₁₉Twentieth switch unit K₂₀And twenty-first switching unit K₂₁Will be turned off.

In the noise detection circuit in fig. 16, for the cancellation module 1603, the twentieth switch unit in the cancellation module is used to control whether the first end of the cancellation capacitor is connected to the common mode voltage, and the twenty-first switch unit in the cancellation module is used to control whether the second end of the cancellation capacitor is connected to the common mode voltage. In fig. 16, the cancellation module 1603 may be configured to control whether the first end of the cancellation capacitor Cc is connected to GND, Vcc, and Vcm through a fifteenth switch module, a sixteenth switch module, and a twentieth switch module, the cancellation module 1603 may also be configured to control whether the second end of the cancellation capacitor Cc is connected to Vcc, GND, and Vcm through a seventeenth switch module, an eighteenth switch module, and a twenty first switch module, respectively, and the cancellation module 1603 may also be configured to control whether the first end of the cancellation capacitor Cc is connected to the first end of the capacitor Cx to be detected through a fifth switch module. The charge transfer module 1604 and the processing module 1605 in fig. 16 are the same as or similar to those described in the previous embodiments, and are not described herein again.

In the noise detection, the timing chart corresponding to fig. 16 may be fig. 17, and the following describes an exemplary operation principle of the noise detection circuit in fig. 16 in combination with the timing chart.

FIG. 17 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 16 according to an embodiment of the present application; as shown in fig. 17, two periods T1-T4 constitute a period of noise detection, where T represents a period of self-capacitance detection, and the main technical processes for each period are briefly described as follows:

period t 1: charging the capacitor Cx to be measured through the common-mode voltage, and connecting the common-mode voltage to two ends of the offset capacitor Cc;

period t 4: the charge transfer module is reset, and the output is 0;

it is understood that the noise detection circuit in fig. 16 may be equivalent to the noise detection circuit in fig. 1D when detecting noise, and according to fig. 16 and 17, the timing chart shown in fig. 2A, specifically, the first control signal Φ in fig. 2A, may also be obtained₁Can be understood as the seventh control signal Φ in fig. 17₇Second control signal Φ in FIG. 2A₂Can be understood as the seventh control signal Φ in fig. 17₇Third control signal Φ in FIG. 2A₃Can be understood as the sixth control signal Φ in fig. 17₆. In FIG. 17,. phi.₁、Φ₂、Φ₄And phi₅Remains low, K₁₃、K₁₄、K₁₅、K₁₆、K₁₇、K₁₈These switches are turned off. For self-capacitance detection and noise detection, phi₃And phi₆Same as the timing of phi₇Corresponding to phi in FIG. 14₁And phi₂Is obtained by performing OR operation to obtain phi₈Is always kept high. The noise detection circuit is analyzed in conjunction with the specific switching state at each time interval.

Period t1, nineteenth switching element K₁₉Conducting the thirteenth switching unit K₁₃And a fourteenth switching unit K₁₄In an off state, a fifteenth switching unit K₁₅Sixteenth switching unit K₁₆Seventeenth switching unit K₁₇Eighteenth switching unit K₁₈Off, twentieth switching unit K₂₀And twenty-first switching unit K₂₁And conducting, so that the first end of the capacitor Cx to be measured is connected with Vcm and the second end of the capacitor Cx to be measured is connected with GND, the first end of the offset capacitor is connected with Vcm and the second end of the offset capacitor is connected with Vcm, and finally the capacitor Cx to be measured is charged. At t1At the end of the segment, the voltage of the capacitor Cx to be measured is Vcm (i.e. Vcm-GND), and the voltage of the cancellation capacitor Cc is 0 (i.e. Vcm-Vcm equals 0). At this time, the charge amount Q1 stored in the capacitance Cx to be measured is (Vcm-Vcm) × Cx, and the charge amount Q2 stored in the offset capacitance Cc is (Vcm-Vcm) × Cc is 0. At this time, since the sixth switching unit K₆Off, therefore, the output voltage Vout of the charge transfer module 1504 is 0.

Period t2, thirteenth switching unit K₁₃And a fourteenth switching unit K₁₄And a fifteenth switching unit K₁₅Sixteenth switching unit K₁₆Seventeenth switching unit K₁₇Eighteenth switching unit K₁₈Nineteenth switch unit K₁₉Twentieth switch unit K₂₀In the off state, the fifth switching unit K₅And in a closed state, the first end of the capacitance Cx to be measured is connected with the first end of the offset capacitance Cc. When no noise exists, the charge conservation law establishes that Vcm Cx + 0-Vx Cx + (Vx-Vxm) Cc, and the voltage Vx-Vcm of the capacitor to be measured is obtained. It should be noted that, if there is noise, for example, an interference source is used to simulate interference, and the interference source affects charges stored in the capacitance Cx to be measured and the offset capacitance Cc, so that the voltage Vx of the capacitance Cx to be measured is not equal to Vcm, it can be understood that the interference of the interference source can charge or discharge the capacitance to be measured and the offset capacitance, so that the voltage Vx of the capacitance Cx to be measured is greater than or less than Vcm.

Period t3, fourth switching unit K₄And when the other switches are turned on, the state of the other switches is kept consistent with the state in the time period t2, and if the voltage Vx of the capacitor Cx to be measured is greater than or less than Vcm, charge transfer is performed between the capacitor Cx to be measured, the offset capacitor Cc and the charge transfer module 1604.

Period t4, fourth switching unit K₄The other switches are turned off, the other switches are kept in agreement with the state of the t3 period, the charge transfer module 1604 is reset, and the output voltage Vout of the charge transfer module 804 becomes 0. In addition, the fifth switching unit may also be closed during the period t 4.

if Vx>V_CMThe capacitor Cx and the offset capacitor Cc to be tested transfer charges to the charge transfer module 1604 simultaneously until the voltage of the capacitor Cx to be tested reaches the common mode voltage V_cm. In this process, the output voltage Vout of the charge transfer module 1604 is a negative voltage, and in addition, the output voltage Vout of the charge transfer module 1604 may also be a positive voltage due to the influence of the interference source on the charge transfer module 1604.

If Vx is equal to V_CMIf the charge transferred between the capacitance Cx to be measured and the offset capacitance Cc and the charge transfer module 1604 is 0, the output voltage Vout of the charge transfer module 1604 is also 0, and the circuit reaches the complete offset state.

If Vx<V_CMThe charge transfer module 1604 may pass through a feedback network (R)_fAnd C_f) Charging the capacitor Cx and the offset capacitor Cc to be measured until the voltage of the capacitor Cx and the offset capacitor Cc to be measured reaches the common-mode voltage V_cm. In this process, the output voltage Vout of the charge transfer module 1604 is a positive voltage, and in addition, the output voltage Vout of the charge transfer module 1604 may also be a negative voltage due to the influence of the interference source on the charge transfer module 1604.

Referring to fig. 18, fig. 18 provides a circuit for both noise detection and self-capacitance detection, the control module 1800, the driving module 1802, the cancellation module 1803, the charge transfer module 1804, and the processing module 1805 in fig. 18 are similar to the foregoing embodiments, except that a power switching module is added to fig. 18, and the technical principle of the circuit can be obtained by combining the corresponding timing diagram of fig. 19 and the similar analysis, and the following describes in detail how the noise detection circuit shown in fig. 18 detects noise and how self-capacitance detection is performed.

For the driving module 1802, during noise detection, the control module is configured to control the driving module 1802 to charge the capacitor to be detected in the first period, and the control module may be further configured to control the cancellation module to charge the cancellation capacitor in the first period or enable two ends of the cancellation capacitor to be charged in the first periodAre all connected with a common mode voltage; the control module is also used for controlling the counteracting module to enable the first end of the counteracting capacitor to be connected with the first end of the capacitor to be detected in the second time period and the third time period; the control module is further used for controlling the charge transfer module to carry out charge transfer on the charges in the cancellation capacitor and the capacitor to be tested in a third time interval so as to output the output voltage Vout. In this embodiment, the control module is further configured to control the power supply switching module 1806, so that noise detection and self-capacitance detection can be implemented. Wherein Vp can be selected from Vcc and Vcm, V_NSelectable between GND and Vcm, switch K₂₂And K₂₃Common control signal phi₇。Φ₇At low time, Vp and V_NVcc and GND are connected respectively, and in this case, a self-capacitance detection mode can be referred to as time period t9-t16 shown in FIG. 19; phi₇At high time, Vp and V_NVcm may be connected all together, this time in the noise detection mode, and reference may be made to the period t1-t8 shown in fig. 19. The timing sequence shown in fig. 19 can be understood that, when the noise detection circuit performs noise detection in the time period t1-t8, the magnitude of noise can be obtained through the output voltage, and when the self-capacitance detection circuit performs self-capacitance detection in the time period t9-t16, and the self-capacitance value can be obtained through the output voltage, in this embodiment, the power supply switching module is added, so that the noise detection circuit and the self-capacitance detection circuit can share a circuit to realize time-sharing detection, for example, as shown in fig. 19, noise is detected in the time period t1-t8, and capacitance is detected in the time period t9-t 16. The drive module and the cancellation module include 3 pairs of Vp and VN sharing a power selection module, or each pair of Vp and V_NThe power ports respectively use one power selection module. When 3 pairs of Vp and V_NWhen the power switching module 1806 is shared, the switch impedance is higher; when each pair of Vp and V_NWhen one power selection module is used for each power port, the complexity of circuit design is increased, and the switch impedance is relatively low.

In the noise detection circuit shown in fig. 18, the processing module may also be connected to the control module, and when the control module controls the power switching module to switch the power supplies of the driving module, the cancellation module, and the charge transfer module to implement noise detection or self-capacitance detection, the control module may also notify the processing module, for example, may send a high level or a low level to the processing module, so that the processing module may know whether the output voltage represents the noise magnitude or the capacitance value.

Compared with the scheme of fig. 16, the scheme reduces one control signal, the control sequence is relatively simple, but the power supply ports of the driving module and the cancellation module are connected in series by using two switches, and the driving impedance is higher. The power supply port in fig. 16 is a switch for controlling on and off, which has the advantage of lower driving impedance, but the control sequence is more complicated.

FIG. 19 is a timing diagram illustrating the operation of the noise detection circuit of FIG. 18 according to an embodiment of the present application; as shown in fig. 19, two time periods T1-T4 form a noise detection half period, where T may represent a noise detection period or a self-capacitance detection period, and the analysis of each time period is similar to the previous embodiment and is not repeated here.

Accurate noise measurement is beneficial to improving the accuracy of self-capacitance detection, and the main anti-interference methods of capacitance detection comprise driving voltage improvement, detection time increase, interference source distance, shielding and frequency hopping. The two methods of increasing the driving voltage and increasing the detection time cannot avoid interference, and only the hard resistance capability of the detection system is increased. Also, there is a limit to increase the driving voltage, and the highest driving voltage is fixed in various applications. And increasing the detection time results in increased power consumption. The method of keeping away from the interference source, shielding and frequency hopping is a method of avoiding interference, but the method of keeping away from the interference source and shielding is sometimes limited by product size and application form and cannot be implemented well. The frequency hopping is a flexible and effective anti-interference method, and the frequency with larger interference is avoided, and the frequency with smaller noise is selected as the working frequency, so that the signal-to-noise ratio of the capacitance detection can be obviously improved, and the sensitivity and the reliability are ensured.

In combination with the disclosure of the foregoing embodiment, this embodiment provides a self-capacitance detection method, which is used to determine an operating frequency of a self-capacitance detection circuit, that is, select an appropriate operating frequency, so that noise during self-capacitance detection is small. Specifically, referring to fig. 20, the method includes the following steps:

s2001: detecting the amplitude of the noise of the self-capacitance detection circuit operating at the first frequency by using the noise detection circuit provided by the foregoing embodiment;

s2002: judging whether the amplitude of the noise is lower than a preset noise threshold value or not; if the amplitude of the noise is lower than the preset noise threshold, go to step S2002A; if the amplitude of the noise is lower than the preset noise threshold, go to step S2002B;

S2002A: the self-capacitance detection circuit performs self-capacitance detection at a first frequency

S2002B: the noise detection circuit provided by the foregoing embodiment is used to detect the amplitude of the noise of the self-capacitance detection circuit operating at the second frequency until the second frequency is determined such that the amplitude of the noise is lower than the preset noise threshold, and the self-capacitance detection circuit performs self-capacitance detection at the second frequency.

In step S2001, when the noise detection circuit detects the noise of the self-capacitance detection circuit operating at the first frequency, the operating frequency of the self-capacitance detection circuit is the first frequency, and when the noise is detected, the demodulation frequency of the noise detection is also the first frequency, and step S2001 may also be understood as detecting the amplitude of the noise detection circuit operating at the first frequency by using the noise detection circuit provided in the foregoing embodiment. The timing sequence of the switching unit of the noise detection circuit may be the same as the switching timing sequence of the self-capacitance detection circuit, so as to ensure that the amplitude of the noise of the self-capacitance detection circuit is acquired more accurately. Taking the timing of fig. 19 as an example, if the noise of the self-capacitance detection circuit at the timing of t9-t16 is to be detected, the timing of the noise detection circuit may be set as shown at t1-t 8. In addition, it can be understood that, as for the demodulation frequency of the processing module, the demodulation frequency of the processing module of the noise detection circuit and the self-capacitance detection circuit is the same. Specifically, referring to fig. 19 for S2002A, if the noise amplitude obtained by the test in the time period t1-t8 is smaller than the preset noise threshold, the self-capacitance detection is performed at the first frequency in the time period t9-t16, so that the switching timing of the self-capacitance detection circuit is the same as the switching timing of the noise detection circuit, and the demodulation frequency of the self-capacitance detection circuit is the same as the demodulation frequency of the noise detection circuit, so that the interference received by the self-capacitance detection circuit when the self-capacitance detection circuit operates at the first frequency is smaller than the preset noise threshold. In addition, since the switching timing of the self-capacitance detection circuit is the same as the switching timing of the noise detection circuit, in the present embodiment, the lengths of the ninth period, the tenth period, the eleventh period, and the twelfth period are equal to the lengths of the first period, the second period, the third period, and the fourth period, respectively.

In this embodiment, in combination with the disclosure of the foregoing embodiments, in the case where the fourth period is not provided, if it is determined from the output voltage of the period t1+ t2+ t3 that the amplitude of the noise is lower than the preset noise threshold, the self-capacitance detection circuit may perform self-capacitance detection at a frequency of f ═ 1/(t1+ t2+ t 3). If it is desired to test the noise of the self-contained detection circuit with the operating frequency f being 1/(t1+ t2+ t3+ t1+ t2+ t3), the magnitude of the noise may be determined according to the output voltage of the charge transfer circuit during the (t1+ t2+ t3+ t1+ t2+ t3) period of time, at which time the noise detection circuit operates according to the timing of t1+ t2+ t3+ t1+ t2+ t 3. In the case where the fourth period is set, if it is desired to test the noise of the self-capacitance detection circuit whose operating frequency is f ═ 1/(t1+ t2+ t3+ t4+ t1+ t2+ t3+ t4), the magnitude of the noise may be determined from the output voltage of the charge transfer circuit during the period (t1+ t2+ t3+ t4+ t1+ t2+ t3+ t4) from the noise detection circuit, and if the magnitude of the noise is lower than a preset noise threshold, the self-capacitance detection circuit may perform self-capacitance detection at the operating frequency f ═ 1/(t1+ t2+ t3+ t4+ t1+ t2+ t3+ t 4).

In this embodiment, if at the present time, the operating frequency of the self-capacitance detection circuit is the first frequency, the noise detection circuit provided in the foregoing embodiment is used to detect the amplitude of the noise of the self-capacitance detection circuit operating at the first frequency, so as to determine whether the first frequency is the proper operating frequency of the self-capacitance detection circuit, that is, determine whether the noise at the first frequency is smaller than a preset noise threshold, and if the noise exceeds the preset noise threshold, the noise detection circuit may test the noise at other operating frequencies, so as to find the proper operating frequency of the self-capacitance detection circuit. In this embodiment, when the noise detection circuit detects the amplitude of the noise, the noise under the operating frequency of the self-capacitance detection circuit at the current time is preferentially detected, that is, the operating frequency of the self-capacitance detection circuit is first determined to be the first frequency, and then the noise detection circuit detects the amplitude of the noise of the self-capacitance detection circuit operating under the first frequency. Thus, if the noise at the first frequency meets the requirement, the noise detection circuit does not need to detect the noise at other frequencies, and the self-capacitance detection circuit continues to perform self-capacitance detection at the first frequency.

Specifically, referring to fig. 21, the method includes the following steps:

s2101: measuring a noise magnitude N1 of a noise detection circuit operating at a frequency of f1 using the noise detection circuit;

s2102: judging whether N1 is smaller than the preset noise threshold TH1, if N1 is smaller than the preset noise threshold TH1, executing step S2002A, otherwise executing step S2002B;

S2102A: the self-capacitance detection circuit performs self-capacitance detection by taking f1 as a working frequency;

S2102B: measuring a noise magnitude N2 of a noise detection circuit operating at a frequency of f2 using the noise detection circuit;

s2103: judging whether N2 is smaller than the preset noise threshold TH 1; if N2 is smaller than the preset noise threshold TH1, go to step S2003A, otherwise go to step S2003B;

S2103A, the self-capacitance detection circuit carries out self-capacitance detection by taking f2 as the working frequency;

S2103B: measuring a noise magnitude N3 of a noise detection circuit operating at a frequency of f3 using the noise detection circuit;

s2104, judging whether N3 is smaller than a preset noise threshold TH 1; if N3 is less than the preset noise threshold TH1, go to step S2004A, otherwise go to step S2004B;

S2104A, the self-capacitance detection circuit performs self-capacitance detection with f3 as the working frequency;

S2104B: measuring the noise magnitude N4 of the noise detection circuit operating at the frequency f4 by using the noise detection circuit until finding the frequency fx so that the Nx measured at the frequency fx is smaller than TH1, and determining the operating frequency of the self-capacitance detection to be fx; or if N1, N2 and N3 … … Nn are all larger than the preset noise threshold, comparing the sizes of N1, N2 and N3 … … Nn and determining the minimum noise, and if Nx is the minimum value, determining the working frequency of the self-capacitance detection to be fx and increasing the time of the self-capacitance detection. It will be appreciated that the signal-to-noise ratio of self-contained detection is improved when the time of self-contained detection is increased.

In step S2104B, the time for self-content detection may be doubled.

In combination with the disclosure of the foregoing embodiment, this embodiment provides a self-capacitance detection method, which is used to select an operating frequency of a self-capacitance detection circuit, so that the self-capacitance detection circuit can operate at a frequency with relatively low noise, and with the noise detection circuit disclosed in the foregoing embodiment, the noise magnitude received by the circuit at a certain operating frequency can be obtained, and based on this, the operating frequency with relatively low noise can be selected, specifically, refer to fig. 22, and the method includes the following steps:

s2201: detecting a noise magnitude N1-Nm of a noise detection circuit operating at a frequency f1-fm using the noise detection circuit;

s2202: comparing the sizes of N1-Nm;

s2203: and selecting the frequency fx corresponding to the minimum noise Nx as the working frequency of the self-capacitance detection circuit.

In this embodiment, the magnitude of the noise may be understood as the amplitude of the noise, the operating frequency of the self-capacitance detection circuit may be understood as the operating frequency of the processing module of the self-capacitance detection circuit, for example, the demodulating operating frequency of the processing module, specifically, may be referred to as the demodulating frequency, and when the noise detection circuit is used to measure the noise magnitude of the noise detection circuit operating at the frequency f1, the demodulating operating frequency of the processing module of the noise detection circuit is also f 1.

In combination with the disclosure of the foregoing embodiments, the present embodiment provides a self-contained detection method, please refer to fig. 23, which includes the following steps:

s2301: detecting, using a noise detection circuit, an amplitude N1 of noise of the noise detection circuit operating at a first frequency f 1;

s2302: judging whether N1 is smaller than a preset noise threshold TH 1; if so, go to step 2202, 2202A; if not, go to step S2202 and 2202B;

S2302A: the self-capacitance detection circuit performs capacitance detection at a first frequency;

S2302B: continuously detecting the amplitudes of the noise under other frequencies until the frequency fx when the frequency is smaller than the preset noise threshold value is determined, and then carrying out capacitance detection on the self-capacitance detection circuit by fx; or increase the detection time of the self-contained detection circuit.

When the detection time of the self-capacitance detection circuit is increased, the self-capacitance detection circuit can further process the detection result by using the results of multiple detections so as to make the detection result more accurate.

Fig. 24 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present disclosure; as shown in fig. 24, it includes a touch sensor 2401, a touch chip 2402, and a host 2403. The touch sensor 2401 has a double-layer structure, and comprises a driving channel Tx and a sensing channel Rx, and the basic capacitance of the driving channel Tx and the sensing channel Rx to the system ground is marked as C1-C5 and C6-C10. During the self-capacitance detection, the touch chip 2402 scans the capacitance of each channel (driving channel, sensing channel) to the system ground, and calculates the capacitance variation of each channel to the system ground. When a finger approaches or touches the touch screen, the capacitance of the channel of the finger approaching or touching position to the system ground becomes large. As shown in FIG. 24, if the capacitance between the finger and the driving channel Tx is Cd, the capacitance between the finger and the sensing channel Rx is Cs. For example, when a finger approaches the driving path Tx2 and the sensing path Rx3, since a human body is connected to the system ground as a conductor, the capacitance of the driving path Tx2 to the system ground becomes C2+ Cd, and the capacitance of the sensing path Rx3 to the system ground becomes C8+ Cs. The touch chip 2402 detects that the capacitance of the driving channel Tx2 and the sensing channel Rx3 to the system ground is increased, and the capacitance of the other channels to the system ground is unchanged or approximately unchanged or smaller, so that the touch position at the intersection of the driving channel Tx2 and the sensing channel Rx3 can be calculated, and the coordinates of the touch position at the intersection can be sent to the host 2403 to realize the touch operation of various functions.

In this embodiment, the noise detection circuit is specifically configured on the touch chip 2402 shown in fig. 24, and therefore, it can be understood that the touch chip 2402 includes the capacitance detection circuit described in the above embodiments.

Fig. 25 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present disclosure; as shown in fig. 25, the touch sensor and the touch chip in this embodiment are the same as or similar to those in the previous embodiments and are not repeated herein. Taking the example of measuring the noise of the electrode Tx5 as an example, the capacitance to be measured is specifically the capacitance formed between the electrode Tx5 and GND in the figure, and this embodiment is only illustrated by taking the example of measuring the capacitance formed by one electrode, and the other electrodes are not described again.

The embodiment of the present application further provides an electronic device, which includes the touch chip described in any embodiment of the present application.

In the above embodiments, although the switch units are described as a single switch, the switch units may be realized as a circuit combination structure, and the components may be any electronic components having on/off functions, such as MOS transistors.

In addition, when the touch detection is implemented based on the mutual capacitance detection, if the basic capacitance of the mutual capacitance is relatively large so as to affect the change rate of the mutual capacitance, the idea of the following embodiments of the present application may also be applied.

The electronic device of the embodiments of the present application exists in various forms, including but not limited to:

(1) mobile communication devices, which are characterized by mobile communication capabilities and are primarily targeted at providing voice and data communications. Such terminals include smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.

(2) The ultra-mobile personal computer equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include PDA, MID, and UMPC devices, such as ipads.

(3) Portable entertainment devices such devices may display and play multimedia content. Such devices include audio and video players (e.g., ipods), handheld game consoles, electronic books, bluetooth headsets, as well as smart toys and portable car navigation devices.

(4) The server is similar to a general computer architecture, but has higher requirements on processing capability, stability, reliability, safety, expandability, manageability and the like because of the need of providing highly reliable services.

(5) And other electronic devices with data interaction functions.

It should be noted that the above method embodiments of the present application may be applied to or implemented by a processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method embodiments may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

It will be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), double data rate SDRAM, enhanced SDRAM, SLDRAM, Synchronous Link DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A noise detection circuit, comprising: the device comprises a control module, a driving module, a counteracting module, a charge transfer module and a processing module; the drive module with offset the module and be connected, offset the module with charge transfer module connects, charge transfer module with processing module connects, control module with the drive module, offset the module and charge transfer module connects, its characterized in that includes:

the control module is used for controlling the driving module to charge the capacitor to be tested by using a first voltage in a first period, and controlling the offset module to charge the offset capacitor by using the first voltage in the first period or connecting two ends of the offset capacitor with the first voltage;

the control module controls the cancellation module to enable the first end of the capacitor to be detected to be connected with the first end of the cancellation capacitor in a second time period;

the control module controls the charge transfer module to convert the charges of the capacitor to be detected and the offset capacitor in a third time period to generate an output voltage;

the first, second, and third periods are consecutive in time, the charge transfer module comprising an amplifier; the inverting input end of the amplifier is connected with the first voltage;

the processing module is used for determining the size of noise at least according to the output voltage.

2. The noise detection circuit of claim 1, wherein the first voltage is a common mode voltage.

3. The noise detection circuit according to claim 1 or 2, wherein the driving module includes a first switch unit, and the control module is further configured to control the first switch unit to be in a closed state, so that the driving module charges the capacitor to be tested with the first voltage during the first period;

when the first switch unit is in a closed state, the first end of the capacitor to be tested is connected with the first voltage; and the second end of the capacitor to be tested is connected with the ground voltage.

4. The noise detection circuit of claim 3, wherein the cancellation module comprises a second switch unit and the cancellation capacitor, and the control module is further configured to control the second switch unit to be in a closed state at the first period;

when the second switch unit is in a closed state, the offset capacitor is charged, a first end of the offset capacitor is connected with the first voltage, and a second end of the offset capacitor is connected with the ground voltage; alternatively, the first and second electrodes may be,

5. The noise detection circuit according to claim 4, wherein the cancellation module further includes a third switching unit, and the control module is further configured to control the third switching unit to be in a closed state during the second period of time so as to connect the first end of the capacitor to be tested with the first end of the cancellation capacitor;

when the third switch unit is in a closed state, the first end of the offset capacitor is disconnected from the first voltage, and the first end of the capacitor to be tested is disconnected from the first voltage.

6. The noise detection circuit according to claim 1 or 2, wherein when the charges of the capacitor to be measured and the cancellation capacitor are converted, the first end of the capacitor to be measured, the first end of the cancellation capacitor, and the non-inverting input terminal of the amplifier are connected.

7. The noise detection circuit according to any one of claims 1 to 6, wherein the control module controls the charge transfer module so that the charge transfer module is reset during a fourth period; the first period, the second period, the third period, and the fourth period are consecutive in time.

8. The noise detection circuit according to claim 7, wherein the charge transfer module further includes a fourth switching unit that is in a closed state in the third period so that the output voltage is generated by converting charges of the capacitance to be measured and the cancellation capacitance; the fourth switching unit is in an off state at the fourth period to reset the charge transfer module.

9. The noise detection circuit according to claim 7 or 8, wherein in the first period, the voltage of the capacitor to be measured is increased to the first voltage, the voltage of the cancellation capacitor is increased to the first voltage, or the voltage of the cancellation capacitor is 0; in the second period, the connection state of the second end of the cancellation capacitor is the same as the connection state of the second end of the cancellation capacitor in the first period; the output voltage of the charge transfer module increases or decreases to 0 during the first period and the second period, and the output voltage of the charge transfer module decreases or increases to 0 during the fourth period.

10. The noise detection circuit according to any one of claims 7 to 9, wherein the processing module comprises a filter, an analog-to-digital converter and a digital signal processor; the filter filters the output voltage of the charge transfer module; the analog-to-digital converter performs analog-to-digital conversion on the filtered output voltage; the digital signal processor is used for demodulating the output voltage after the analog-to-digital conversion, and the reference frequency used for demodulation is the reciprocal of a noise detection period; the noise detection period is equal to an integer multiple of a noise detection half-period, the noise detection half-period being a sum of the first time period, the second time period, the third time period, and the fourth time period; or the noise detection half period is the sum of the first period, the second period and the third period.

11. The noise detection circuit of claim 10, wherein the processing module determines the magnitude of the noise based at least on the output voltage comprises: the processing module determines the amplitude of noise according to the output voltage of the charge transfer module in the noise detection period.

12. The noise detection circuit according to claim 1, wherein the driving module includes a thirteenth switching unit, a fourteenth switching unit, and a nineteenth switching unit; the control module is further configured to control the thirteenth switching unit, the fourteenth switching unit, and the nineteenth switching unit to perform noise detection or self-capacitance detection; when the noise detection is performed, the control module is configured to control the nineteenth switching unit so that the first end of the capacitor to be detected is connected to the first voltage in the first period; when the self-capacitance detection is performed, the control module is used for controlling the thirteenth switching unit and the fourteenth switching unit so that the first end of the capacitor to be detected is connected with the ground voltage or the power supply voltage; and the second end of the capacitor to be tested is connected with the ground voltage.

13. The noise detection circuit of claim 12, wherein the cancellation module comprises a fifteenth switching unit, a sixteenth switching unit, a twentieth switching unit, a seventeenth switching unit, an eighteenth switching unit, and a twenty-first switching unit; the control module is further configured to control the fifteenth switching unit, the sixteenth switching unit, the twentieth switching unit, the seventeenth switching unit, the eighteenth switching unit, and the twenty-first switching unit to perform the noise detection or the self-capacitance detection; when the noise detection is performed, the control module is configured to control the twentieth switching unit and the twenty-first switching unit to connect the first terminal and the second terminal of the cancellation capacitor to the first voltage during the first period, or to connect the first terminal of the cancellation capacitor to the first voltage and connect the second terminal of the cancellation capacitor to the ground voltage during the first period; when the self-capacitance detection is performed, the control module is configured to control the fifteenth switching unit, the sixteenth switching unit, the seventeenth switching unit, and the eighteenth switching unit so that the first end and the second end of the cancellation capacitor are connected to the ground voltage or the power supply voltage.

14. The noise detection circuit of claim 13, wherein the cancellation module further includes a fifth switch unit, and the control module is further configured to control the fifth switch unit such that the first end of the capacitor to be tested is connected to the first end of the cancellation capacitor during the second period and the third period, and the first end of the capacitor to be tested is disconnected from the first end of the cancellation capacitor during the first period.

15. The noise detection circuit according to claim 1, further comprising a power switching module, wherein the power switching module is connected to the control module, the driving module, and the cancellation module, and is configured to switch the first voltage, so that the control module controls the driving module, the cancellation module, the charge transfer module, and the processing module to perform self-capacitance detection or noise detection, and when performing the self-capacitance detection, the control module is further configured to control the cancellation capacitor to perform charge cancellation processing on the capacitor to be detected.

16. The noise detection circuit of claim 15, wherein the power switching module is configured to switch two first voltages connected to the first end of the capacitor to be detected into a power voltage and the ground voltage, respectively, during the self-capacitance detection; the power supply switching module is further configured to switch two first voltages connected to the first end of the cancellation capacitor to the power supply voltage and the ground voltage, respectively; the power supply switching module is further configured to switch two first voltages connected to the second end of the cancellation capacitor to the power supply voltage and the ground voltage, respectively.

17. The noise detection circuit according to claim 15 or 16, wherein the power supply switching module is configured to switch a power supply voltage connected to the first end of the capacitor to be detected and the ground voltage to the first voltage during noise detection; the power supply switching module is further used for switching a power supply voltage connected with the first end of the offset capacitor and the ground voltage into the first voltage; the power supply switching module is further configured to switch a power supply voltage connected to the second end of the cancellation capacitor and the ground voltage to the first voltage.

18. The noise detection circuit of claim 1, wherein the driving module, the cancellation module, and the charge transfer module each include at least one switching unit; when noise detection is carried out, the time sequence of the switch units of the driving module, the counteracting module and the charge transfer module is the same as the time sequence of the switch units of the driving module, the counteracting module and the charge transfer module when self-capacitance detection is carried out.

19. The noise detection circuit of any of claims 1-18, wherein the amplifier is a single-ended amplifier.

20. The noise detection circuit according to any one of claims 1 to 18, wherein the amplifier is a fully differential amplifier.

21. A self-contained test method, comprising: detecting an amplitude of noise of the noise detection circuit operating at a first frequency using the noise detection circuit of any of claims 1 to 20; and if the amplitude of the noise is lower than a preset noise threshold value, the self-capacitance detection circuit performs capacitance detection at the first frequency.

22. The self-capacitance detection method according to claim 21, wherein a period of the self-capacitance detection is equal to a reciprocal of the first frequency, the self-capacitance detection circuit performs capacitance detection at the first frequency, and the period of the self-capacitance detection is equal to a noise detection period.

23. The self-contained detection method of claim 22, wherein the noise detection period is equal to an integer multiple of a noise detection half-period, the noise detection half-period being a sum of the first time period, the second time period, the third time period, and the fourth time period.

24. The self-contained detection method of claim 23, wherein the noise detection period is twice the noise detection half period.

25. The self-capacitance detection method according to claim 21, wherein when the self-capacitance detection circuit operates at the first frequency, the processing module performs demodulation at the first frequency to obtain a self-capacitance value.

26. The self-capacitance detection method according to claim 21, wherein during self-capacitance detection, the capacitance to be detected and the cancellation capacitance are charged in a ninth time period, and the capacitance to be detected and the cancellation capacitance are charge-cancelled in a tenth time period; in an eleventh time period, carrying out charge transfer on the charges of the capacitor to be measured and the offset capacitor; during a twelfth period, the charge transfer module is reset; in a thirteenth time period, discharging the capacitor to be detected and charging the offset capacitor; in a fourteenth time period, carrying out charge cancellation on the capacitor to be measured and the cancellation capacitor; in a fifteenth time period, carrying out charge transfer on the charges of the capacitor to be measured and the offset capacitor; during a sixteenth period, the charge transfer module is reset; the ninth period, the tenth period, the eleventh period, the twelfth period have lengths equal to the thirteenth period, the fourteenth period, the fifteenth period, and the sixteenth period, respectively; the ninth period, the tenth period, the eleventh period, and the twelfth period have lengths equal to lengths of the first period, the second period, the third period, and the fourth period, respectively.

27. A touch chip, comprising: the noise detection circuit of any of claims 1 to 20.

28. A capacitive touch system, comprising: the touch chip and the touch sensor of claim 27.

29. An electronic device comprising the touch chip of claim 27.