CN111866410A - Display processing system capable of receiving multiple optical fiber SDI signals - Google Patents
Display processing system capable of receiving multiple optical fiber SDI signals Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3406—Control of illumination source
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/265—Mixing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/22—Adaptations for optical transmission
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/18—Use of optical transmission of display information
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- Computer Hardware Design (AREA)
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Abstract
The invention discloses a display processing system capable of receiving a plurality of paths of optical fiber SDI signals, which realizes the work and video algorithm processing of a display hardware circuit through an FPGA controller, wherein the display hardware circuit comprises a power supply processing part, a signal processing part, a backlight adjusting circuit, a heating control circuit and a temperature acquisition circuit; the display of the display processing system can receive multiple SDI signals through optical fiber transmission, so that interference caused by cable transmission is avoided, and the number of used display terminals is reduced; the multi-channel video splicing display or the single-channel video amplifying display can be realized, and a user can conveniently check different video monitoring information; meanwhile, the complexity of the hardware circuit design is reduced, the cost is reduced, and the reliability is improved.
Description
Technical Field
The invention relates to a display processing system capable of receiving multiple paths of optical fiber SDI signals.
Background
Some large transport machines monitor the scene information outside the machine body through a plurality of cameras placed outside the cabin, and the picture information is transmitted to a display inside the cabin to be displayed.
However, the electromagnetic environment inside the aircraft is complex, and is prone to generate interference on signal transmission cables, and for long-distance signal transmission, optical fibers are generally selected to realize signal transmission. Meanwhile, the existing camera transmission generally adopts SDI signals or CVBS signals, the CVBS cannot transmit high-resolution video signals, and the signal anti-interference capability is weak, so that the camera is not suitable for military airborne video transmission.
Therefore, it is urgently needed to provide a display processing system capable of receiving multiple optical fiber SDI signals to realize external multiple SDI video splicing display and single SDI video amplification display.
Disclosure of Invention
The invention aims to provide a display processing system capable of receiving multiple paths of optical fiber SDI signals, wherein a display of the display processing system can receive the multiple paths of SDI signals through optical fiber transmission, so that the interference caused by cable transmission is avoided, and the using number of display terminals is reduced; the multi-channel video splicing display or the single-channel video amplifying display can be realized, and a user can conveniently check different video monitoring information; meanwhile, the complexity of the hardware circuit design is reduced, the cost is reduced, and the reliability is improved.
In order to achieve the purpose, the invention provides a display processing system capable of receiving a plurality of paths of optical fiber SDI signals, which realizes the work and video algorithm processing of a display hardware circuit through an FPGA controller, wherein the display hardware circuit comprises a power supply processing part, a signal processing part, a backlight adjusting circuit, a heating control circuit and a temperature acquisition circuit; wherein the content of the first and second substances,
in the power supply processing part, a display is connected with an onboard 28V power supply, and the power supply is filtered and subjected to anti-surge processing by a power supply processing module to supply power for 28V to a backlight LED lamp and heating glass; then, 5V is converted into 1.2V, 2.5V, 3.3V and 1.8V through a circuit for converting 28V into 5V, and the voltage is used for supplying power to the FPGA and other circuits;
in the signal processing part, 3 paths of optical fiber SDI signals are converted into SDI signals through the photoelectric conversion module respectively, and the SDI signals are decoded by the SDI decoding chip and input into the FPGA; the FPGA controls two groups of DDR3 memories to realize caching and splicing processing of signals, then the signals are output to an LVDS coding chip, and finally the coding chip outputs the signals to an LCD; the FPGA acquires key values of the key light guide plate to realize the functions of displaying internal maintenance pictures of the display, adjusting the brightness and contrast of the display and switching the display of an external video source;
in the backlight adjusting circuit, the FPGA outputs PWM to control the backlight driving circuit to switch to realize constant current, and the frequency output by the PWM is adjusted to adjust the current so as to adjust the brightness of the LED lamp;
in the heating control circuit, the FPGA outputs PWM to control the switch of the heating control circuit, and the duty ratio of the PWM is adjusted to control the on-off time of the heating circuit so as to control the current flowing through the heating glass and realize heating control;
in the temperature acquisition circuit, the temperature acquisition circuit acquires data of two paths of temperature sensors, the data are converted into digital quantity to be sent to the FPGA, and the FPGA acquires temperature information and controls the display to heat at low temperature.
Preferably, the external SDI video source is 1080P @30fps, the resolution of the LCD screen is 1920 × 1200, and the signal transmission is odd-even LVDS transmission.
Preferably, the 3-way SDI is decoded into a BT.1120 video stream by an SDI decoding chip, the FPGA decodes the BT.1120 video stream, and converts the data format with the encoding format of YUV4:4:2 into an RGB8:8:8 data format of the Vesa standard.
Preferably, the 3-path video is cached and output through the 1 st group of DDR3 after completing data format conversion, the FPGA controls the reading and writing of the 1 st group of DDR3 through priority arbitration, and the 3-path video caches 3 frames in the DDR3 and is independent from each other without influence.
Preferably, the key light guide plate selects an external SDI video display mode through 4 keys, wherein a key 1 displays 3 SDI video splices; keys 2, 3 and 4 sequentially display a single SDI video; the OSD key collection module acquires key value information of the key light guide plate, if the key value information is displayed in a splicing mode, the signal selection module outputs 3 paths of videos cached by the 1 st group of DDR3, and the videos enter 3 Scale Down modules (video reduction modules) respectively and are reduced to 960 x 600 resolution; if the single-channel video is displayed, the signal selection module selects the corresponding video signal to enter the ScaleUp module (video amplification module) according to the selected video source, and amplifies the video with the resolution of 1920 × 1200.
Preferably, the 3-path scaledon video completes the video splicing operation in the 2 nd group of DDRs 3, the 3-path video is spliced into a shape like a Chinese character pin, the FPGA controls the reading and writing of the 2 nd group of DDRs 3 through priority arbitration, 3-path 960 × 600 video writing into the DDR3 is realized, and the video is read out from the DDR3 at 1920 × 1200 resolution.
Preferably, the signal switching module selects an internal maintenance picture or an external reduced or amplified video source to output to the contrast adjusting module, and the signal is subjected to contrast adjustment and then is superposed with the internal OSD picture; inserting a startup picture when the display is started, outputting the startup picture by the startup switching module within the startup time of the display startup system, or outputting the video subjected to superposition processing; the single-path to odd-even conversion module converts the single-path signal output by the starting switching module into an odd-even dual-path video signal and respectively sends the odd-even dual-path video signal to the LVDS coding chips, and the two LVDS coding chips code the RGB signal into an odd-even LVDS signal to be displayed on the LCD screen.
Preferably, the ScaleUP module is in a reset state by sending a signal when the ScaleUP module works, and the ScaleUP module is in a reset state by sending a signal when the ScaleUP module works, so that the working power consumption of the FPGA is reduced.
According to the technical scheme, the work and video algorithm processing of the display hardware circuit are realized through the FPGA controller. Specifically, the display can receive multiple SDI signals through optical fiber transmission, so that interference caused by cable transmission is avoided, and the number of used display terminals is reduced; the display can realize multi-path splicing display or single-path video amplification display, and is convenient for a user to check different video monitoring information; compared with other displays which use a single GPU or CPU to process signal display contents, the display has the advantages of reduced complexity of hardware circuit design, reduced cost and improved reliability.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic block diagram of a display circuit according to the present invention;
FIG. 2 is a schematic block diagram of FPGA signal processing in the present invention;
fig. 3 is a schematic diagram of 3-way video splicing in the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
In the present invention, unless otherwise specified, the directional terms included in the terms merely represent the directions of the terms in a conventional use state or are colloquially known by those skilled in the art, and should not be construed as limiting the terms.
Referring to fig. 1, the invention provides a display processing system capable of receiving multiple optical fiber SDI signals, which realizes the work and video algorithm processing of a display hardware circuit through an FPGA controller, wherein the display hardware circuit comprises a power supply processing part, a signal processing part, a backlight adjusting circuit, a heating control circuit and a temperature acquisition circuit; wherein the content of the first and second substances,
in the power supply processing part, a display is connected with an onboard 28V power supply, and the power supply is filtered and subjected to anti-surge processing by a power supply processing module to supply power for 28V to a backlight LED lamp and heating glass; then, 5V is converted into 1.2V, 2.5V, 3.3V and 1.8V through a circuit for converting 28V into 5V, and the voltage is used for supplying power to the FPGA and other circuits;
in the signal processing part, 3 paths of optical fiber SDI signals are converted into SDI signals through the photoelectric conversion module respectively, and the SDI signals are decoded by the SDI decoding chip and input into the FPGA; the FPGA controls two groups of DDR3 memories to realize caching and splicing processing of signals, then the signals are output to an LVDS coding chip, and finally the coding chip outputs the signals to an LCD; the FPGA acquires key values of the key light guide plate to realize the functions of displaying internal maintenance pictures of the display, adjusting the brightness and contrast of the display and switching the display of an external video source;
in the backlight adjusting circuit, the FPGA outputs PWM to control the backlight driving circuit to switch to realize constant current, and the frequency output by the PWM is adjusted to adjust the current so as to adjust the brightness of the LED lamp;
in the heating control circuit, the FPGA outputs PWM to control the switch of the heating control circuit, and the duty ratio of the PWM is adjusted to control the on-off time of the heating circuit so as to control the current flowing through the heating glass and realize heating control;
in the temperature acquisition circuit, the temperature acquisition circuit acquires data of two paths of temperature sensors, the data are converted into digital quantity to be sent to the FPGA, and the FPGA acquires temperature information and controls the display to heat at low temperature.
In fig. 2, the external SDI video source is 1080P @30fps, the resolution of the LCD screen is 1920 × 1200, and the signal transmission is odd-even LVDS transmission.
The 3-way SDI is decoded into a BT.1120 video stream by an SDI decoding chip, the BT.1120 video stream is decoded by the FPGA, and the data format with the encoding format of YUV4:4:2 is converted into an RGB8:8:8 data format of the Vesa standard.
After completing data format conversion, the 3 paths of videos are cached and output through the 1 st group of DDR3, the FPGA controls the reading and writing of the 1 st group of DDR3 through priority arbitration, and the 3 paths of videos are cached in the DDR3 for 3 frames and are independent from each other and do not influence each other.
The key light guide plate selects an external SDI video display mode through 4 keys, wherein 3 SDI video splicing is displayed by a key 1; keys 2, 3 and 4 sequentially display a single SDI video; the OSD key collection module acquires key value information of the key light guide plate, if the key value information is displayed in a splicing mode, the signal selection module outputs 3 paths of videos cached by the 1 st group of DDR3, and the videos enter 3 Scale Down modules (video reduction modules) respectively and are reduced to 960 x 600 resolution; if the single-channel video is displayed, the signal selection module selects the corresponding video signal to enter the ScaleUp module (video amplification module) according to the selected video source, and amplifies the video with the resolution of 1920 × 1200.
As shown in fig. 3, the 3-way scaledon video completes the video splicing operation in the 2 nd group of DDR3, the 3-way video is spliced into a shape of "pin", the FPGA controls the reading and writing of the 2 nd group of DDR3 through priority arbitration, so that the 3-way 960 × 600 video is written into the DDR3, and the video is read out from the DDR3 at 1920 × 1200 resolution.
The signal switching module selects an internal maintenance picture or an external reduced or amplified video source to output to the contrast adjusting module, and the signal is subjected to contrast adjustment and then is superposed with an internal OSD picture; inserting a startup picture when the display is started, outputting the startup picture by the startup switching module within the startup time of the display startup system, or outputting the video subjected to superposition processing; the single-path to odd-even conversion module converts the single-path signal output by the starting switching module into an odd-even dual-path video signal and respectively sends the odd-even dual-path video signal to the LVDS coding chips, and the two LVDS coding chips code the RGB signal into an odd-even LVDS signal to be displayed on the LCD screen.
The scaleDown module sends a signal to enable the scaleUP module to be in a reset state when working, and the scaleUP module sends a signal to enable the scaleDown module to be in the reset state when working, so that the working power consumption of the FPGA is reduced.
In a specific embodiment, the display realizes the switching of 4 kinds of display through four keys of the key light guide plate, and triggers the key 1 to display the superposition display of 3 paths of SDI video signals; triggering a key 2, and displaying the 1 st SDI video signal by a display; triggering a key 3 display to display the 3 rd SDI video signal; triggering a key 4 display to display the 4 th SDI video signal;
when 3 paths of spliced display are carried out, 3 paths of SDI signals need to be processed through two groups of DDR3, the 1 st group of DDR3 is used for caching 3 paths of videos to realize that the 3 paths of videos are subjected to reduction and amplification processing for a Scale Down or Scale UP module; group 2 DDRs 3 enable the stitching of 3-way 960 x 600 resolution video. The 3-way 960 × 600 video data writes data to the same block DDR3 memory at different offset addresses, and then reads out the written 3-way video data at 1920 × 1200 resolution.
The single-path display is amplified to 1920 × 1200 resolution by the ScaleUP module for 1920 × 1080 resolution ScaleUP of external input, and the single-path display does not need to use the 2 nd group of DDRs 3.
Through the technical scheme, the FPGA controller is used for realizing the work of a display hardware circuit and video algorithm processing. Namely, the display can receive multiple SDI signals through optical fiber transmission, so that the interference caused by cable transmission is avoided, and the number of used display terminals is reduced; the display can realize multi-channel video splicing display or single-channel video amplification display, and is convenient for a user to check different video monitoring information; compared with other displays which use a single GPU or CPU to process signal display contents, the display has the advantages of reduced complexity of hardware circuit design, reduced cost and improved reliability.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.
Claims (8)
1. A display processing system capable of receiving multiple paths of optical fiber SDI signals is characterized in that work and video algorithm processing of a display hardware circuit are achieved through an FPGA controller, and the display hardware circuit comprises a power supply processing part, a signal processing part, a backlight adjusting circuit, a heating control circuit and a temperature acquisition circuit; wherein the content of the first and second substances,
in the power supply processing part, a display is connected with an onboard 28V power supply, and the power supply is filtered and subjected to anti-surge processing by a power supply processing module to supply power for 28V to a backlight LED lamp and heating glass; then, 5V is converted into 1.2V, 2.5V, 3.3V and 1.8V through a circuit for converting 28V into 5V, and the voltage is used for supplying power to the FPGA and other circuits;
in the signal processing part, 3 paths of optical fiber SDI signals are converted into SDI signals through the photoelectric conversion module respectively, and the SDI signals are decoded by the SDI decoding chip and input into the FPGA; the FPGA controls two groups of DDR3 memories to realize caching and splicing processing of signals, then the signals are output to an LVDS coding chip, and finally the coding chip outputs the signals to an LCD; the FPGA acquires key values of the key light guide plate to realize the functions of displaying internal maintenance pictures of the display, adjusting the brightness and contrast of the display and switching the display of an external video source;
in the backlight adjusting circuit, the FPGA outputs PWM to control the backlight driving circuit to switch to realize constant current, and the frequency output by the PWM is adjusted to adjust the current so as to adjust the brightness of the LED lamp;
in the heating control circuit, the FPGA outputs PWM to control the switch of the heating control circuit, and the duty ratio of the PWM is adjusted to control the on-off time of the heating circuit so as to control the current flowing through the heating glass and realize heating control;
in the temperature acquisition circuit, the temperature acquisition circuit acquires data of two paths of temperature sensors, the data are converted into digital quantity to be sent to the FPGA, and the FPGA acquires temperature information and controls the display to heat at low temperature.
2. The system of claim 1, wherein the external SDI video source is 1080P @30fps, the LCD screen has a resolution of 1920 x 1200, and the signaling is odd-even LVDS.
3. The system of claim 1, wherein the 3 SDI is decoded into BT.1120 video stream by SDI decoder chip, the FPGA decodes BT.1120 video stream, and converts the data format with YUV4:4:2 into RGB8:8:8 data format of Vesa standard.
4. The system of claim 1, wherein 3 videos are buffered and output by the group 1 of DDR3 after completing data format conversion, the FPGA controls reading and writing of the group 1 of DDR3 through priority arbitration, and the 3 videos are buffered for 3 frames in the DDR3 and are independent of each other without affecting.
5. The system of claim 1, wherein the key light guide plate selects an external SDI video display mode by 4 keys, wherein key 1 displays 3 SDI video tiles; keys 2, 3 and 4 sequentially display a single SDI video; the OSD key collection module acquires key value information of the key light guide plate, if the key value information is displayed in a splicing mode, the signal selection module outputs 3 paths of videos cached by the 1 st group of DDR3, and the videos enter 3 Scale Down modules (video reduction modules) respectively and are reduced to 960 x 600 resolution; if the single-channel video is displayed, the signal selection module selects the corresponding video signal to enter the ScaleUp module (video amplification module) according to the selected video source, and amplifies the video with the resolution of 1920 × 1200.
6. The system of claim 1, wherein 3 scaledon videos are spliced into a delta shape in the 2 nd group of DDR3, 3 videos are spliced into a delta shape, the FPGA controls reading and writing of the 2 nd group of DDR3 through priority arbitration, and 3 paths of 960 x 600 video writing DDR3 are realized, and video reading from the DDR3 is realized at 1920 x 1200 resolution.
7. The system of claim 1, wherein the signal switching module selects an internal maintenance frame or an external video source that is reduced or enlarged and outputs the selected frame to the contrast adjustment module, and the signal is subjected to contrast adjustment and then is superimposed on an internal OSD frame; inserting a startup picture when the display is started, outputting the startup picture by the startup switching module within the startup time of the display startup system, or outputting the video subjected to superposition processing; the single-path to odd-even conversion module converts the single-path signal output by the starting switching module into an odd-even dual-path video signal and respectively sends the odd-even dual-path video signal to the LVDS coding chips, and the two LVDS coding chips code the RGB signal into an odd-even LVDS signal to be displayed on the LCD screen.
8. The system of claim 1, wherein the ScaleUP module is operable to signal the ScaleUP module to be in a reset state, and wherein the ScaleUP module is operable to signal the ScaleUP module to be in a reset state to reduce FPGA power consumption.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113766267A (en) * | 2021-09-15 | 2021-12-07 | 深圳市道通智能航空技术股份有限公司 | Multi-channel video live broadcast method, system, equipment and storage medium based on unmanned aerial vehicle |
| CN115206255A (en) * | 2022-06-17 | 2022-10-18 | 中航华东光电有限公司 | Aviation display control system and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270578A (en) * | 2014-09-19 | 2015-01-07 | 深圳市晶日盛科技有限公司 | Method and system for processing multi-channel video images based on network transmitting |
| CN105554416A (en) * | 2015-12-24 | 2016-05-04 | 深圳市捷视飞通科技股份有限公司 | FPGA (Field Programmable Gate Array)-based high-definition video fade-in and fade-out processing system and method |
| CN105847927A (en) * | 2016-05-09 | 2016-08-10 | 华东师范大学 | Multi-source multi-mode high-speed video wireless synchronous display apparatus |
| US20200143772A1 (en) * | 2018-11-01 | 2020-05-07 | Aten International Co., Ltd. | Video control device and video wall system using the same and control method for outputting video images to the video wall |
-
2020
- 2020-08-04 CN CN202010775222.6A patent/CN111866410A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270578A (en) * | 2014-09-19 | 2015-01-07 | 深圳市晶日盛科技有限公司 | Method and system for processing multi-channel video images based on network transmitting |
| CN105554416A (en) * | 2015-12-24 | 2016-05-04 | 深圳市捷视飞通科技股份有限公司 | FPGA (Field Programmable Gate Array)-based high-definition video fade-in and fade-out processing system and method |
| CN105847927A (en) * | 2016-05-09 | 2016-08-10 | 华东师范大学 | Multi-source multi-mode high-speed video wireless synchronous display apparatus |
| US20200143772A1 (en) * | 2018-11-01 | 2020-05-07 | Aten International Co., Ltd. | Video control device and video wall system using the same and control method for outputting video images to the video wall |
Non-Patent Citations (2)
| Title |
|---|
| 易子川等: "基于FPGA的多路视频实时处理系统", 《华南师范大学学报(自然科学版)》 * |
| 朱礼年等: "一款1.8寸超高亮度微显示器电路设计", 《山东工业技术》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113766267A (en) * | 2021-09-15 | 2021-12-07 | 深圳市道通智能航空技术股份有限公司 | Multi-channel video live broadcast method, system, equipment and storage medium based on unmanned aerial vehicle |
| WO2023040984A1 (en) * | 2021-09-15 | 2023-03-23 | 深圳市道通智能航空技术股份有限公司 | Unmanned aerial vehicle-based multi-channel video live broadcast method, system, device and storage medium |
| CN113766267B (en) * | 2021-09-15 | 2023-10-24 | 深圳市道通智能航空技术股份有限公司 | Multi-path video live broadcast method, system, equipment and storage medium based on unmanned aerial vehicle |
| CN115206255A (en) * | 2022-06-17 | 2022-10-18 | 中航华东光电有限公司 | Aviation display control system and method |
| CN115206255B (en) * | 2022-06-17 | 2024-04-19 | 中航华东光电有限公司 | Aviation display control system and method |
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Application publication date: 20201030 |