CN111865263B

CN111865263B - Double-circuit numerical control frequency hopping trapper

Info

Publication number: CN111865263B
Application number: CN202010682566.2A
Authority: CN
Inventors: 刘泽雨; 蔡楚才
Original assignee: WUHAN BOCHANG SMOOTH LETTER EQUIPMENT CO Ltd
Current assignee: WUHAN BOCHANG SMOOTH LETTER EQUIPMENT CO Ltd
Priority date: 2020-07-15
Filing date: 2020-07-15
Publication date: 2023-06-27
Anticipated expiration: 2040-07-15
Also published as: CN111865263A

Abstract

The invention provides a double-path numerical control frequency hopping trap, which comprises a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a first directional coupler, a second directional coupler, a first numerical control frequency hopping filter, a second numerical control frequency hopping filter, a third numerical control frequency hopping filter, a fourth numerical control frequency hopping filter, a first 50 omega load, a second 50 omega load, a third 50 omega load, a fourth 50 omega load and a singlechip main control unit. The invention can realize a plurality of working modes such as single-channel independent notch, double-channel notch, bypass and the like of the notch filter by controlling the gating of the three radio frequency switch signal channels, has high flexibility in selecting the working modes, can simultaneously filter two large interference signals when the notch filter works in the double-channel notch mode, and has good filtering effect.

Description

Double-circuit numerical control frequency hopping trapper

Technical Field

The invention relates to the technical field of frequency hopping wave traps, in particular to a double-path numerical control frequency hopping wave trap.

Background

When the broadband receiver works, if a single or a plurality of high-power interference signals in a space are received, serious signal blockage can occur in a low-noise amplifier, an AD (analog-to-digital) and the like at the receiving front end, and the normal working of a system can be influenced, so that the broadband receiver needs to have the function of selectively eliminating the large signals and simultaneously reserving the small signals to be received at the radio frequency receiving front end.

The digital control frequency hopping wave trap is a device for eliminating large signals at the front end of the broadband receiver, the traditional digital control frequency hopping wave trap is usually designed to filter single large interference signals at a time, two interference signals cannot be filtered at the same time, and when more interference needs to be filtered, the filtering effect is poor; and whether filtering is performed cannot be selected, and the flexibility of selecting the working mode is low.

Disclosure of Invention

The invention provides a double-path numerical control frequency hopping wave trap, which aims to solve the problems that the traditional numerical control frequency hopping wave trap cannot filter two interference signals at the same time and has low flexibility in selecting a working mode.

The technical scheme of the invention is realized as follows: the double-path numerical control frequency hopping trap comprises a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a first directional coupler, a second directional coupler, a first numerical control frequency hopping filter, a second numerical control frequency hopping filter, a third numerical control frequency hopping filter, a fourth numerical control frequency hopping filter, a first 50 omega load, a second 50 omega load, a third 50 omega load, a fourth 50 omega load and a singlechip master control unit, wherein the second radio frequency switch comprises a 3-4 signal channel, a 1-4 signal channel and a 3-2 signal channel;

the singlechip main control unit is respectively connected with the first radio frequency switch, the second radio frequency switch, the third radio frequency switch, the first numerical control frequency hopping filter, the second numerical control frequency hopping filter, the third numerical control frequency hopping filter and the fourth numerical control frequency hopping filter;

the radio frequency input signal is input into a first radio frequency switch, a first signal channel of the first radio frequency switch is connected with a first signal channel of a third radio frequency switch, a second signal channel of the first radio frequency switch is connected with a port 1 of a second radio frequency switch, and a port 2 of the second radio frequency switch is connected with a second signal channel of the third radio frequency switch;

the third signal channel of the first radio frequency switch is connected with the input end of the first directional coupler, the isolation end of the first directional coupler is connected with the port 3 of the second radio frequency switch, the port 4 of the second radio frequency switch is connected with the input end of the second directional coupler, and the isolation end of the second directional coupler is connected with the third signal channel of the third radio frequency switch;

the direct-through end of the first directional coupler is grounded through a first numerical control frequency hopping filter and a first 50Ω load in sequence, the coupling end of the first directional coupler is grounded through a second numerical control frequency hopping filter and a second 50Ω load in sequence, the direct-through end of the second directional coupler is grounded through a third numerical control frequency hopping filter and a third 50Ω load in sequence, and the coupling end of the second directional coupler is grounded through a fourth numerical control frequency hopping filter and a fourth 50Ω load in sequence.

Optionally, the frequency range of the first directional coupler and the second directional coupler is 1MHz-40 MHz.

Optionally, the first digital control frequency hopping filter, the second digital control frequency hopping filter, the third digital control frequency hopping filter and the fourth digital control frequency hopping filter are twelve paths of PIN switch capacitor arrays.

Optionally, the first digital control frequency hopping filter, the second digital control frequency hopping filter, the third digital control frequency hopping filter or the fourth digital control frequency hopping filter comprises inductors L1 to L5, capacitors C1 to C2, a PIN switch capacitor array K1 and a PIN switch capacitor array K2;

the front-stage circuit is sequentially connected with the rear-stage circuit through an inductor L1, an inductor L2, an inductor L3 and an inductor L4 which are connected in series, the common end of the inductor L1 and the inductor L2 is grounded through a capacitor C1, the PIN switch capacitor array K1 is connected with the capacitor C1 in parallel, the common end of the inductor L3 and the inductor L4 is grounded through a capacitor C2, the PIN switch capacitor array K2 is connected with the capacitor C2 in parallel, and the common end of the inductor L2 and the inductor L3 is grounded through an inductor L5.

Optionally, the PIN switch capacitor array K1 comprises resistors R1-R3, capacitors C3-C4 and PIN diodes D1-D2;

one end of the resistor R1 is sequentially grounded through the cathode of the PIN diode D1, the anode of the PIN diode D1, the cathode of the PIN diode D2 and the anode of the PIN diode D2, the other end of the resistor R1 is connected with a control signal, the public end of the PIN diode D1 and the public end of the PIN diode D2 are connected with the inductance L1 and the inductance L2 through the capacitor C3, the resistor R2 is connected with the PIN diode D1 in parallel, the resistor R3 is connected with the PIN diode D2 in parallel, and the public end of the cathode of the resistor R1 and the PIN diode D1 is grounded through the capacitor C4.

Optionally, the PIN switched capacitor array K1 further includes an inductor L6 and an NMOS transistor S1;

the inductor L6 is connected between the inductor L5 and the ground, one end of the inductor L6, which is close to the inductor L5, is also connected with the drain electrode of the NMOS tube S1, one end of the inductor L6, which is grounded, is also connected with the source electrode of the NMOS tube S1, and the singlechip main control unit is connected with the grid electrode of the NMOS tube S1.

Optionally, the PIN switched capacitor array K1 further includes an inductance L7 and capacitors C5 to C6;

the inductor L7 is connected between the inductor L6 and the ground, the common end of the inductor L5 and the inductor L6 is grounded through the capacitor C5, and one end of the inductor L7, which is grounded, is also grounded through the capacitor C6.

Compared with the prior art, the double-path numerical control frequency hopping wave trap has the following beneficial effects:

(1) The double-channel numerical control frequency hopping trap can realize a plurality of working modes such as single-channel independent trap, double-channel trap, bypass and the like of the trap by controlling gating of three radio frequency switch signal channels, has high flexibility in selecting the working modes, can simultaneously filter two large interference signals when the trap works in the double-channel trap mode, and has good filtering effect;

(2) By arranging the inductor L6 and the NMOS tube S1, the NMOS tube S1 can be controlled to be conducted when the frequency hopping filter hops to the low end of the frequency, the inductor L5 and the inductor L6 are used as the coupling inductance of the double-tuning circuit together, the coupling inductance is increased, the NMOS tube S1 can be controlled to be cut off when the frequency hopping filter hops to the high end of the frequency, only the inductor L5 is used as the coupling inductance of the double-tuning circuit, the coupling inductance is reduced, and the problem that the performance consistency of the numerical control frequency hopping filter in the high-low frequency is poor is solved;

(3) The compensating network formed by the inductance L7 and the capacitances C5-C6 compensates the insertion loss of the coupling circuit caused by the NMOS tube S1, and improves the performance of the frequency hopping filter.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a two-way numerical control frequency hopping trap of the present invention;

FIG. 2 is a circuit diagram of a digitally controlled frequency hopping filter of the present invention;

FIG. 3 is a partial circuit diagram of a PIN switched capacitor array of the present invention;

fig. 4 is an equivalent schematic diagram of the coupling circuit when the NMOS transistor S1 is turned on.

Detailed Description

The following description of the embodiments of the present invention will clearly and fully describe the technical aspects of the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.

As shown in fig. 1, the two-way digitally controlled frequency trap of the present embodiment includes a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a first directional coupler, a second directional coupler, a first digitally controlled frequency hopping filter, a second digitally controlled frequency hopping filter, a third digitally controlled frequency hopping filter, a fourth digitally controlled frequency hopping filter, a first 50Ω load, a second 50Ω load, a third 50Ω load, a fourth 50Ω load, and a single chip microcomputer main control unit, where the second radio frequency switch includes a 3-4 signal channel, a 1-4 signal channel, and a 3-2 signal channel.

The singlechip main control unit is respectively connected with the first radio frequency switch, the second radio frequency switch, the third radio frequency switch, the first numerical control frequency hopping filter, the second numerical control frequency hopping filter, the third numerical control frequency hopping filter and the fourth numerical control frequency hopping filter. The radio frequency input signal is input into a first radio frequency switch, a first signal channel of the first radio frequency switch is connected with a first signal channel of a third radio frequency switch, a second signal channel of the first radio frequency switch is connected with a port 1 of a second radio frequency switch, and a port 2 of the second radio frequency switch is connected with a second signal channel of the third radio frequency switch. The third signal channel of the first radio frequency switch is connected with the input end of the first directional coupler, the isolation end of the first directional coupler is connected with the port 3 of the second radio frequency switch, the port 4 of the second radio frequency switch is connected with the input end of the second directional coupler, and the isolation end of the second directional coupler is connected with the third signal channel of the third radio frequency switch. The direct-through end of the first directional coupler is grounded through a first numerical control frequency hopping filter and a first 50Ω load in sequence, the coupling end of the first directional coupler is grounded through a second numerical control frequency hopping filter and a second 50Ω load in sequence, the direct-through end of the second directional coupler is grounded through a third numerical control frequency hopping filter and a third 50Ω load in sequence, and the coupling end of the second directional coupler is grounded through a fourth numerical control frequency hopping filter and a fourth 50Ω load in sequence.

The single chip microcomputer main control unit is used for controlling the first radio frequency switch, the second radio frequency switch and the third radio frequency switch to select one path from a plurality of signal channels to be communicated, and controlling the resonance frequencies of the first numerical control frequency hopping filter, the second numerical control frequency hopping filter, the third numerical control frequency hopping filter and the fourth numerical control frequency hopping filter to realize frequency conversion. The first rf switch may be a 1×3 rf switch, the port 3 and the port 2 of the second rf switch may form a first signal channel of the second rf switch, the port 1 and the port 4 may form a second signal channel of the second rf switch, the port 3 and the port 4 may form a third signal channel of the second rf switch, and the third rf switch may be a 3×1 rf switch. The frequency range of the first directional coupler and the second directional coupler is 1MHz-40MHz, the isolation degree is higher, and the input signals can be converted into two signals with equal amplitude and 90 degrees phase difference. The performance of the first numerical control frequency hopping filter is close to and synchronously controlled with the second numerical control frequency hopping filter, and the performance of the third numerical control frequency hopping filter is close to and synchronously controlled with the fourth numerical control frequency hopping filter. The first digital control frequency hopping filter, the second digital control frequency hopping filter, the third digital control frequency hopping filter and the fourth digital control frequency hopping filter are twelve paths of PIN switch capacitor arrays, so that the accurate and rapid response of the center frequency of the frequency hopping filter, high selectivity, small bandwidth and lower input standing wave ratio can be realized.

In this embodiment, if the first signal channel of the first radio frequency switch is turned on and the first signal channel of the third radio frequency switch is turned on, the radio frequency input signal is directly output through the first radio frequency switch and the third radio frequency switch, and does not pass through any notch filter, the two-way digital control frequency hopping notch filter works in the bypass mode.

If the second signal channel of the first radio frequency switch is on, the second signal channel of the second radio frequency switch is on, and the third signal channel of the third radio frequency switch is on, the radio frequency input signal reaches the input end of the second directional coupler through the first radio frequency switch and the second radio frequency switch, the second directional coupler converts the input signal into two signals with equal amplitude and 90 degrees phase difference, when the two signals pass through the center frequency of the third frequency hopping filter and the center frequency of the fourth frequency hopping filter, the two signals are absorbed to the ground through a 50 ohm load, when the two signals pass through the stop band of the third frequency hopping filter and the fourth frequency hopping filter, the two signals are reflected to the output port to be synthesized into a signal output, the amplitude is slightly lower than the input signal, and the difference is the insertion loss of the second directional coupler. If the second signal channel of the first radio frequency switch is on, the second signal channel of the second radio frequency switch is on, and the third signal channel of the third radio frequency switch is on, the radio frequency input signal reaches the input end of the second directional coupler through the first radio frequency switch and the second radio frequency switch, the second directional coupler converts the input signal into two signals with equal amplitude and 90 degrees phase difference, when the two signals pass through the center frequency of the third frequency hopping filter and the center frequency of the fourth frequency hopping filter, the two signals are absorbed by a 50 ohm load, when the two signals pass through the stop band of the third frequency hopping filter and the fourth frequency hopping filter, the two signals are reflected to the output port to be synthesized into a signal output, the amplitude is slightly lower than the input signal, the difference part is the insertion loss of the second directional coupler, and at the moment, the two-way numerical control frequency hopping trap works in a single-channel independent notch mode, and a large interference signal can be filtered.

If the third signal channel of the first radio frequency switch is on, the first signal channel of the second radio frequency switch is on, and the second signal channel of the third radio frequency switch is on, the radio frequency input signal reaches the input end of the first directional coupler through the first radio frequency switch, the first directional coupler converts the input signal into two signals with equal amplitude and 90 degrees of phase difference, when the two signals pass through the center frequency of the first frequency hopping filter and the center frequency of the second frequency hopping filter, the two signals are absorbed to the ground through a 50 ohm load, when the two signals pass through the stop band of the first frequency hopping filter and the second frequency hopping filter, the two signals are reflected to the output port to synthesize a signal output, the amplitude is slightly lower than the input signal, the difference part is the insertion loss of the first directional coupler, and at the moment, the two-way numerical control frequency hopping trap works in a single-channel independent notch mode, and can filter a large interference signal.

If the third signal channel of the first radio frequency switch is on, the third signal channel of the second radio frequency switch is on, and the third signal channel of the third radio frequency switch is on, the radio frequency input signal reaches the input end of the first directional coupler through the first radio frequency switch, the first directional coupler converts the input signal into two signals with equal amplitude and 90 degrees of phase difference, when the two signals pass through the center frequency of the first frequency hopping filter and the center frequency of the second frequency hopping filter, the two signals are absorbed to the ground through a 50 ohm load, when the two signals pass through the stop band of the first frequency hopping filter and the stop band of the second frequency hopping filter, the two signals are reflected to the output port to be synthesized into a signal output, the radio frequency signal output through the first directional coupler reaches the second directional coupler to carry out the same process treatment, the amplitude of the final output signal is slightly lower than the input signal, the difference part is the insertion loss of the first directional coupler and the second directional coupler, and at the moment, the two-path numerical control frequency hopping trap works in a two-path mode, and two interference large signals can be filtered.

Therefore, the double-channel numerical control frequency hopping trapper of the embodiment can realize a plurality of working modes such as single-channel independent notch, double-channel notch, bypass and the like of the trapper by controlling gating of three radio frequency switch signal channels, the flexibility of selecting the working modes is high, two interference large signals can be filtered simultaneously when the trapper works in the double-channel notch mode, and the filtering effect is good. The double-path numerical control frequency hopping trap has the advantages of high response speed, accurate trap center frequency, large attenuation value, small trap bandwidth range, small influence on useful signals, small passband insertion loss of the trap and good intermodulation index of the two trap frequencies.

Further, in this embodiment, the circuit structures of the first digitally controlled frequency hopping filter, the second digitally controlled frequency hopping filter, the third digitally controlled frequency hopping filter, and the fourth digitally controlled frequency hopping filter are preferably identical, and as shown in fig. 2, for any one of the four digitally controlled frequency hopping filters, the first digitally controlled frequency hopping filter, the second digitally controlled frequency hopping filter, the third digitally controlled frequency hopping filter, and the fourth digitally controlled frequency hopping filter specifically include inductors L1 to L5, capacitors C1 to C2, a PIN switch capacitor array K1, and a PIN switch capacitor array K2. The front-stage circuit is sequentially connected with the rear-stage circuit through an inductor L1, an inductor L2, an inductor L3 and an inductor L4 which are connected in series, the common end of the inductor L1 and the inductor L2 is grounded through a capacitor C1, the PIN switch capacitor array K1 is connected with the capacitor C1 in parallel, the common end of the inductor L3 and the inductor L4 is grounded through a capacitor C2, the PIN switch capacitor array K2 is connected with the capacitor C2 in parallel, and the common end of the inductor L2 and the inductor L3 is grounded through an inductor L5.

The front-stage circuit refers to a direct-current end or a coupling end of the two directional couplers, and the rear-stage circuit refers to four 50Ω loads. In this embodiment, the inductors L1 to L5 and the capacitors C1 to C2 form a basic double-tuning filter circuit, the inductor L5 is a coupling inductor, the circuit structures of the PIN switch capacitor array K1 and the PIN switch capacitor array K2 are identical, each of the capacitors comprises twelve parallel capacitors, the resonance frequency of the digital control frequency hopping filter can be changed by selecting one of the twelve parallel capacitors on both sides, the tuning purpose is achieved, and the center frequency of the digital control frequency hopping filter can be changed by simultaneously changing the capacitors connected into the twelve parallel capacitors on both sides, so that the frequency hopping of the digital control frequency hopping filter is realized.

Specifically, as shown in fig. 3, the PIN-switched capacitor array K1 is exemplified as including resistors R1 to R3, capacitors C3 to C4, and PIN diodes D1 to D2. One end of the resistor R1 is sequentially grounded through the cathode of the PIN diode D1, the anode of the PIN diode D1, the cathode of the PIN diode D2 and the anode of the PIN diode D2, the other end of the resistor R1 is connected with a control signal, the public end of the PIN diode D1 and the public end of the PIN diode D2 are connected with the inductance L1 and the inductance L2 through the capacitor C3, the resistor R2 is connected with the PIN diode D1 in parallel, the resistor R3 is connected with the PIN diode D2 in parallel, and the public end of the cathode of the resistor R1 and the PIN diode D1 is grounded through the capacitor C4.

The key of the digital control frequency hopping filter is the selection of variable capacitors in the PIN switch capacitor array, in this embodiment, resistors R1-R3, capacitors C3-C4 and PIN diodes D1-D2 form a capacitor array, and twelve capacitor arrays with the same structure are arranged in the PIN switch capacitor array K1 and the PIN switch capacitor array K2. When the control signal connected to one end of the resistor R1 is at a low level, the diode D1 and the diode D2 are conducted, and the capacitor C3 is connected to the circuit through the diode D1 and the diode D2 and is used as a selected variable capacitor in the PIN switch capacitor array. When the control signal connected to one end of the resistor R1 is at a high level, the diode D1 and the diode D2 are cut off, and the capacitor C3 is equivalent to suspension and is disconnected from the circuit. Therefore, the selection of the variable capacitor in the PIN switch capacitor array is realized, and the realization of the electrically-tuned band-pass filter by using different capacitor networks in the PIN diode switch to adjust the capacitor array has great advantages, and the realized filter has high technical index, stable performance and small volume, and is convenient for digital control. The capacitor C4 is used for blocking direct current, so that a control signal connected to one end of the resistor R1 is prevented from being directly connected to the ground, the resistor R1 is a current limiting resistor, and the resistor R2 and the resistor R3 are used for guaranteeing reliable cut-off of the diode D1 and the diode D2.

In this embodiment, the change of the frequency of the control center of the capacitor causes the problems of the relative bandwidth, the insertion loss, the poor standing wave ratio consistency and the like at the high end and the low end of the frequency, and the root cause of the problems is that the filter only changes the capacitance of the resonant circuit in order to be as simple as possible under the tuning condition, but the coupling circuit is not changed, and a series of electrical parameters deviate from the design requirement of the circuit, and the performance is reduced, so that the key of changing the performance of the filter is that the capacitance is adjustable, the coupling inductance also changes along with the change of the frequency, and the coupling coefficients at the high end and the low end of the frequency are as consistent as possible with the circuit requirement. Experiments prove that when the frequency hopping filter hops to the low end of the frequency, the coupling inductance is increased, and when the frequency hopping filter hops to the high end of the frequency, the coupling inductance is reduced, so that the performance of the frequency hopping filter is kept as consistent as possible in the variable frequency range.

As shown in fig. 2, the PIN switched capacitor array K1 in this embodiment further includes an inductor L6 and an NMOS tube S1, the inductor L6 is connected between the inductor L5 and ground, one end of the inductor L6 close to the inductor L5 is further connected to the drain electrode of the NMOS tube S1, one end of the inductor L6 grounded is further connected to the source electrode of the NMOS tube S1, and the single-chip microcomputer main control unit is connected to the gate electrode of the NMOS tube S1. When the singlechip main control unit judges that the frequency hopping filter hops to the low end of the frequency, the NMOS tube S1 can be controlled to be conducted, the inductor L6 is connected into a circuit, and the inductor L5 and the inductor L6 are used as the coupling inductance of the double-tuning circuit together, so that the coupling inductance is increased; when the singlechip main control unit judges that the frequency hopping filter hops to the high end of the frequency, the NMOS tube S1 can be controlled to cut off, the inductor L6 is short-circuited, and only the inductor L5 is used as the coupling inductor of the double-tuning circuit, so that the coupling inductance is reduced. Thus, the problem of poor consistency of the numerical control frequency hopping filter in high and low frequency performance is solved.

In this embodiment, when the problem that the high-low frequency performance of the digitally controlled frequency hopping filter is poor in consistency is solved, the NMOS transistor S1 is introduced, so that the insertion loss of the circuit is increased. The insertion loss caused by the MOS tube S1 is mainly determined by the on-resistance of the MOS tube S1, and the higher the resonance signal frequency is, the larger the insertion loss is. Therefore, in this embodiment, the PIN switched capacitor array K1 preferably further includes an inductor L7 and capacitors C5 to C6, the inductor L7 is connected between the inductor L6 and ground, the common end of the inductor L5 and the inductor L6 is grounded through the capacitor C5, and one end of the inductor L7 which is grounded is also grounded through the capacitor C6. As shown in fig. 4, R0 is the on-resistance of the MOS transistor S1, and when the MOS transistor S1 is turned on, the inductor L5, the inductor L7, the resistor R0, and the capacitors C5 to C6 form a low-pass filter circuit, and since the insertion loss caused by the MOS transistor S1 increases along with the resonant frequency, the coupling circuit can be equivalent to a high-pass filter circuit, so that the variation trend of the coupling circuit can be compensated by the low-pass filter circuit, and the insertion loss of the coupling circuit caused by the NMOS transistor S1 can be compensated. Here, when the NMOS transistor S1 is turned off, the inductor L5, the inductor L6, and the inductor L7 are commonly used as coupling inductors, and when the NMOS transistor S1 is turned on, the inductor L5 and the inductor L7 are used as coupling inductors.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.

Claims

1. The double-path numerical control frequency hopping wave trap is characterized by comprising a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a first directional coupler, a second directional coupler, a first numerical control frequency hopping filter, a second numerical control frequency hopping filter, a third numerical control frequency hopping filter, a fourth numerical control frequency hopping filter, a first 50 omega load, a second 50 omega load, a third 50 omega load, a fourth 50 omega load and a singlechip main control unit, wherein the second radio frequency switch comprises a 3-4 signal channel, a 1-4 signal channel and a 3-2 signal channel;

2. The two-way digitally controlled frequency trap of claim 1 wherein the first directional coupler and the second directional coupler have a frequency in the range of 1MHz to 40MHz.

3. The two-way digitally controlled frequency trap of claim 1, wherein the first digitally controlled frequency hopping filter, the second digitally controlled frequency hopping filter, the third digitally controlled frequency hopping filter, and the fourth digitally controlled frequency hopping filter are all twelve PIN switched capacitor arrays.

4. The two-way digitally controlled frequency trap of claim 3 wherein the first, second, third, or fourth digitally controlled frequency hopping filters comprise inductors L1-L5, capacitors C1-C2, PIN switched capacitor array K1, and PIN switched capacitor array K2;

5. The two-way digitally controlled frequency trap of claim 4 wherein PIN switched capacitor array K1 comprises resistors R1-R3, capacitors C3-C4 and PIN diodes D1-D2;

6. The two-way digitally controlled frequency trap of claim 5, wherein PIN switched capacitor array K1 further comprises inductor L6 and NMOS tube S1;

7. The two-way digitally controlled frequency trap of claim 6 wherein PIN switched capacitor array K1 further comprises an inductance L7 and capacitors C5-C6;