CN111863793A - Semiconductor packaging device and chip interconnection method - Google Patents

Semiconductor packaging device and chip interconnection method Download PDF

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Publication number
CN111863793A
CN111863793A CN202010739151.4A CN202010739151A CN111863793A CN 111863793 A CN111863793 A CN 111863793A CN 202010739151 A CN202010739151 A CN 202010739151A CN 111863793 A CN111863793 A CN 111863793A
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package
elements
layer
substrate
stacked
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CN202010739151.4A
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CN111863793B (en
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李骏
戴颖
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Nantong Tongfu Microelectronics Co ltd
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Nantong Tongfu Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application discloses a semiconductor package device and a chip interconnection method, the semiconductor package device includes: the packaging structure comprises a substrate, a plurality of first packaging elements and conductive adhesive, wherein the plurality of first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connection structure, and the electric connection structure is electrically connected with a bonding pad on a functional surface of the main chip and is provided with an exposed part positioned on the side surface of the first packaging element; the conductive adhesive is located on the side surfaces of the stacked first package elements and electrically connected with the electric connection structures located on the side surfaces of the first package elements and the substrate. Through the mode, the occupied space after the main chip is stacked can be reduced, and the reliability of connection between the main chip and the substrate is improved.

Description

Semiconductor packaging device and chip interconnection method
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor package device and a chip interconnection method.
Background
With the upgrading of electronic products, the functions of the electronic products are increasingly required to be diversified and the volume of the electronic products is required to be more compact, so that the volume of stacked chips needs to be compressed as much as possible in a stacking manner capable of realizing the non-functional chips.
In the prior art, a through hole is usually formed in stacked main chips in a semiconductor package device, and a conductive material is filled in the through hole to interconnect the main chips and a substrate; or the main chips in the semiconductor packaging device are arranged in a staggered and stacked mode, the upper main chip does not completely cover the lower main chip so that the bonding pads of the main chips are exposed, and bonding wires are arranged between the bonding pads of the main chips and between the bonding pads of the main chips close to the substrate and the substrate so that the main chips and the substrate are interconnected.
The inventor of the application finds that in the existing semiconductor packaging device, the structural strength of the main chip provided with the through hole is poor, the occupied volume of the staggered and laminated main chip is large, the joint of the bonding wire is weak, and the requirements of small volume and reliable connection are difficult to meet.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a semiconductor packaging device and a chip interconnection method, which can reduce the occupied space after a main chip is stacked and improve the connection reliability of the main chip and a substrate.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a semiconductor package device including: the package structure comprises a substrate, a plurality of first package elements and conductive adhesive. The first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connection structure, and the electric connection structure is electrically connected with bonding pads on the functional surface of the main chip and provided with an exposed part positioned on the side surface of the first packaging element; the conductive adhesive is located on the side surfaces of the plurality of first package elements in a stacked manner, and is electrically connected with the electric connection structures located on the side surfaces of the plurality of first package elements and the substrate.
Wherein the first package element further comprises: the first plastic package layer covers the functional surface and the side surface of the main chip, the protective layer is positioned on one side, far away from the functional surface of the main chip, of the first plastic package layer, and at least part of the electric connection structure is positioned between the first plastic package layer and the protective layer; wherein at least a portion of the electrical connection structure located at a side of the first package element is exposed from the first molding compound and the protection layer.
All the electric connection structures are positioned between the first plastic package layer and the protective layer, and the side surfaces of the electric connection structures are flush with the side surfaces of the first plastic package layer and the protective layer; or, a part of the electric connection structure is located between the first plastic package layer and the protective layer, the rest part of the electric connection structure covers the side surface of the first plastic package layer, and the rest part of the electric connection structure is flush with the side surface of the protective layer.
Wherein the semiconductor package device further comprises: and the protective adhesive is positioned on one side of the side face, far away from the plurality of first packaging elements, of the conductive adhesive and completely covers the conductive adhesive.
In order to solve the above technical problem, another technical solution adopted by the present application is: a chip interconnection method is provided, which includes: stacking a plurality of first package elements on a substrate, the first package elements including at least one main chip and an electrical connection structure electrically connected to pads on a functional surface of the main chip and having a surface exposed from a side surface of the first package element; and forming conductive adhesive on the side surfaces of the plurality of first package elements which are stacked, so that the plurality of first package elements are electrically connected with the substrate through the conductive adhesive.
Wherein, the forming of the conductive paste on the side surfaces of the plurality of first package components arranged in a stacked manner includes: forming the conductive adhesive on the side surfaces of the plurality of first package elements which are stacked in a dispensing or coating mode; after the conductive paste is formed on the side surfaces of the plurality of first package elements which are stacked, the method further includes: and forming protective glue on the side surfaces of the plurality of first packaging elements which are stacked by layers in a dispensing or coating mode.
Wherein the forming of the conductive paste on the side surfaces of the plurality of first package elements stacked on each other by means of dispensing includes: arranging a reticular clapboard on the side surface of the plurality of first packaging elements which are arranged in a stacked mode; forming the conductive adhesive on the mesh partition plate at a position corresponding to the substrate and the electrical connection structure exposed from the side surface of the first package element; the forming of the protective glue on the side surfaces of the plurality of first package elements arranged in a stacked manner by a glue dispensing manner includes: and forming the protective adhesive on the mesh-shaped partition plate at a position corresponding to the conductive adhesive so that the conductive adhesive is completely covered by the protective adhesive.
Wherein the forming of the conductive paste on the side surfaces of the plurality of first package elements stacked by layers by means of dispensing or coating comprises: rotating the plurality of first packaging elements and the substrate which are stacked until the electric connection structure on one side exposed from the side surface of the first packaging element is vertically upward and the electric connection structure on the other side is vertically downward; forming the conductive adhesive on the side surfaces of the plurality of first packaging elements which are vertically upward by means of dispensing or coating; the forming of the protective glue on the side surfaces of the plurality of first package elements arranged in a stacked manner by means of glue dispensing or coating comprises: and forming the protective adhesive on the conductive adhesive in a dispensing or coating mode so that the protective adhesive covers the conductive adhesive or covers the vertically upward side faces of the plurality of first packaging elements.
Wherein the stacking of the plurality of first package components on the substrate includes: fixing the plurality of first packaging elements by non-conductive adhesive; the plurality of first packaging elements and the substrate which are bonded and fixed through the non-conductive adhesive; or the plurality of first packaging elements are sequentially adhered and fixed on the substrate by the non-conductive adhesive.
Wherein the stacking of the plurality of first package components on the substrate includes: and sequentially and alternately laminating the plurality of first packaging elements and the plurality of radiating fins on the substrate, wherein one radiating fin is arranged between every two adjacent first packaging elements.
The beneficial effect of this application is: the electrical connection structure on the first package element in the present application is exposed from the side surface of the first package element, and the electrical connection structure is electrically connected to the pad on the functional surface, and further the conductive adhesive is electrically connected to the electrical connection structure on the side surfaces of the plurality of first package elements and the substrate, so as to interconnect the plurality of main chips and the substrate. The first packaging elements are stacked in a stacking mode and are not staggered, so that the transverse space is saved, the overall size is reduced, holes are not punched in the main chip, the yield and the reliability of the main chip are improved, the side surfaces of the first packaging elements stacked mutually are connected with each other by the conductive adhesive and are connected with the substrate, and the connection is firmer and the reliability is higher.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic cross-sectional view of one embodiment of a semiconductor package device of the present application;
FIG. 2 is a schematic cross-sectional view of one embodiment of the first package component of FIG. 1;
FIG. 3 is a schematic cross-sectional view of another embodiment of the first package component of FIG. 1
FIG. 4 is a schematic cross-sectional view of another embodiment of the first package component of FIG. 1;
FIG. 5 is a schematic cross-sectional view of another embodiment of the first package component of FIG. 1;
FIG. 6 is a schematic flow chart diagram illustrating an embodiment of a chip interconnection method according to the present application;
FIG. 7 is a schematic cross-sectional view of an embodiment corresponding to step S101 in FIG. 6;
FIG. 8 is a schematic flow chart diagram illustrating one embodiment of forming the first package component of FIG. 2;
FIG. 9 is a flowchart illustrating an embodiment corresponding to step S201 in FIG. 8;
FIG. 10a is a schematic cross-sectional view of an embodiment corresponding to step S301 in FIG. 9;
FIG. 10b is a schematic cross-sectional view of an embodiment corresponding to step S302 in FIG. 9;
FIG. 10c is a schematic cross-sectional view of an embodiment corresponding to step S303 in FIG. 9;
FIG. 10d is a schematic cross-sectional view of an embodiment corresponding to step S304 in FIG. 9;
FIG. 11 is a schematic cross-sectional view of an embodiment corresponding to step S202 in FIG. 8;
FIG. 12 is a schematic cross-sectional view of one embodiment after step S202 in FIG. 8;
FIG. 13 is a flowchart illustrating the steps S102 and a corresponding step S102 of FIG. 6;
FIG. 14a is a schematic cross-sectional view of an embodiment corresponding to step S401 in FIG. 13;
FIG. 14b is a schematic side view of an embodiment corresponding to step S402 in FIG. 13;
FIG. 14c is a schematic side view of the structure of the embodiment corresponding to step S403 in FIG. 13;
FIG. 15 is a schematic flow chart illustrating step S102 and another embodiment corresponding to the step S102 in FIG. 6;
FIG. 16a is a schematic cross-sectional view of an embodiment corresponding to step S501 in FIG. 15;
FIG. 16b is a schematic cross-sectional view of an embodiment corresponding to step S502 in FIG. 15;
fig. 16c is a schematic cross-sectional structure diagram of an embodiment corresponding to step S503 in fig. 15.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and 2, fig. 1 is a schematic cross-sectional view of an embodiment of a semiconductor package device of the present application, and fig. 2 is a schematic cross-sectional view of an embodiment of a first package component in fig. 1, where the semiconductor package device 20 includes: a substrate 202, a plurality of first package components 10 and a conductive paste 204. The plurality of first package elements 10 are stacked on the substrate 202, each first package element 10 includes at least one main chip 100 and an electrical connection structure 104, and the electrical connection structure 104 is electrically connected to a pad 1000 on a functional surface of the main chip 100 and has an exposed portion located on a side surface of the first package element 10. The conductive paste 204 is located on the side surfaces of the stacked first package elements 10, and is electrically connected to the electrical connection structure 104 and the substrate 202 located on the side surfaces of the first package elements 10.
Specifically, the first package component 10 is stacked on the substrate 202, so as to save the lateral space, thereby reducing the volume of the first package component 10 after being connected and packaged with the substrate 202. Fig. 1 is only schematic, and the number of the first package elements 10 may be selected according to actual needs, wherein the type of the main chip 100 of the first package element 10 may also be selected according to actual needs, for example, the main chip 100 may be one or more of an ASIC chip, a CPU chip, a GPU chip, an FPGA chip, and an MCU chip.
Further, the conductive paste 204 on the side surfaces of the stacked first package elements 10 electrically connects the main chips 100 to each other, and the conductive paste 204 is in contact with the substrate 202 and electrically connected to the substrate 202, thereby electrically connecting the main chips 100 to the substrate 202, and enabling electrical signals to be transmitted between the main chips 100 and between the substrates 202.
In a specific application scenario, a non-conductive adhesive (not shown) is further included between the plurality of first package elements 10, and the non-conductive adhesive adheres and fixes the first package elements 10 and adheres and fixes the surface of the first package element 10 contacting the substrate 202 and the substrate 202. The non-conductive adhesive can further protect the circuit structures on the first package elements 10, improve the safety of the circuit structures on the stacked first package elements 10, and reduce the probability of damage to the electrical elements due to accidental touch.
Further, the semiconductor package device 20 further includes: a protective glue 206. The protection adhesive 206 is disposed on a side of the conductive adhesive 204 away from the plurality of first package components 10, and completely covers the conductive adhesive 204.
In particular, fig. 1 and 2 are merely schematic, wherein the thickness of the main chip 100 is not actually as thick as shown in the figures, and may take the form of a dispensing when forming the conductive glue 204, the conductive glue 204 covering at least the electrical connection structures 104 of the sides of the first package elements 10 and being in contact with the substrate 202, so as to interconnect the electrical connection structures 104 of the sides of each first package element 10 and electrically connect with the substrate 202. The conductive paste 204 may not completely cover the side surfaces of the stacked plurality of first package components 10. The protective adhesive 206 at least completely covers the conductive adhesive 204, thereby protecting the conductive adhesive 204 from being erroneously contacted by other electrical components, and when the conductive adhesive 204 may not completely cover the side surfaces of the stacked first package components 10, the protective adhesive 206 covers the conductive adhesive 204 but not completely covers the side surfaces of the stacked first package components 10, or completely covers the side surfaces of the stacked first package components 10. When the conductive paste 204 may completely cover the side surfaces of the stacked plurality of first package members 10, the protective paste 206 covers the conductive paste 204 and completely covers the side surfaces of the stacked plurality of first package members 10.
In the semiconductor package device 20 of the present embodiment, the electrical connection structure 104 on the first package element 10 is exposed from the side surface of the first package element 10, and the electrical connection structure 104 is electrically connected to the pad 1000 on the functional surface, and the conductive paste 204 is electrically connected to the electrical connection structures 104 and the substrate 202 on the side surfaces of the plurality of first package elements 10, so as to interconnect the plurality of main chips 100 and to interconnect the substrate 202. The first package elements 10 are stacked without being staggered in a stacking manner, so that a transverse space is saved, the overall volume is reduced, holes are not formed in the main chip 100, the yield and the reliability of the main chip 100 are improved, and the side surfaces of the stacked first package elements 10 are connected with each other by the conductive adhesive 204 and the substrate 202, so that the connection is firmer and the reliability is higher.
Further, with reference to fig. 2, the first package device 10 further includes: a first molding layer 102 and a protective layer 106. The first molding compound layer 102 covers the functional surface and the side surface of the main chip 100, the protection layer 106 is located on the side of the first molding compound layer 102 away from the functional surface of the main chip 100, and at least a portion of the electrical connection structure 104 is located between the first molding compound layer 102 and the protection layer 106. Wherein at least a portion of the electrical connection structure 104 located at the side of the first package component 10 is exposed from the first molding compound layer 102 and the protection layer 106.
Part of the electrical connection structure 104 is located between the first molding compound layer 102 and the protection layer 106, the rest of the electrical connection structure 104 is located at the side of the first molding compound layer 102, and the rest of the electrical connection structure 104 is exposed from the protection layer 106. The electrical connection structure 104 located between the first molding compound layer 102 and the protection layer 106 is electrically connected to the pad 1000 on the functional surface of the chip 100, and a part of the surface of the electrical connection structure 104 located on the side surface of the first molding compound layer 102 is exposed from the side surface of the first package element 10.
Further, the electrical connection structure 104 includes a first conductive layer 1040 and a first conductive pillar 1042. The first conductive layer 1040 covers at least a surface of the first molding compound layer 102 away from the functional surface, and is electrically connected to the pad 1000. The material of the first conductive layer 1040 may be at least one of gold, silver, copper, nickel, etc., and the first conductive layer 1040 may be electroplated or deposited on the surface of the first molding compound layer 102. The edge of the first molding compound layer 102 away from the functional surface is provided with a first opening 1020, the first conductive layer 1040 further covers the sidewall of the first opening 1020, and the first conductive pillar 1042 is located at the position of the first opening 1020. The first conductive pillars 1042 fill the first openings 1020, so that the structure of the entire first package element 10 is more complete, and the first conductive pillars 1042 are located in the first openings 1020, which further saves the space of the first package element 10.
Further, all the electrical connection structures 104 of the first package element 10 are located between the first molding compound layer 102 and the protection layer 106, and the side surfaces of the electrical connection structures 104 are flush with the side surfaces of the first molding compound layer 102 and the protection layer 106; alternatively, a part of the electrical connection structure 104 is located between the first molding layer 102 and the protection layer 106, the remaining part of the electrical connection structure 104 covers the side of the first molding layer 102, and the remaining part of the electrical connection structure 104 is flush with the side of the protection layer 106.
In an application manner, referring to fig. 3, fig. 3 is a schematic cross-sectional structure view of another embodiment of the first package component in fig. 1, in which a first conductive layer 1040b in the first package component 10b covers a side surface of the first molding compound layer 102b and a side surface of the first molding compound layer 102b away from the functional surface. The first conductive layer 1040b covering the side surface of the first molding layer 102b can be electrically connected to other electrical components.
Optionally, in this application, the electrical connection structure 104b further includes a first redistribution layer 1044b, the first redistribution layer 1044b covers a side surface of the first conductive layer 1040b away from the chip 100b and is electrically connected to the first conductive layer 1040b, and a side surface of the first redistribution layer 1044b is exposed from a side surface of the first package element 10 b. The first redistribution layer 1044b is electrically connected to the pad 1000b on the chip 100b through the first conductive layer 1040b, so as to lead the pad 1000b to the side of the first package element 10b, and the protection layer 106b covers the side of the first redistribution layer 1044b away from the chip 100b, and the side of the protection layer 106b is flush with the side of the first redistribution layer 1044 b. The first redistribution layer 1044b further fixes and reinforces the first conductive layer 1040b, and the patterned first redistribution layer 1044b may be formed according to actual needs to meet different requirements.
In another application, referring to fig. 4, fig. 4 is a schematic cross-sectional structure view of another embodiment of the first package element in fig. 1, in the first package element 10c, a side surface of the first conductive layer 1040c located at one side of the first molding layer 102c protrudes out of a side surface of the first molding layer 102c, and the first conductive pillar 1042c is located at a side surface of the first molding layer 102c and is electrically connected to the first conductive layer 1040 c.
Specifically, the first package element 10c further includes a first passivation layer 105c, the first passivation layer 105c is located on the surface of the first molding layer 102c, an opening (not labeled) is formed on the first passivation layer 105c at a position corresponding to the pad 1000c on the functional surface of the chip 100c, the first conductive layer 1040c covers the surface and the side surface of the first passivation layer 105c, the first conductive layer 1040c located on the side surface of the first passivation layer 105c protrudes from the side surface of the first molding layer 102c, and the first conductive layer 1040c is electrically connected to the pad 1000c through the opening on the first passivation layer 105 c. The first conductive posts 1042c are located on the side surface of the first plastic package layer 102c and electrically connected to the first conductive layer 1040c on the side surface of the first plastic package layer 102c, and further the first conductive posts 1042c are electrically connected to the pad 1000c through the first conductive layer 1040c, and the first conductive posts 1042c are located on the side surface of the first plastic package layer 102c, so that the width of the first plastic package layer 102c is appropriately reduced, that is, the volume of the first package element 10c after being packaged is reduced.
In another application, referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of another embodiment of the first package component in fig. 1, in the first package component 10d, the electrical connection structure 104d is entirely located between the first molding compound layer 102d and the protection layer 106d, and a side surface of the electrical connection structure 104d is flush with side surfaces of the first molding compound layer 102d and the protection layer 106 d. The electrical connection structures 104d are located on the side away from the functional surface of the chip 100d, so as to separate the electrical connection structures 104d from the chip 100d as much as possible.
Further, the electrical connection structure 104d includes a first conductive layer 1040d and a first conductive pillar 1042 d. The first conductive layer 1040d is located on a side of the first molding compound layer 102d away from the functional surface, and is electrically connected to the pad 1000 d. The first conductive post 1042d is located on a side of the first conductive layer 1040d away from the functional surface and at an edge of the first conductive layer 1040 d.
Specifically, a first passivation layer 105d is further included between the first molding compound layer 102d and the protection layer 106d, an opening (not labeled) is disposed on the first passivation layer 105d at a position corresponding to the pad 1000d on the functional surface of the chip 100d, the first conductive layer 1040d covers a surface of the first passivation layer 105d and a sidewall of the opening, and the first conductive layer 1040d is electrically connected to the pad 1000d through the opening on the first passivation layer 105 d. The first conductive pillar 1042d is located at an edge of the first conductive layer 1040d and electrically connected to the first conductive layer 1040d, and the first conductive pillar 1042d located at the edge is exposed from a side surface of the first package element 10d, so as to lead the pad 1000d on the chip 100d to the side surface of the chip 100 d.
Further, the protection layer 106d covers at least one side of the first conductive layer 1040d away from the functional surface and the side surface opposite to the first conductive pillar 1042 d. The side of the first conductive pillar 1042d away from the functional surface can be exposed from the passivation layer 106d, and further electrically connected to other electrical elements by wire bonding, so that the position for wire bonding is reserved. The side of the first conductive pillar 1042d away from the functional surface can also be covered by the protection layer 106d, so as to reduce the probability of short circuit caused by the mis-touch of the first conductive pillar 1042 d.
Referring to fig. 6, fig. 6 is a schematic flowchart illustrating a chip interconnection method according to an embodiment of the present application, the chip interconnection method including:
step S101: a plurality of first packaging elements are arranged on the substrate in a stacked mode, each first packaging element comprises at least one main chip and an electric connection structure, the electric connection structure is electrically connected with the bonding pads on the functional surface of the main chip, and the electric connection structure is provided with a surface exposed from the side face of the first packaging element.
Specifically, referring to fig. 1 and fig. 2, the first package device 10 is packaged in advance, the pads 1000 on the functional surface of the main chip 100 are electrically connected to the electrical connection structures 104, and the electrical connection structures 104 are at least partially exposed from the side surface of the first package device 10, and the exposed portions can be electrically connected to other electrical devices, so as to be electrically connected to the electrical connection structures 104 on the side surface of the main chip 100, and then electrically connected to the pads 1000 on the functional surface of the main chip 100.
In a specific application scenario, the plurality of first package elements 10 are fixed by non-conductive adhesive (not shown), and the plurality of first package elements 10 and the substrate 202 after being fixed by non-conductive adhesive are fixed by non-conductive adhesive. Namely, a plurality of first package components 10 are bonded to the substrate 202.
In another specific application scenario, the plurality of first package elements 10 are sequentially fixed to the substrate 202 by non-conductive adhesive. One of the first package components 10 is bonded to the substrate 202, and the other first package components 10 are stacked in sequence and bonded by a nonconductive adhesive.
Specifically, the non-conductive adhesive can further protect the circuit structures on the first package elements 10, improve the safety of the stacked circuit structures on the plurality of first package elements 10, and reduce the probability of damage to the electrical elements due to accidental touches.
Optionally, referring to fig. 7, fig. 7 is a schematic cross-sectional structural view of an embodiment corresponding to step S101 in fig. 6, in which a plurality of first package components 10 and a plurality of heat sinks 208 are sequentially and alternately stacked on the substrate 202, wherein one heat sink 208 is disposed between adjacent first package components 10. The heat sink 208 may be a metal sheet with a groove on both sides, or a metal sheet with an inclined angle on both sides to achieve better heat dissipation effect, so that the heat of the main chip 100 can be dissipated as soon as possible, thereby improving the stability of the main chip 100 and prolonging the service life thereof. When the heat sink 208 is fixed, the adjacent first package components 10 are fixed by coating a non-conductive adhesive on the surfaces of the two sides of the heat sink 208, which can contact with the first package components 10.
In one embodiment, referring to fig. 8, fig. 8 is a schematic flow chart of an embodiment of forming the first package device of fig. 2, including:
step S201: and forming a first plastic package layer on the side surfaces and one side of the functional surfaces of the main chips, wherein the bonding pads on the functional surfaces of the main chips are exposed out of the first plastic package layer, and a first opening is formed on the first plastic package layer between the adjacent main chips.
In an application manner, please refer to fig. 9, where fig. 9 is a flowchart illustrating an embodiment corresponding to step S201 in fig. 8, and step S201 specifically includes:
step S301: and pasting one side of the non-functional surfaces of the main chips on the first carrier plate.
Specifically, referring to fig. 10a, fig. 10a is a schematic cross-sectional structure diagram of an embodiment corresponding to step S301 in fig. 9, the first carrier 200 in fig. 10a only schematically shows one of the regions, in practical applications, the first carrier 200 may be a larger region, and is divided into a plurality of small regions, and a peelable adhesive is used to adhere the non-functional surface side of the main chip 100 to the first carrier 200 in each of the small regions.
Step S302: the first die is arranged on one side of the functional surfaces of the main chips, wherein a plurality of first convex parts are arranged on one side, facing the main chips, of the first die, and the first convex parts correspond to areas between the adjacent main chips.
Specifically, referring to fig. 10b, fig. 10b is a schematic cross-sectional structure view of an embodiment corresponding to step S302 in fig. 9, after the first mold 300 is disposed on the plurality of main chips 100, the main chips 100 are spaced apart by the first protrusions 3000 on the first mold 300. Fig. 10b is merely schematic, and when N main chips 100 are provided, N-1 first protrusions 3000 between the corresponding main chips 100 on the first mold 300, two first protrusions 3000 at the outermost edge on the first mold 300, and the width of the first protrusions 3000 between the corresponding main chips 100 of the first mold 300 is twice the width of the first protrusions 3000 at the outermost edge. The first protrusion 3000 may contact the first carrier 200 or may have a certain distance from the first carrier 200 as shown in fig. 10 b.
Step S303: and forming a first plastic package layer on the side surface and one side of the functional surface of the main chip, exposing the bonding pad on the functional surface of the main chip from the first plastic package layer, and forming a first opening on the first plastic package layer at a position corresponding to the first convex part.
Specifically, referring to fig. 10c, fig. 10c is a schematic cross-sectional structure view of an embodiment corresponding to step S303 in fig. 9, the first carrier 200, the main chip 100 and the first mold 300 are disposed in a mold cavity for performing mold sealing to form the first mold layer 102, and the first mold 300 is schematically moved away from the main chip 100 in fig. 10c to make the illustration more clear. As shown in fig. 10c, the first protrusion 3000 is spaced apart from the first carrier 200, and a space is formed between the bottom of the first opening 1020 of the first molding compound layer 102 and the first carrier 200. If the first protrusion 3000 contacts the first carrier 200, the first carrier 200 is exposed from the first opening 1020 after the first molding compound layer 102 is formed. If the end of the first protrusion 3000 contacting the first mold 300 is farther from the first carrier 200 than the functional surface of the main chip 100, the first molding compound 102 is formed to cover the functional surface of the main chip 100. Specifically, the size of the first mold 300 and the position where the first mold 300 is disposed may be selected according to actual needs.
Step S304: the first mold is removed.
Specifically, referring to fig. 10d, fig. 10d is a schematic cross-sectional structure view of an embodiment corresponding to step S304 in fig. 9, when the first molding compound layer 102 does not cover the functional surface of the main chip 100, the first mold 300 is removed, and when the first molding compound layer 102 covers the functional surface of the main chip 100, the first molding compound layer 102 on one side of the functional surface of the main chip 100 is ground to expose the bonding pad 1000 after the first mold 300 is removed.
Step S202: and forming an electric connection structure on the first plastic packaging layer, wherein the electric connection structure is electrically connected with the bonding pad and covers the surface of the first opening.
Specifically, referring to fig. 11, fig. 11 is a schematic cross-sectional view of an embodiment corresponding to step S202 in fig. 8, in which an electrical connection structure 104 is formed on a functional surface side of the main chip 100, the electrical connection structure 104 is electrically connected to the pad 1000, and the electrical connection structure 104 covers a surface of the first opening 1020.
Specifically, the conductive layer 1040 is formed on the side of the first molding compound layer 102 away from the functional surface of the main chip 100, the first conductive layer 1040 is formed by sputtering, and after the first conductive layer 1040 is formed, the first conductive layer 1040 is etched to retain a required portion of the first conductive layer 1040, so that the pad 1000 is independent, and the first conductive layer 1040 is fine and is more tightly bonded to the first molding compound layer 102 made of resin. The first conductive layer 1040 covers the first molding layer 102 and the surface of the first opening 1020, and the first conductive layer 1040 is electrically connected to the pad 1000. A first conductive pillar 1042 is formed at a remaining position in the first opening 1020, and the first conductive pillar 1042 is electrically connected to the first conductive layer 1040.
Further, referring to fig. 12, fig. 12 is a schematic cross-sectional structure view of an embodiment corresponding to the step S202 in fig. 8, in which a protection layer 106 is formed on a side of the electrical connection structure 104 away from the functional surface of the main chip 100, and the protection layer 106 covers a surface of the electrical connection structure 104.
Step S203: and cutting off part of the first plastic packaging layer and part of the electric connection structure between the adjacent main chips to obtain a first packaging element containing a single main chip, wherein the side surface of the first packaging element is provided with the electric connection structure electrically connected with the bonding pad.
Specifically, referring to fig. 2 again, and referring to fig. 10a to fig. 10d in combination, a portion of the protection layer 106, the electrical connection structure 104 and the first molding compound layer 102 are cut apart, and the first carrier board 200 is removed to form the first package device 10 including a single main chip 100, the electrical connection structure 104 is electrically connected to the bonding pad 1000, the top and the bottom of the electrical connection structure 104 are covered by the protection layer 106 and the first molding compound layer 102, respectively, and only the portion exposed from the side surface of the first package device 10 can be electrically connected to other electrical devices or the main chip 100.
It should be noted that the above is only one forming way for forming the first package component 10 of the present application, and other forming methods are also included in other embodiments, such as: a first molding layer 102 is formed on the side surfaces and the functional surface sides of the plurality of main chips 100, wherein the side surface of the first molding layer 102 away from the functional surface is flat, and the bonding pads 1000 on the functional surface of the main chip 100 are exposed from the first molding layer 102. A first conductive layer 1040 is formed on the first molding layer 102, and the first conductive layer 1040 is electrically connected to the pad 1000 exposed from the first molding layer 102. A first conductive pillar 1042 is formed on the first conductive layer 1040 at a position corresponding to a position between adjacent main chips 100, and the first conductive pillar 1042 is electrically connected to the pad 1000 through the first conductive layer 1040. Forming the passivation layer 106 on the side of the electrical connection structure 104 away from the functional surface, and cutting off a portion of the first molding compound layer 102, a portion of the electrical connection structure 104 and a portion of the passivation layer 106 between adjacent main chips 100 to obtain the first package element 10 including a single main chip 100, wherein the first conductive pillar 1042 has a surface exposed from a side surface of the first package element 10.
Step S102: and forming conductive adhesive on the side surfaces of the plurality of first packaging elements which are stacked, so that the plurality of first packaging elements are electrically connected with the substrate through the conductive adhesive.
Specifically, referring to fig. 1 and fig. 2 again, fig. 1 is only schematic, wherein the thickness of the main chip 100 is not actually as thick as that shown in the figure, so that the conductive paste 204 can be formed on the side surfaces of the stacked first package devices 10 by dispensing, and of course, the conductive paste 204 can also be formed on the side surfaces of the stacked first package devices 10 by coating.
Further, step S102 is followed by: the protective paste 206 is formed by dispensing or coating on the side surfaces of the plurality of first package components 10 stacked.
Specifically, when the conductive paste 204 is formed on the side of the stacked first package elements 10 by dispensing, the protective paste 206 is formed on the side of the conductive paste 204 away from the first package elements 10 by dispensing or coating. That is, when the conductive paste 204 may not completely cover the side surfaces of the stacked plurality of first package elements 10, the protective paste 206 covers the conductive paste 204 but does not completely cover the side surfaces of the stacked plurality of first package elements 10, or completely covers the side surfaces of the stacked plurality of first package elements 10. When the conductive paste 204 is formed on the side of the stacked first package elements 10 by coating, the protective paste 206 is formed on the side of the conductive paste 204 away from the first package elements 10 by coating. That is, when the conductive paste 204 may completely cover the side surfaces of the stacked plurality of first package components 10, the protective paste 206 covers the conductive paste 204 and completely covers the side surfaces of the stacked plurality of first package components 10.
In an application manner, please refer to fig. 13, where fig. 13 is a flowchart illustrating an embodiment corresponding to step S102 and step S102 in fig. 6, where step S102 and the following steps specifically include:
step S401: a mesh spacer is provided on a side surface of the plurality of first package elements stacked.
Specifically, referring to fig. 14a, fig. 14a is a schematic cross-sectional structure view of an embodiment corresponding to step S401 in fig. 13, in which one end of the mesh spacer 209 is in contact with the substrate 202 and is disposed on a side surface of the first package element 10.
Step S402: and forming conductive adhesive on the mesh partition plate at positions corresponding to the electric connection structure and the substrate exposed from the side surface of the first packaging element.
Specifically, referring to fig. 14b, fig. 14b is a schematic side view of an embodiment corresponding to step S402 in fig. 13, a mesh-shaped spacer 209 is disposed on the substrate 202 from the direction of arrow a shown in fig. 14a, the mesh-shaped spacer 209 is divided into a plurality of meshes (not shown), a plurality of dots are dispensed at positions corresponding to the electrical connection structures 104 on the side surfaces of the stacked first package devices 10, the sticky conductive paste 204 slides down and is connected to each other by gravity, and a portion of the conductive paste 204 is disposed on the substrate 202.
Step S403: and forming protective glue on the mesh-shaped partition plate at the position corresponding to the conductive glue so as to completely cover the conductive glue.
Specifically, referring to fig. 14c, fig. 14c is a schematic side view of an embodiment corresponding to step S403 in fig. 13, a glue is dispensed on a position corresponding to the conductive glue 204 in the grid of the mesh spacer 209, the usage amount of the protective glue 206 is greater than that of the conductive glue 204, and the conductive glue 204 is covered by the protective glue 206. The mesh spacer 209 has a plurality of meshes, the baffle plates in the meshes can prevent the conductive adhesive 204 and the protective adhesive 206 from being excessively accumulated on one side close to the substrate 202 due to gravity, and the mesh spacer 209 enables the conductive adhesive 204 and the protective adhesive 206 to be relatively uniformly disposed on the side surfaces of the plurality of first package components 10 which are stacked.
In another application, please refer to fig. 15, fig. 15 is a flowchart illustrating another embodiment corresponding to step S102 and step S102 in fig. 6, where step S102 and the following steps specifically include:
step S501: and rotating the stacked first packaging elements and the substrate until the electric connection structure exposed from the side surface of the first packaging element on one side is vertically upward and the electric connection structure on the other side is vertically downward.
Specifically, referring to fig. 16a, fig. 16a is a schematic cross-sectional structure view of an embodiment corresponding to step S501 in fig. 15, in which a plurality of first package elements 10 and a substrate 202 are integrally rotated, one side of each first package element 10 is vertically upward, and the other side of each first package element 10 is vertically downward.
Step S502: and forming the conductive adhesive on the vertical upward side surfaces of the first packaging elements in a dispensing or coating mode.
Specifically, referring to fig. 16b, fig. 16b is a schematic cross-sectional structure view of an embodiment corresponding to step S502 in fig. 15, in which a glue is dispensed or a conductive adhesive 204 is directly coated on a vertically upward side surface of the first package element 10, and since the side surface of the first package element 10 is in a relatively horizontal state, the sticky conductive adhesive 204 is substantially kept in a uniform state under the action of gravity.
Step S503: and forming protective glue on the conductive glue in a dispensing or coating mode so that the protective glue covers the conductive glue or covers the side faces of the plurality of first packaging elements, which are vertically upward.
Specifically, referring to fig. 16c, fig. 16c is a schematic cross-sectional structure diagram of an embodiment corresponding to step S503 in fig. 15, where the conductive adhesive 204 is formed by a dispensing or coating process to form the protective adhesive 206 at a position corresponding to the conductive adhesive 204, and the protective adhesive 206 at least covers the conductive adhesive 204.
Optionally, the protective glue 206 completely covers the vertically upward side of the first package element 10 to protect the conductive glue 204.
The chip interconnection method provided by the embodiment improves the flatness of the conductive adhesive 204 and the protective adhesive 206, and prevents the conductive adhesive 204 and the protective adhesive 206 from being accumulated on one side close to the substrate 202, so that the packaged device has a tighter structure and higher reliability after being packaged.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (10)

1. A semiconductor package device, comprising:
a substrate;
the first packaging elements are stacked on the substrate and comprise at least one main chip and an electric connection structure, and the electric connection structure is electrically connected with bonding pads on the functional surface of the main chip and provided with an exposed part positioned on the side surface of the first packaging element;
and the conductive adhesive is positioned on the side surfaces of the plurality of first packaging elements which are stacked and arranged, and is electrically connected with the electric connection structures positioned on the side surfaces of the plurality of first packaging elements and the substrate.
2. The semiconductor package device of claim 1,
the first package component further includes: the first plastic package layer covers the functional surface and the side surface of the main chip, the protective layer is positioned on one side, far away from the functional surface of the main chip, of the first plastic package layer, and at least part of the electric connection structure is positioned between the first plastic package layer and the protective layer;
wherein at least a portion of the electrical connection structure located at a side of the first package element is exposed from the first molding compound and the protection layer.
3. The semiconductor package device of claim 2,
all the electric connection structures are positioned between the first plastic package layer and the protective layer, and the side surfaces of the electric connection structures are flush with the side surfaces of the first plastic package layer and the protective layer; or,
and part of the electric connection structure is positioned between the first plastic packaging layer and the protective layer, the rest part of the electric connection structure covers the side surface of the first plastic packaging layer, and the rest part of the electric connection structure is flush with the side surface of the protective layer.
4. The semiconductor package device of claim 1, further comprising:
and the protective adhesive is positioned on one side of the side face, far away from the plurality of first packaging elements, of the conductive adhesive and completely covers the conductive adhesive.
5. A chip interconnection method, comprising:
stacking a plurality of first package elements on a substrate, the first package elements including at least one main chip and an electrical connection structure electrically connected to pads on a functional surface of the main chip and having a surface exposed from a side surface of the first package element;
and forming conductive adhesive on the side surfaces of the plurality of first package elements which are stacked, so that the plurality of first package elements are electrically connected with the substrate through the conductive adhesive.
6. The chip interconnection method of claim 5,
the forming of the conductive paste on the side surfaces of the plurality of first package elements arranged in a stacked manner includes:
forming the conductive adhesive on the side surfaces of the plurality of first package elements which are stacked in a dispensing or coating mode;
after the conductive paste is formed on the side surfaces of the plurality of first package elements which are stacked, the method further includes:
and forming protective glue on the side surfaces of the plurality of first packaging elements which are stacked by layers in a dispensing or coating mode.
7. The chip interconnection method of claim 6,
the forming of the conductive paste on the side surfaces of the plurality of first package elements arranged in a stacked manner by a paste dispensing method includes:
arranging a reticular clapboard on the side surface of the plurality of first packaging elements which are arranged in a stacked mode;
forming the conductive adhesive on the mesh partition plate at a position corresponding to the substrate and the electrical connection structure exposed from the side surface of the first package element;
the forming of the protective glue on the side surfaces of the plurality of first package elements arranged in a stacked manner by a glue dispensing manner includes: and forming the protective adhesive on the mesh-shaped partition plate at a position corresponding to the conductive adhesive so that the conductive adhesive is completely covered by the protective adhesive.
8. The chip interconnection method of claim 6,
the forming of the conductive paste by means of dispensing or coating on the side surfaces of the plurality of first package elements arranged in a stacked manner includes:
rotating the plurality of first packaging elements and the substrate which are stacked until the electric connection structure on one side exposed from the side surface of the first packaging element is vertically upward and the electric connection structure on the other side is vertically downward;
forming the conductive adhesive on the side surfaces of the plurality of first packaging elements which are vertically upward by means of dispensing or coating;
the forming of the protective glue on the side surfaces of the plurality of first package elements arranged in a stacked manner by means of glue dispensing or coating comprises:
and forming the protective adhesive on the conductive adhesive in a dispensing or coating mode so that the protective adhesive covers the conductive adhesive or covers the vertically upward side faces of the plurality of first packaging elements.
9. The chip interconnection method of claim 5, wherein the disposing the plurality of first package components on the substrate in a stacked manner comprises:
fixing the plurality of first packaging elements by non-conductive adhesive; the plurality of first packaging elements and the substrate which are bonded and fixed through the non-conductive adhesive; or,
and fixing the plurality of first packaging elements on the substrate sequentially through non-conductive adhesive bonding.
10. The chip interconnection method of claim 5, wherein the disposing the plurality of first package components on the substrate in a stacked manner comprises:
and sequentially and alternately laminating the plurality of first packaging elements and the plurality of radiating fins on the substrate, wherein one radiating fin is arranged between every two adjacent first packaging elements.
CN202010739151.4A 2020-07-28 2020-07-28 Semiconductor packaging device and chip interconnection method Active CN111863793B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413798A (en) * 2013-08-02 2013-11-27 南通富士通微电子股份有限公司 Chip structure and chip packaging structure
CN111106078A (en) * 2019-12-16 2020-05-05 山东砚鼎电子科技有限公司 Multi-chip integrated packaging structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103413798A (en) * 2013-08-02 2013-11-27 南通富士通微电子股份有限公司 Chip structure and chip packaging structure
CN111106078A (en) * 2019-12-16 2020-05-05 山东砚鼎电子科技有限公司 Multi-chip integrated packaging structure

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