CN111863734A - Power MOSFET, semiconductor device and substrate thinning method thereof - Google Patents

Power MOSFET, semiconductor device and substrate thinning method thereof Download PDF

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CN111863734A
CN111863734A CN201910362271.4A CN201910362271A CN111863734A CN 111863734 A CN111863734 A CN 111863734A CN 201910362271 A CN201910362271 A CN 201910362271A CN 111863734 A CN111863734 A CN 111863734A
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power mosfet
substrate
mosfet
layer
semiconductor device
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郑英豪
严大生
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Abstract

The invention provides a power MOSFET, a semiconductor device and a method for thinning a substrate thereof, wherein the power MOSFET at least comprises: an adhesion barrier layer formed under the substrate; and an electroplated copper layer formed underneath the adhesion barrier layer; wherein the thickness of the power MOSFET is less than or equal to 300 μm. The method comprises the following steps: forming a temporary adhesion carrier on the front surface of the semiconductor device; turning over the semiconductor device and thinning the substrate; sequentially forming an adhesion barrier layer and an electroplated copper layer on the substrate; and removing the temporary adhesion carrier. The method not only can reduce the substrate of the power MOSFET device to be less than 100 mu m with simple process and low cost, but also reduces the total resistance of the power MOSFET, particularly the reduction of the resistance is obvious in a low-voltage power MOSFET, and thereby the performance of the power MOSFET is improved.

Description

Power MOSFET, semiconductor device and substrate thinning method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a power MOSFET, a semiconductor device and a substrate thinning method thereof.
Background
Power MOSFETs, i.e. power MOS field effect transistors. The power MOSFET mostly adopts a vertical conductive structure, which is also called as VMOSFET (vertical MOSFET), so that the voltage resistance and current resistance of the MOSFET device are greatly improved. One power MOSFET common in the prior art has a structure as shown in fig. 1, which is a trench type power MOSFET that includes a drift region 103 located over an n + substrate 102, the drift region 103 being an n-epitaxial layer. Above the drift region 103, a p-well or p-body region 104 is provided, and in the p-well 104, a heavily doped n + region 105 is provided. The power MOSFET further comprises a gate 106 located above the drift region 103, and a gate dielectric layer 107 is further provided between the gate 106 and the p-well 104. A source 108 is provided over the p-well 104, while a back gold 101 is also provided on the other side of the substrate to act as a drain.
The on-resistance of a power MOSFET is comprised of several parts including source diffusion resistance, channel resistance, junction resistance, drift region resistance, and substrate resistance. For power MOSFETs of different voltages, the contribution of each part of the resistance to the total resistance of the power MOSFET is different. However, in both high-voltage power MOSFETs and low-voltage power MOSFETs, the contribution of the substrate resistance to the total resistance is not negligible, and especially in low-voltage power MOSFETs, the substrate resistance is a large proportion of the total resistance of the MOSFET, so it is a very effective way to reduce the substrate resistance and thus the total resistance of the MOSFET by reducing the thickness of the substrate. On the other hand, the thickness of the substrate cannot be too thin, and therefore the substrate needs to be kept at a thickness such that the heat generated from the device can be uniformly and widely distributed, thereby preventing the temperature rise in the MOSFET device.
In the MOSFET, a laminated structure including a source, a gate, a body region and a drift region may be collectively referred to as a device region, and has a typical thickness of 3 to 15 μm, a typical thickness of a back metal of 1 to 3 μm, and a typical thickness of a substrate of 50 to 300 μm, so that there is a very large operating space for reducing the resistance of the substrate by thinning the substrate.
Therefore, it is a great technical challenge for the skilled person how to provide a MOSFET with a low substrate resistance and how to thin the substrate of a power MOSFET device to below 50 μm with a simple process and low cost.
Disclosure of Invention
In view of the above, an embodiment of the present invention provides a power MOSFET, which at least includes:
a substrate;
a drift region formed over the substrate;
a body region, a gate and a source formed over the drift region;
an adhesion barrier layer formed under the substrate; and
an electroplated copper layer formed below the adhesion barrier layer.
Optionally, the power MOSFET comprises a vertical conductivity type VMOSFET.
Optionally, the power MOSFET comprises a PMOSFET or an NMOSFET.
Optionally, the power MOSFET comprises a trench MOSFET or a planar MOSFET.
Optionally, the drift region comprises an n-epitaxial layer or a p-epitaxial layer.
Optionally, the source comprises a metal.
Optionally, the gate comprises at least one of polysilicon, metal or metal silicide.
Optionally, the adhesion barrier layer comprises at least one of Ta, TaN, Ti, TiN.
Optionally, the electroplated copper layer includes a copper thin film layer grown by an electroplating method on the copper seed layer.
Optionally, the substrate comprises silicon.
Optionally, the substrate has a thickness of 100 μm or less.
Optionally, the thickness of the electroplated copper layer is 50-300 μm.
In the power MOSFET, the resistance of the substrate can be greatly reduced by reducing the thickness of the substrate to be less than 100 μm, so that the total resistance of the power MOSFET is reduced, and the reduction of the resistance is particularly obvious in a low-voltage power MOSFET. The thickness of the electroplated copper layer is set to be 50-300 mu m, so that reliable support is provided for the whole power MOSFET, and the phenomenon that the whole power MOSFET device cannot be supported due to the fact that the substrate is too thin can be avoided.
The present invention also provides a semiconductor device comprising any of the power MOSFETs described above.
According to a second aspect, an embodiment of the present invention provides a method for thinning a substrate, where the substrate is a substrate of a semiconductor device, the method including the steps of:
Forming a drift region over a substrate;
forming a body region, a gate and a source over the drift region to form a front side of the semiconductor device;
forming a temporary adhesion carrier on the front side of the semiconductor device;
turning over the semiconductor device and thinning the substrate;
and sequentially forming an adhesion barrier layer and an electroplated copper layer on the substrate.
Optionally, in the above method, the semiconductor device comprises a power MOSFET.
Optionally, in the above method, the power MOSFET comprises a vertical conduction type VMOSFET.
Optionally, in the above method, the power MOSFET comprises a PMOSFET or an NMOSFET.
Optionally, in the above method, the power MOSFET comprises a trench MOSFET or a planar MOSFET.
Optionally, in the above method, the drift region includes an n-epitaxial layer.
Optionally, in the above method, the source electrode includes a metal.
Optionally, in the above method, the gate electrode includes at least one of polysilicon, metal, or metal silicide.
Optionally, in the above method, the adhesion barrier layer includes at least one of Ta, TaN, Ti, and TiN.
Optionally, in the above method, the electroplated copper layer includes a copper thin film layer grown by an electroplating method on the copper seed layer.
Optionally, in the above method, the substrate comprises silicon.
Optionally, in the above method, the substrate has a thickness of 100 μm or less.
Optionally, in the above method, the thickness of the electroplated copper layer is 50 to 300 μm.
The method not only can reduce the substrate of the power MOSFET device to be less than 100 mu m with simple process and low cost, but also can greatly reduce the resistance of the substrate by reducing the thickness of the substrate to be less than 100 mu m, thereby reducing the total resistance of the power MOSFET, particularly obviously reducing the resistance in a low-voltage power MOSFET and improving the performance of the power MOSFET.
Drawings
The features and advantages of the present invention will be more clearly understood by reference to the accompanying drawings, which are illustrative and not to be construed as limiting the invention in any way, and in which:
fig. 1 shows a schematic diagram of a power MOSFET in the prior art.
Fig. 2 shows two commonly used techniques for thinning a substrate.
Fig. 3 shows a schematic diagram of a power MOSFET with a thinned substrate in the present invention.
Fig. 4-8 show a schematic diagram of a method of thinning a substrate of a power MOSFET in accordance with the present invention.
Fig. 9 is a schematic flow chart showing the thinning of the substrate of the power MOSFET in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
Fig. 2 shows two commonly used techniques for thinning a substrate. Fig. 2(a) shows a conventional thinning technique in which an adhesive layer 202 such as an adhesive tape is first applied to a glass 201, and then a wafer 203 is placed on the adhesive layer 202, and the wafer 203 is polished. This thinning technique cannot thin the wafer 203 to a thickness of, for example, 100 μm or less, and on the other hand, the wafer 203 after grinding may form a sharp edge, which may cause concentrated stress on the edge of the wafer 203, which may result in easy damage to the wafer 203 and a reduction in yield. To further thin the substrate, the most popular method at present is the drum-out method, which is extremely useful for back-end processes, especially for chip probing. As shown in fig. 2(b), the wafer 204 obtained by the ultra-thin grinding method forms an extra-drum ring, which can be removed by a subsequent process. However, the taibu ultra-thin grinding method also has the following problems: 1. for a silicon substrate, the thickness can be reduced to about 50 μm at most, and if the thickness is lower than 50 μm, the probability of wafer breakage is obviously improved; 2. the equipment used in the Taibu ultra-thin grinding method needs to be purchased, and corresponding equipment, machines and the like for subsequent processing of the Taibu ring are also needed, so that the grinding cost is greatly increased compared with the traditional thinning technology.
The present invention provides a power MOSFET, fig. 3 shows a schematic diagram of a power MOSFET with a thinned substrate according to the present invention, the power MOSFET at least comprises: a substrate 303; a drift region 304 formed over the substrate 303; a p-implanted region 305, an n-implanted region 306, and an interlayer dielectric layer 307 formed over the drift region 304; an adhesion barrier layer 302 formed under the substrate 303; and an electroplated copper layer 301 formed under said adhesion barrier layer 302; the thickness of the substrate 303 is less than 50 μm, and the thickness of the electroplated copper layer 301 is 50-300 μm. The power MOSFET also includes a gate and source, not shown, and the p-implant region 305 serves as the body region of the MOSFET. The drift region 304 comprises an n-epitaxial layer.
In the power MOSFET, the resistance of the substrate 303 can be greatly reduced by thinning the thickness of the substrate 303 to 50 μm or less, thereby reducing the total resistance of the power MOSFET, and the reduction of the resistance is significant particularly in a low-voltage power MOSFET. The thickness of the electroplated copper layer 301 is set to be 50-300 mu m, so that reliable support is provided for the whole power MOSFET, and the problem that the whole power MOSFET device cannot be supported due to the fact that the thickness of the substrate 303 is too thin can be avoided. Optionally, the thickness of the substrate 303 is 3 to 30 μm, and particularly preferably, the thickness of the substrate 303 is 3 to 15 μm.
The power MOSFET shown in fig. 3 is a vertical conductivity type VMOSFET, and this type of MOSFET has higher withstand voltage performance and current capability.
The power MOSFET shown in fig. 3 is a trench MOSFET. Optionally, the power MOSFET may also be a planar MOSFET.
The source comprises a metal and the gate comprises at least one of polysilicon, a metal, or a metal silicide.
Optionally, the adhesion barrier layer 302 includes at least one of Ta, TaN, Ti, TiN. Preferably, the adhesion barrier layer 302 comprises Ta or TaN, which are well suited as adhesion barriers due to the high diffusion activation energy of copper in metallic Ta and TaN films.
The electroplated copper layer 301 includes a copper thin film layer grown by electroplating on a copper seed layer.
The substrate 303 comprises silicon, for example the substrate 303 may be an n + silicon substrate.
In the power MOSFET, the electroplated copper layer with a certain thickness is formed on the back surface of the power MOSFET, so that the support is provided for the whole MOSFET device, and the problem that the support is insufficient due to insufficient thickness of a silicon substrate is solved.
Example two
An embodiment of the present invention provides a method for thinning a substrate, where the substrate is a semiconductor device, especially a substrate of a power MOSFET, fig. 4 to 8 show schematic diagrams of a method for thinning a substrate of a power MOSFET in the present invention, fig. 9 shows a schematic diagram of a process for thinning a substrate of a power MOSFET in the present invention, and the method for thinning a substrate is described in detail below with reference to fig. 4 to 9, and includes the following steps:
S1, forming a temporary bonding carrier on the front surface of the MOSFET;
in this step, in conjunction with fig. 4, a drift region 402 is formed over a substrate 401; a p-implant region 403, an n-implant region 404, and an interlayer dielectric layer 405 are formed over the drift region 402. The power MOSFET also includes a gate and a source, not shown, and the p-implant region 403 serves as the body region of the MOSFET. The drift region 402 comprises an n-epitaxial layer. Forming a body region, a gate and a source over the drift region 402 to form a front side of the semiconductor device; a temporary adhesion carrier 406 is formed on the front side of the semiconductor device. The temporary adhesion carrier 406 has a typical thickness of 50 to 300 μm.
The source comprises a metal, the gate comprises at least one of polysilicon, a metal or a metal silicide, and the substrate comprises silicon.
The power MOSFET shown in fig. 4 is a vertical conductivity type VMOSFET, and this type of MOSFET has higher withstand voltage performance and current capability.
The power MOSFET shown in fig. 4 is a trench MOSFET. Optionally, the power MOSFET may also be a planar MOSFET. The power MOSFET includes a vertical conductivity type VMOSFET. The power MOSFET includes a PMOSFET or an NMOSFET.
S2, turning the wafer and thinning the silicon substrate;
In this step, the substrate 401 is flipped over and the substrate 401 is thinned to below 50 μm, in conjunction with fig. 5. In the thinning process, since the classic thickness of the temporary adhesion carrier 406 is 50-300 μm, the temporary adhesion carrier 406 can provide better support, and therefore, the substrate 401 can be ground by adopting a traditional grinding method and the substrate 401 can be thinned to be less than 50 μm. With the conventional polishing method, it is not necessary to use expensive equipment such as that used in the super drum ultra-thin polishing method, and therefore, the substrate 401 can be thinned to 50 μm or less without greatly increasing the cost.
In the power MOSFET, the resistance of the substrate 401 can be greatly reduced by thinning the thickness of the substrate 401 to 50 μm or less, thereby reducing the total resistance of the power MOSFET, and the reduction of the resistance is significant particularly in a low-voltage power MOSFET. Optionally, the thickness of the substrate 401 is 3-30 μm, and it is especially preferable that the thickness of the substrate 401 is 3-15 μm, because the decrease in the thickness of the substrate 401 further decreases the total resistance of the power MOSFET, which improves the performance of the power MOSFET.
S3, depositing a barrier layer and a seed crystal layer on the silicon substrate;
In this step, in conjunction with fig. 6, an adhesion barrier layer 407 and a copper seed layer 408 are sequentially formed on the thinned substrate 401. Wherein the adhesion barrier layer 407 comprises at least one of Ta, TaN, Ti, TiN. Preferably, the adhesion barrier 407 comprises Ta or TaN, which are well suited as adhesion barriers due to the high diffusion activation energy of copper in metallic Ta and TaN films. The adhesion barrier 407 may be deposited using PVD. Adhesion barrier 407 may increase adhesion properties between silicon substrate 401 and a metal layer, such as copper seed layer 408, while may prevent copper from diffusing into silicon substrate 401 and epitaxial layer drift region 402.
S4, electroplating a copper layer;
referring to fig. 7, in this step, a copper thin film layer is grown on the copper seed layer 408 by an electroplating method to form an electroplated copper layer 409. Wherein the thickness of the electroplated copper layer is 50-300 μm.
The thickness of the electroplated copper layer 409 is set to be 50-300 mu m, so that reliable support is provided for the whole power MOSFET, and the problem that the whole power MOSFET device cannot be supported due to the fact that the thinned substrate 401 is too thin can be avoided.
S5, removing the temporary bonding carrier;
in this step, in conjunction with fig. 8, the wafer is flipped again so that the power MOSFET is right side up and the temporary adhesion carrier 406 is removed to obtain a power MOSFET with a thinned substrate.
The method not only can reduce the substrate of the power MOSFET device to be less than 50 mu m with simple process and low cost, but also can greatly reduce the resistance of the substrate by reducing the thickness of the substrate to be less than 50 mu m, thereby reducing the total resistance of the power MOSFET, particularly obviously reducing the resistance in a low-voltage power MOSFET and improving the performance of the power MOSFET.
The foregoing embodiments are merely illustrative of the principles of this invention and its efficacy, rather than limiting it, and various modifications and variations can be made by those skilled in the art without departing from the spirit and scope of the invention, which is defined in the appended claims.

Claims (26)

1. A power MOSFET, comprising:
a substrate;
a drift region formed over the substrate;
a body region, a gate and a source formed over the drift region;
an adhesion barrier layer formed under the substrate; and
an electroplated copper layer formed under the adhesion barrier layer;
wherein the thickness of the power MOSFET is less than or equal to 300 μm.
2. The power MOSFET of claim 1 wherein the power MOSFET comprises a vertical conductivity type VMOSFET.
3. The power MOSFET of claim 1 or 2, wherein the power MOSFET comprises a PMOSFET or an NMOSFET.
4. The power MOSFET of claim 1 or 2, wherein the power MOSFET comprises a trench MOSFET or a planar MOSFET.
5. The power MOSFET of claim 1 or 2 wherein the drift region comprises an n-epitaxial layer or a p-epitaxial layer.
6. The power MOSFET of claim 1 or 2 wherein the source comprises a metal.
7. The power MOSFET of claim 1 or 2 wherein the gate comprises at least one of polysilicon, metal, or metal silicide.
8. The power MOSFET of claim 1 or 2, wherein the adhesion barrier layer comprises at least one of Ta, TaN, Ti, TiN.
9. The power MOSFET of claim 1 or 2 wherein the electroplated copper layer comprises a copper thin film layer grown by electroplating on a copper seed layer.
10. The power MOSFET of claim 1 or 2 wherein the substrate comprises silicon.
11. The power MOSFET of claim 1 or 2 wherein the substrate has a thickness of 100 μm or less.
12. The power MOSFET of claim 1 or 2, wherein the thickness of the electroplated copper layer is 50-300 μm.
13. A semiconductor device, characterized in that it comprises a power MOSFET according to any of claims 1-12.
14. A method for thinning a substrate, wherein the substrate is a substrate of a semiconductor device, the method comprising the steps of:
forming a drift region over a substrate;
forming a body region, a gate and a source over the drift region to form a front side of the semiconductor device;
forming a temporary adhesion carrier on the front side of the semiconductor device;
turning over the semiconductor device and thinning the substrate;
sequentially forming an adhesion barrier layer and an electroplated copper layer on the substrate; and
removing the temporary adhesion carrier.
15. The method of claim 14, wherein the semiconductor device comprises a power MOSFET.
16. The method of claim 15, wherein the power MOSFET comprises a vertical conductivity type VMOSFET.
17. The method of claim 15, wherein the power MOSFET comprises a PMOSFET or an NMOSFET.
18. The method of claim 15, wherein the power MOSFET comprises a trench MOSFET or a planar MOSFET.
19. The method of any of claims 14-18, wherein the drift region comprises an n-epitaxial layer or a p-epitaxial layer.
20. The method of any of claims 14-18, wherein the source electrode comprises a metal.
21. The method of any of claims 14-18, wherein the gate comprises at least one of polysilicon, metal, or metal silicide.
22. The method of any of claims 14-18, wherein the adhesion barrier layer comprises at least one of Ta, TaN, Ti, TiN.
23. The method of any of claims 14-18, wherein the electroplated copper layer comprises a copper thin film layer grown by electroplating on a copper seed layer.
24. The method of any of claims 14-18, wherein the substrate comprises silicon.
25. The method of any one of claims 14-18, wherein the substrate has a thickness of 100 μ ι η or less.
26. The method according to any one of claims 14 to 18, wherein the thickness of the electroplated copper layer is 50 to 300 μm.
CN201910362271.4A 2019-04-30 2019-04-30 Power MOSFET, semiconductor device and substrate thinning method thereof Pending CN111863734A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090102026A1 (en) * 2007-10-18 2009-04-23 International Business Machines Corporation Semiconductor-on-insulator substrate with a diffusion barrier
CN101432846A (en) * 2006-04-06 2009-05-13 费查尔德半导体有限公司 Method for bonding a semiconductor substrate to a metal substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101432846A (en) * 2006-04-06 2009-05-13 费查尔德半导体有限公司 Method for bonding a semiconductor substrate to a metal substrate
US20090102026A1 (en) * 2007-10-18 2009-04-23 International Business Machines Corporation Semiconductor-on-insulator substrate with a diffusion barrier

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