CN111863109A - Three-dimensional flash memory interlayer error rate model and evaluation method - Google Patents
Three-dimensional flash memory interlayer error rate model and evaluation method Download PDFInfo
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- CN111863109A CN111863109A CN202010650473.1A CN202010650473A CN111863109A CN 111863109 A CN111863109 A CN 111863109A CN 202010650473 A CN202010650473 A CN 202010650473A CN 111863109 A CN111863109 A CN 111863109A
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention discloses a three-dimensional flash memory interlayer error rate model and an evaluation method. The three-dimensional flash memory is widely used in solid state disks due to its characteristics of large capacity, high performance, and the like. However, due to the influence of the process and physical mechanism, the three-dimensional flash has obvious reliability difference between different layers, which is mainly indicated by the fact that the error rate has a specific change rule with the increase of the stacked layers. Aiming at the modeling of the error rate between layers of the three-dimensional flash memory, the characteristics of the flash memory can be more effectively known, the data layout can be optimized, and the data service life can be predicted. The method models the error rate and the programming/erasing times of the three-dimensional flash memory layer, the data storage time and the word line number. The model evaluates the error rate of the three-dimensional flash memory layer, provides information for data layout optimization and data life prediction, and is beneficial to designing a more reliable and longer-acting flash memory storage system. The invention has great significance for improving the reliability of the solid state disk, reducing the cost and relevant industrial application.
Description
Technical Field
The invention belongs to the field of computer storage, and particularly relates to a three-dimensional flash memory interlayer error rate model and an evaluation method.
Background
In the past decade, a storage device based on a mechanical hard disk is the mainstream device in the storage field, but a solid state hard disk using a flash memory as a storage medium is rapidly developing due to its low energy consumption, high reliability and low access delay, and gradually eats the market share of the mechanical hard disk. In particular, in recent years, the three-dimensional flash memory technology has rapidly increased the storage capacity and rapidly decreased the price, but in a large-scale storage system, the solid state disk also has a reliability problem.
Three-dimensional flash memory contains several stacked layers per block, such as 64 layers, 96 layers at maturity, and 128 layers or higher in the future. Each layer contains a number of word lines, each word line containing a number of types of flash memory pages. Due to the influence of flash memory architecture, stacking process and physical structure, the interference and physical effect on different layers are different, and finally the difference between the performance and reliability of the layers is shown. With the continuous improvement of the three-dimensional stacking layer number and the evolution of the multi-bit storage technology, the difference becomes more and more obvious, and the data storage capacity of partial layers becomes odd. The inter-layer reliability difference can be characterized by the error rate of the word line or the error rate of the page, and modeling the inter-layer reliability difference is helpful for optimizing data layout, predicting data life and the like. Therefore, with the increasingly complex characteristics of the existing and future three-dimensional flash memories with higher stacking levels and the severe problems caused by interlayer differences, an interlayer error rate model is established and evaluated, and the method has important significance for optimizing data distribution, reducing storage cost and ensuring reliability in the solid state disk.
Disclosure of Invention
Aiming at the research of the requirements and the flash memory characteristics, the invention provides a three-dimensional flash memory interlayer error rate model and an evaluation method, aiming at quantifying interlayer difference according to the relation of the three-dimensional flash memory interlayer error rates, and evaluating the error rate of any word line under the conditions of different programming/erasing times and data storage time combinations through the model so as to optimize the word line with higher predicted error rate and ensure the data reliability of a solid state disk.
To achieve the above object, according to an aspect of the present invention, there is provided a three-dimensional flash memory inter-layer error rate model and an evaluation method, including the steps of:
(1) testing the three-dimensional flash memory, and collecting error rate data of each page of the three-dimensional flash memory at different programming/erasing times and data storage time;
(2) performing data statistics, wherein an average value of data Error rates of different blocks in the step (1) is used as an Error Rate (Bit Error Rate, BER) under the combination condition, for example, BER (pe, rt, pg) represents an Error Rate of a pg page after an rt time passes under pe programming/erasing;
(3) analyzing a statistical result;
(4) selecting an appropriate model to match the statistics, such as r ═ F (pe, rt, wl), where pe denotes the number of program/erase times, rt denotes the data retention time, wl denotes the word line number, and r denotes the error rate;
(5) Substituting the data in the step (2) to obtain a model parameter table;
(6) inputting a word line wl 'to be evaluated, the corresponding programming/erasing times pe' and the data storage time rt 'into a model, and operating the model through a parameter table to obtain an error rate r'.
The invention comprises a model establishing module and an error rate evaluating module: wherein the steps (1) to (5) are model building modules; and (6) an error rate evaluation module.
In the present invention, the test of step (1) comprises the following steps:
a) randomly selecting a batch of blocks which are not subjected to any programming/erasing operation in a three-dimensional flash memory chip, wherein no bad blocks can exist;
b) dividing the batch of blocks into a plurality of sets, respectively carrying out programming/erasing operations of different files on each set, reading each page and recording the error rate of each page, such as BER (1,0, pg), BER (1000,0, pg), BER (2000,0, pg) and the like;
c) data saving operations, i.e. placing, are performed on all sets, reading all pages each month (or each week) and recording each page error rate, such as BER (1,0, pg), BER (1,30, pg), BER (1,60, pg), … …, BER (1000,0, pg), BER (1000,30, pg), etc.
In the present invention, the model in step (4) is based on the statistical analysis result in step (3), and the BER distribution between layers and the page number pg can be represented by a piecewise linear model.
In the invention, because one word line comprises a plurality of pages of different types, the establishment of the interlayer error rate model can be calculated by taking the word line as a unit or by the page type.
In the present invention, in step (2), besides taking the average value of the data error rates of different blocks to measure BER, the highest value, median, etc. may also be taken.
In the invention, the data written in the programming test is random, and the data written in different word lines are completely different so as to simulate the scene of storing real data in the solid state disk.
The claimed technical solution is as follows:
a three-dimensional flash memory interlayer error rate model and an evaluation method comprise the following steps:
(1) testing the three-dimensional flash memory, and collecting error rate data of each page of the three-dimensional flash memory under different programming/erasing times and data storage time;
(2) performing data statistics, namely taking the average value or the highest value or the median of the data of different blocks in the step (1) as the error rate under the combination condition, recording the error rate as BER (pe, rt, pg), and representing the error rate of the pg page after the rt time passes under pe programming/erasing;
(3) analyzing a statistical result;
(4) selecting a proper model to match the statistical result in the step (3), wherein r is F (pe, rt, wl), where pe represents the programming/erasing times, rt represents the data storage time, wl represents the word line number, and r represents the error rate;
(5) Substituting the data in the step (2) to obtain a model parameter table;
(6) inputting a word line (wl ') to be evaluated, a corresponding programming/erasing time (pe') and a data storage time (rt ') into a model, and operating the model through a parameter table to obtain an error rate (r').
Preferably, the test described in step (1) comprises the steps of:
a) randomly selecting a batch of blocks which are not subjected to any programming/erasing operation in a three-dimensional flash memory chip, wherein no bad blocks can exist;
b) dividing the batch of blocks into a plurality of sets, respectively carrying out programming/erasing operation of different files on each set, reading each page and recording the error rate of each page;
c) and performing data storage operation, namely placing, on all the sets, reading all the pages at certain time intervals and recording the error rate of each page.
The certain time period of the interval in the step c) is every month or every week.
Preferably, the model in step (4) is based on the statistical analysis result in step (3), and the BER distribution between layers and the page number pg are represented by a piecewise linear model.
Preferably, the inter-layer error rate model is established in units of word lines, and can be counted according to page types.
Preferably, the data written in the programming test in step (1) is random, and the data written on different word lines are completely different, so as to simulate the scene of storing real data in the solid state disk.
In general, the above technical solutions contemplated by the present invention can achieve the following beneficial effects:
the method can model the interlayer error rate, the programming/erasing times and the data storage time of the three-dimensional flash memory, and predict the error rate of different layers of the three-dimensional flash memory. The three-dimensional flash memory interlayer error rate model provided by the method is based on flash memory test and data analysis, so that the obtained model has high feasibility and reliability, and is beneficial to designing a special error rate prediction model, thereby providing basic information for reliability optimization of a flash memory storage system.
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FIG. 1 is a block diagram of a three-dimensional flash memory inter-layer error rate model and evaluation method steps according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The overall idea of the invention is to model the interlayer error rate, the programming/erasing times and the data storage time of the three-dimensional flash memory through flash memory test and data analysis. Specifically, as shown in fig. 1, the model building includes the following steps:
(1) and (3) data testing: testing the three-dimensional flash memory, and collecting error rate data of each page of the three-dimensional flash memory at different programming/erasing times and data storage time; specifically, the method comprises the following steps:
a) randomly selecting a batch of blocks which are not subjected to any programming/erasing operation in a three-dimensional flash memory chip, wherein no bad blocks can exist;
b) dividing the batch of blocks into a plurality of sets, respectively carrying out programming/erasing operations of different files on each set, reading each page and recording the error rate of each page, such as BER (1,0, pg), BER (1000,0, pg), BER (2000,0, pg) and the like;
c) data saving operations, i.e. placing, are performed on all sets, reading all pages each month (or each week) and recording each page error rate, such as BER (1,0, pg), BER (1,30, pg), BER (1,60, pg), … …, BER (1000,0, pg), BER (1000,30, pg), etc.
(2) Performing data statistics, wherein an average value of data Error rates of different blocks in the step (1) is used as an Error Rate (Bit Error Rate, BER) under the combination condition, for example, BER (pe, rt, pg) represents an Error Rate of a pg page after an rt time passes under pe programming/erasing;
(3) Analyzing a statistical result;
(4) selecting an appropriate model to match the statistics, such as r ═ F (pe, rt, wl), where pe denotes the number of program/erase times, rt denotes the data retention time, wl denotes the word line number, and r denotes the error rate;
(5) substituting the data in the step (2) to obtain a model parameter table;
(6) inputting a word line wl 'to be evaluated, the corresponding programming/erasing times pe' and the data storage time rt 'into a model, and operating the model through a parameter table to obtain an error rate r'.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A three-dimensional flash memory interlayer error rate model and an evaluation method are characterized by comprising the following steps:
(1) testing the three-dimensional flash memory, and collecting error rate data of each page of the three-dimensional flash memory under different programming/erasing times and data storage time;
(2) performing data statistics, namely taking the average value or the highest value or the median of the data of different blocks in the step (1) as the error rate under the combination condition, recording the error rate as BER (pe, rt, pg), and representing the error rate of the pg page after the rt time passes under pe programming/erasing;
(3) Analyzing a statistical result;
(4) selecting a proper model to match the statistical result in the step (3), wherein r is F (pe, rt, wl), where pe represents the programming/erasing times, rt represents the data storage time, wl represents the word line number, and r represents the error rate;
(5) substituting the data in the step (2) to obtain a model parameter table;
(6) inputting a word line (wl ') to be evaluated, a corresponding programming/erasing time (pe') and a data storage time (rt ') into a model, and operating the model through a parameter table to obtain an error rate (r').
2. The method of claim 1, wherein the testing in step (1) comprises the steps of:
(1) randomly selecting a batch of blocks which are not subjected to any programming/erasing operation in a three-dimensional flash memory chip, wherein no bad blocks can exist;
(2) dividing the batch of blocks into a plurality of sets, respectively carrying out programming/erasing operation of different files on each set, reading each page and recording the error rate of each page;
(3) and performing data storage operation, namely placing, on all the sets, reading all the pages at certain time intervals and recording the error rate of each page.
3. The method of claim 2, wherein the time interval in step (3) is monthly or weekly.
4. The method as claimed in claim 1, wherein the model in step (4) is based on the statistical analysis result in step (3), and the BER distribution between layers and the page number pg are represented by a piecewise linear model.
5. The method as claimed in claim 1, wherein the inter-layer error rate model is established in units of word lines or by page type.
6. The method as claimed in claim 1, wherein the data written during the programming test in step (1) is random, and the data written on different word lines are completely different, so as to simulate the scenario of real data stored in the solid state disk.
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| CN113126925A (en) * | 2021-04-21 | 2021-07-16 | 山东英信计算机技术有限公司 | Member list determining method, device and equipment and readable storage medium |
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