CN111863106B

CN111863106B - Flash memory error correction method and device

Info

Publication number: CN111863106B
Application number: CN201910351203.8A
Authority: CN
Inventors: 彭攀来; 霍文捷; 秦义
Original assignee: Wuhan Hikstorage Technology Co ltd
Current assignee: Wuhan Hikstorage Technology Co ltd
Priority date: 2019-04-28
Filing date: 2019-04-28
Publication date: 2022-08-05
Anticipated expiration: 2039-04-28
Also published as: CN111863106A

Abstract

The application discloses a flash memory error correction method and device, and belongs to the technical field of solid-state storage. The flash memory error correction method provided by the embodiment of the application receives a read request, the read request carries a position identifier of a first position of a flash memory and is used for reading data stored in the first position, when an error indication returned by the flash memory is received, a plurality of error messages of the read request are added into a plurality of first error correction linked lists, and error correction is performed in parallel according to the error messages in the plurality of first error correction linked lists. According to the method, the error information in the first error correction linked lists is corrected in parallel by adding the error information into the first error correction linked lists, so that the error correction time is shortened, and the error correction efficiency is improved.

Description

Flash memory error correction method and device

Technical Field

The present application relates to the field of solid state storage technology. In particular, to a flash memory error correction method and apparatus.

Background

The NAND Flash (NAND gate Flash) memory is one of Flash memories, is suitable for storing a large amount of data, and is increasingly widely applied in the technical field of solid-state storage. The NAND Flash memory mainly stores data in three forms of Die, Block, and Page. One Die includes a plurality of blocks, one Block includes a plurality of pages, and one Page includes a plurality of bits. When the number of erroneous bits in a Page exceeds the hardware error correction capability of the flash memory, data error correction needs to be performed by an error correction method.

In the related technology, when error correction is performed, error information corresponding to error data is mainly added to a linked list, and then error correction is performed on the error information in the linked list one by one through an error correction method.

However, in the related art, only one error message in the linked list can be corrected each time the error is corrected, which results in long error correction time and low error correction efficiency.

Disclosure of Invention

The embodiment of the application provides a flash memory error correction method and device, which can solve the problems of long error correction time and low error correction efficiency. The technical scheme is as follows:

in one aspect, a flash memory error correction method is provided, and the method includes:

receiving a read request, wherein the read request carries a position identifier of a first position of a flash memory and is used for requesting to read data stored in the first position;

when an error indication returned by the flash memory is received, adding a plurality of error messages of the read request into a plurality of first error correction linked lists;

and correcting errors in parallel according to the error information in the first error correction linked lists.

In one possible implementation manner, the adding the plurality of error messages of the read request to the plurality of first error correction linked lists includes:

determining a Die where each error message is located;

and for each error message, adding the error message into an error correction linked list corresponding to the Die according to the Die where the error message is located.

In another possible implementation manner, the performing error correction in parallel according to the error information in the plurality of first error correction linked lists includes:

error correction is carried out on the error information of the first error correction linked list;

and in the error correction process, error information in other first error correction linked lists in the plurality of first error correction linked lists is corrected in parallel.

In another possible implementation manner, the error correcting the error information of the first error correction linked list includes:

determining a first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list, wherein the first error correction method sequence comprises at least one error correction method;

correcting error information in the header by the first error correction method sequence;

when the error correction of the error information in the header is successful or the error correction is finished through the last error correction method in the first error correction method sequence, deleting the error information in the header;

and adding the next error information after the header in the first error correction linked list into the header, and then executing the step of determining the first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list until the error correction of the last error information in the first error correction linked list is finished.

In another possible implementation manner, the determining, according to the error information in the header of the first error correction linked list, a first error correction method sequence of the error information in the header includes:

determining an error type of error information in the header;

and determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods.

In another possible implementation manner, before determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods, the method further includes:

acquiring a first error number of error information in an error Block Block when data errors occur in the flash memory last time;

acquiring a second error number of error information in the error Block when the data is in error currently;

correspondingly, the determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods includes:

and determining the first error correction method sequence according to the first error number, the second error number, the error type and the plurality of error correction methods.

In another possible implementation manner, the determining the first error correction method sequence according to the first error number, the second error number, the error type, and the plurality of error correction methods includes:

and when the second error number is not larger than the first error number, selecting a first error correction method sequence corresponding to the error type from a plurality of error correction method sequences according to the error type and the corresponding relation between the error type and the error correction method sequence.

In another possible implementation, the first sequence of error correction methods includes a Read Retry error correction method;

the error correction of the error information in the header by the first error correction method sequence includes:

selecting a first offset voltage value from a first Retry table, and correcting error information in the header based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value;

and when the error information in the header cannot be corrected successfully through the reference voltage value and each first offset voltage value in the first retry table, selecting a second offset voltage value from a second retry table, and correcting the error information in the header through the reference voltage value and the selected second offset voltage value.

In another possible implementation manner, the first error correction method sequence further includes calibrating a Calibration error correction method;

determining a voltage regulation range of the first error message according to a reference voltage value and a first offset interval of the Calibration error correction method;

determining a third voltage value from the voltage regulation range;

and correcting error information in the header according to the third voltage value.

In another possible implementation manner, the method further includes:

adding a plurality of error messages which fail to be subjected to sequence error correction through the first error correction method into a second error correction linked list;

and correcting error information in the second error correction linked list one by one through a second error correction method sequence, wherein the second error correction method sequence comprises at least one error correction method.

In another possible implementation manner, the second error correction method sequence includes a software low density parity check code SLDPC error correction method and a redundant array of independent disks RAID error correction method;

the step of performing error correction on the error information in the second error correction linked list one by one through a second error correction method sequence includes:

when the errors are not corrected by the SLDPC error correction method and the RAID error correction method at the current first time, the error information in the second error correction linked list is corrected one by the SLDPC error correction method;

and for the error information which fails to be corrected by the SLDPC error correction method at present, when the error information is not corrected by the SLDPC error correction method and the RAID error correction method at the present second time, correcting the error information which fails to be corrected by the SLDPC error correction method by the RAID error correction method.

In another aspect, there is provided a flash memory error correction apparatus, the apparatus including:

a receiving module, configured to receive a read request, where the read request carries a location identifier of a first location of a flash memory, and is used to request to read data stored in the first location;

the adding module is used for adding a plurality of error messages of the reading request into a plurality of first error correction linked lists when receiving error indications returned by the flash memory;

and the error correction module is used for correcting errors in parallel according to the error information in the plurality of first error correction linked lists.

In a possible implementation manner, the adding module is further configured to determine a Die where each error message is located; and for each error message, adding the error message into an error correction linked list corresponding to the Die according to the Die where the error message is located.

In another possible implementation manner, the error correction module is further configured to correct error information of the first error correction linked list; and in the error correction process, error information in other first error correction linked lists in the plurality of first error correction linked lists is corrected in parallel.

In another possible implementation manner, the error correction module is further configured to determine a first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list, where the first error correction method sequence includes at least one error correction method; correcting error information in the header by the first error correction method sequence; when the error correction of the error information in the header is successful or the error correction is finished through the last error correction method in the first error correction method sequence, deleting the error information in the header; and adding the next error information after the header in the first error correction linked list into the header, and then executing the step of determining the first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list until the error correction of the last error information in the first error correction linked list is finished.

In another possible implementation manner, the error correction module is further configured to determine an error type of the error information in the header; and determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods.

In another possible implementation manner, the apparatus further includes:

the acquisition module is used for acquiring a first error number of error information in an error Block when data errors occur in the flash memory last time; acquiring a second error number of error information in the error Block when the data is in error currently;

the error correction module is further configured to determine the first error correction method sequence according to the first error number, the second error number, the error type, and the plurality of error correction methods.

In another possible implementation manner, the error correction module is further configured to select, when the second error number is not greater than the first error number, a first error correction method sequence corresponding to the error type from a plurality of error correction method sequences according to the error type and a correspondence between the error type and the error correction method sequence.

the error correction module is further configured to select a first offset voltage value from a first Retry table, and correct error information in the header based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value; and when the error information in the header cannot be corrected successfully through the reference voltage value and each first offset voltage value in the first retry table, selecting a second offset voltage value from a second retry table, and correcting the error information in the header through the reference voltage value and the selected second offset voltage value.

the error correction module is further configured to determine a voltage adjustment range of the first error message according to a reference voltage value of the Calibration error correction method and a first offset interval; determining a third voltage value from the voltage regulation range; and correcting error information in the header according to the third voltage value.

In another possible implementation manner, the adding module is further configured to add a plurality of error messages that have failed in sequence error correction by the first error correction method to a second error correction linked list;

the error correction module is further configured to perform error correction on the error information in the second error correction linked list one by one through a second error correction method sequence, where the second error correction method sequence includes at least one error correction method.

In another possible implementation manner, the second error correction method sequence includes a software low density parity check code (SLDPC) error correction method and a Redundant Array of Independent Disks (RAID) error correction method;

the error correction module is further configured to correct the error information in the second error correction linked list one by one through the SLDPC error correction method when no error correction is performed through the SLDPC error correction method and the RAID error correction method at the current first time; and for the error information which fails to be corrected by the SLDPC error correction method at present, when the error information is not corrected by the SLDPC error correction method and the RAID error correction method at the present second time, correcting the error information which fails to be corrected by the SLDPC error correction method by the RAID error correction method.

In another aspect, a computing device is provided, which includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the bus; a memory for storing a computer program; and the processor is used for executing the program stored in the memory and realizing the method steps of any one of the flash memory error correction methods. .

In another aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, and when being executed by a processor, the computer program implements the method steps of any of the above flash memory error correction methods.

The technical scheme provided by the embodiment of the application has the following beneficial effects:

the embodiment of the application provides a flash memory error correction method, which comprises the steps of receiving a read request, wherein the read request carries a position identifier of a first position of a flash memory and is used for reading data stored in the first position, adding a plurality of error messages of the read request into a plurality of first error correction linked lists when an error indication returned by the flash memory is received, and correcting errors in parallel according to the error messages in the plurality of first error correction linked lists. According to the method, the error information in the first error correction linked lists is corrected in parallel by adding the error information into the first error correction linked lists, so that the error correction time is shortened, and the error correction efficiency is improved.

Drawings

Fig. 1 is a schematic diagram of an application scenario of flash memory error correction according to an embodiment of the present application;

FIG. 2 is a flowchart of a flash memory error correction method according to an embodiment of the present disclosure;

FIG. 3 is a flowchart of a flash memory error correction method according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating state switching of a Read Retry error correction method according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating state switching of a Calibration error correction method according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating state switching of an SLDPC error correction method according to an embodiment of the present application;

fig. 7 is a schematic diagram illustrating a state switching of a RAID error correction method according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an error correction process by a RAID error correction method according to an embodiment of the present application;

fig. 9 is a schematic diagram of error correction of error information by a first error correction method sequence and a second error correction method sequence according to an embodiment of the present application;

FIG. 10 is a schematic diagram illustrating error correction of error information by a second error correction method sequence according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a flash memory error correction apparatus according to an embodiment of the present application;

fig. 12 is a block diagram of a computing device according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the present application more clear, the following describes the embodiments of the present application in further detail.

An embodiment of the present application provides an application scenario of flash memory error correction, and referring to fig. 1, the application scenario includes: terminal 101, computing device 102. The terminal 101 and the computing device 102 may be connected by a wireless connection or a wired connection. The computing device 102 includes a flash memory therein for storing data. The computing device 102 may be a terminal or a server, among others. For ease of distinction, the computing device 102 may be referred to as a first terminal when it is a terminal; the terminal 101 may be referred to as a second terminal. When the computing device 102 is a first terminal, the application scenario is that a second terminal obtains data from a flash memory of the first terminal. When the computing device 102 is a server, the application scenario is that the terminal 101 obtains data from a flash memory of the server. In the embodiment of the present application, the computing device 102 is taken as a server for explanation.

When the terminal 101 reads data from the flash memory in the computing device 102, it sends a read request to the computing device 102, where the read request carries a location identifier of a first location of the flash memory, and is used to request to read the data stored in the first location. The computing device 102 receives the read request and reads the data stored at the first location. However, due to the occurrence of a bad Block in the flash memory or due to the long time interval between the time of storage and the time of reading, electrons in the memory cells in the flash memory are lost, and the actual voltage value of the electrons deviates from the reference voltage value, resulting in an error in the computing device 102 when reading the data in the first location. When the number of erroneous bits of the data at the first location is not greater than the first threshold, error correction can be directly performed through hardware of the flash memory, so as to obtain the data stored at the first location. However, when the Bit number of the data error in the first location is greater than the first threshold and exceeds the hardware error correction capability in the flash memory, a data error occurs. When a data error occurs, the flash memory returns an error indication of a read error to the computing device 102, and after receiving the error indication returned by the flash memory, the computing device 102 needs to correct the error information of the read request by an error correction method.

In the related technology, a plurality of error messages of a read request are added into an error correction linked list, when the error correction linked list is corrected by a computing device through an error correction method, only a first error message in the error correction linked list can be corrected, after the first error message is corrected, no matter the error correction is successful or failed, the first error message is deleted from the error correction linked list, a second error message in the error correction linked list replaces the position of the original first error message to serve as the first error message, and the error message is corrected through the error correction method. In the related art, only one error correction linked list is provided, and only the first error message in the error correction linked list can be corrected during each error correction, so that only the first error message in the error correction linked list can be corrected during the error correction by the current error correction method, other error messages cannot be corrected by other error correction methods, and the error correction efficiency is low.

In the embodiment of the application, when data errors occur, the computing device adds a plurality of error messages of the read request to the plurality of first error correction linked lists, and performs error correction on the error messages in the plurality of first error correction linked lists in parallel, so that the error correction time is shortened, and the error correction efficiency is improved.

When the computing device 102 successfully corrects the error information of the read request by the error correction method to obtain the data at the first position, the computing device can directly output the data at the first position to the terminal 101, so that the terminal 101 successfully obtains the data at the first position; the computing device 102 may output the data of the first location to the terminal 101 the next time the terminal 101 acquires the data of the first location without directly outputting the data of the first location after the data of the first location is obtained.

It should be noted that one Die includes multiple blocks, one Block includes multiple pages, one Page includes multiple Bit numbers, and data is written in the Page in the form of Bit numbers. When reading data at the first location is erroneous, multiple Bit numbers may be erroneous, typically in units of mKB. The computing device 102 determines the Page with mKB bits as mKB, determines the Block with the Page, determines the Die with the Block according to the Block, that is, determines the storage address corresponding to mKB bits, and encapsulates the storage address corresponding to mKB bits to obtain an error message. And the data of the first position comprises data on at least one Die, and when the data of the first position is read based on the read request with errors, the read request corresponds to a plurality of error messages. For each error message, the computing device 102 may correct the error using the flash error correction method provided by the embodiments of the present application. In the embodiment of the present application, the essence of error correction of the error information is to re-read data corresponding to the memory address from the flash memory, based on the memory address corresponding to the Bit number of mKB in the error information.

An embodiment of the present application provides a flash memory error correction method, referring to fig. 2, the method includes:

step 201: and receiving a read request, wherein the read request carries a position identifier of a first position of the flash memory and is used for requesting to read data stored in the first position.

Step 202: when an error indication returned by the flash memory is received, a plurality of error messages of the read request are added to a plurality of first error correction linked lists.

Step 203: and correcting errors in parallel according to the error information in the first error correction linked lists.

In one possible implementation, adding a plurality of error messages of the read request to a plurality of first error correction linked lists includes:

determining a Die where each error message is located;

and for each error message, adding the error message into an error correction linked list corresponding to the Die according to the Die in which the error message is positioned.

In another possible implementation manner, performing error correction in parallel according to error information in a plurality of first error correction linked lists includes:

error information in the header is corrected through a first error correction method sequence;

and adding the next error information after the head in the first error correction linked list into the head, and then executing the step of determining the first error correction method sequence of the error information in the head according to the error information in the head of the first error correction linked list until the error correction of the last error information in the first error correction linked list is finished.

In another possible implementation manner, the determining a first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list includes:

determining an error type of the error information in the header;

and determining a first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods.

In another possible implementation manner, before determining a first error correction method sequence corresponding to an error type according to the error type and a plurality of error correction methods, the method further includes:

acquiring a first error number of error information in an error Block when data errors occur in a flash memory last time;

acquiring a second error number of error information in the error Block when the data error occurs at present;

correspondingly, according to the error type and a plurality of error correction methods, determining a first error correction method sequence corresponding to the error type, including:

and determining a first error correction method sequence according to the first error number, the second error number, the error type and a plurality of error correction methods.

In another possible implementation manner, determining a first error correction method sequence according to the first error number, the second error number, the error type, and the plurality of error correction methods includes:

and when the second error number is not larger than the first error number, selecting a first error correction method sequence corresponding to the error type from the error correction method sequences according to the error type and the corresponding relation between the error type and the error correction method sequence.

error correction is carried out on error information in the header through a first error correction method sequence, and the method comprises the following steps:

selecting a first offset voltage value from the first Retry table, and correcting error information in the header of the table based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value;

and when the error information in the header cannot be corrected successfully through the reference voltage value and each first offset voltage value in the first retry table, selecting a second offset voltage value from the second retry table, and correcting the error information in the header through the reference voltage value and the selected second offset voltage value.

determining a voltage regulation range of first error information according to a reference voltage value and a first offset interval of a Calibration error correction method;

determining a third voltage value from the voltage regulation range;

In another possible implementation manner, the method further includes:

adding a plurality of error messages which fail in sequence error correction through a first error correction method into a second error correction linked list;

and correcting the error information in the second error correction linked list one by one through a second error correction method sequence, wherein the second error correction method sequence comprises at least one error correction method.

and correcting the error information in the second error correction linked list one by one through a second error correction method sequence, wherein the method comprises the following steps:

when the error is not corrected by the SLDPC error correction method and the RAID error correction method at the current first time, the error information in the second error correction linked list is corrected one by the SLDPC error correction method;

and for the error information which fails to be corrected by the SLDPC error correction method at present, when the error information is not corrected by the SLDPC error correction method and the RAID error correction method at the present second time, the error information which fails to be corrected by the SLDPC error correction method is corrected by the RAID error correction method.

An embodiment of the present application provides a flash memory error correction method, which is applied to a computing device, and with reference to fig. 3, the method includes:

step 301: the computing device receives a read request, wherein the read request carries a location identifier of a first location of the flash memory and is used for requesting to read data stored at the first location.

The computing device may include a flash memory, and the flash memory stores a plurality of data, and the plurality of data are stored in different locations in the flash memory. When the terminal reads data from the computing device, the terminal sends a read request to the computing device, wherein the read request carries the location identifier of the first location of the flash memory and is used for requesting to read the data stored in the first location. The computing device receives a reading request sent by the terminal, and reads data stored in a first position corresponding to a position identifier of the first position in the flash memory according to the position identifier of the first position carried in the reading request.

And the computing equipment reads the data stored in the first position according to the position identification of the first position carried in the reading request. When the error Bit number of the data at the first position is not greater than the first threshold, error correction can be directly performed through hardware of the flash memory, so that the data stored at the first position is obtained. But when the error Bit number of the data at the first position is larger than the first threshold value and the hardware error correction capability in the flash memory is exceeded, the data error occurs, and the flash memory sends an error indication of the read error to the computing device.

It should be noted that one Die includes multiple blocks, one Block includes multiple pages, one Page includes multiple Bit numbers, and data is written in the Page in the form of Bit numbers. When reading data at the first location is erroneous, multiple Bit numbers may be erroneous, typically in units of mKB. The computing device determines the Page where mKB bits are located in mKB units, determines the Block where the Page is located according to the Page, determines the Die where the Block is located according to the Block, that is, determines the storage address corresponding to mKB bits, and encapsulates the storage address corresponding to mKB bits to obtain error information. And the data of the first position comprises data on at least one Die, and when the data of the first position is read to be wrong, a plurality of corresponding error messages are provided. For each error message, the computing device may correct the error by using the flash memory error correction method provided in the embodiments of the present application. In the embodiment of the present application, the essence of error correction of the error information is to re-read data corresponding to the memory address from the flash memory, based on the memory address corresponding to the Bit number of mKB in the error information.

m is a positive integer, and can be set and changed as needed, and this is not particularly limited in the embodiments of the present application. For example, m is 4.

Step 302: when an error indication returned by the flash memory is received, the computing device adds a plurality of error messages of the read request to the plurality of first error correction linked lists.

When the computing device receives an error indication returned by the flash memory, a plurality of error messages of the read request are added into a plurality of first error correction linked lists, and at least one error message is added into one first error correction linked list.

In one possible implementation, the present step can be implemented by the following steps (1) to (2), including:

(1) the computing device determines the Die in which each error message is located.

The plurality of error messages may correspond to different Die, the computing device determines a Page where the Bit number of mKB is located according to a storage address corresponding to the Bit number of mKB in the error messages, determines a Block where the Page is located according to the Page where the Bit number of mKB is located, and determines the Die where the Block is located according to the Block.

(2) And for each error message, the computing equipment adds the error message to the error correction linked list corresponding to the Die according to the Die where the error message is located.

The flash memory comprises a plurality of Dies, and for each error message, the computing device can add the error message to the error correction linked list corresponding to the Die in which the error message is positioned according to the sequence of the data corresponding to the error message when the error occurs. When the Dies where a plurality of error messages are located are the same Die, the computing equipment adds the plurality of error messages to the error correction linked list corresponding to the same Die according to the sequence of the data corresponding to the error messages when errors occur. And when the subsequent computing equipment corrects the error, correcting the error according to the sequence of the error information, and correcting the error information added into the error correction linked list. In addition, the computing equipment divides the error correction linked list according to the Die where the error information is located, namely, the error information is divided according to the storage address, and the subsequent error correction of the error information on different dies is not interfered with each other, so that the improvement of the error correction efficiency is facilitated.

For example, flash memory includes 3 Dies, Die0, Die1, and Die 2. For each error message, the computing device determines that the Die in which the error message is located is Die0, Die1, or Die2, for example, if the computing device determines that the Die in which the error message is located is Die0, the computing device adds the error message to the error correction linked list corresponding to Die 0.

In one possible implementation manner, the number of the plurality of first error correction linked lists may be the same as or different from the number of Die in the flash memory. When the number of the first error correction linked lists is the same as the number of the Die, for example, the flash memory includes 3 Die, the number of the first error correction linked lists is 3, and each Die corresponds to one first error correction linked list. When the number of the first error correction linked lists is different from the number of the Die, the number of the first error correction linked lists may be set and changed as needed, for example, the number of the first error correction linked lists is 2 or 4.

Step 303: and the computing equipment corrects the error information of the first error correction linked list, and corrects the error information in other first error correction linked lists in parallel in the error correction process.

And for each first error correction linked list in the plurality of first error correction linked lists, the head of each first error correction linked list exists, and the computing equipment adds the first error information in each first error correction linked list to the head of the first error correction linked list to obtain the error information in the head of each first error correction linked list. The error information in the headers of different first error correction linked lists is different. When the error information in the head of the first error correction linked list is corrected by the computing equipment, error information in the heads of other first error correction linked lists is corrected in parallel. When the error correction of the error information in the header of the first error correction linked list is finished, the error information is deleted from the header by the computing equipment, the second error information is added into the header, and the error correction is carried out on the error information newly added into the header. In the process, after the error correction of the error information in the headers of the other first error correction linked lists is finished, the error information in the headers of the other first error correction linked lists can be simultaneously deleted from the corresponding headers, the second error information of each first error correction linked list in the other first error correction linked lists is added into the corresponding header, and the error information newly added into the headers of the other first error correction linked lists is subjected to error correction in parallel.

In one possible implementation, the computing device may perform error correction on the error information in the header of the first error correction linked list by using a specified sequence of error correction methods. When the computing device corrects the error information in the header of the first error correction linked list through the designated error correction method sequence, the computing device can also correct the error information in the headers of other first error correction linked lists. In another possible implementation manner, the computing device may further perform error correction on the plurality of first error correction linked lists in parallel through a plurality of designated error correction method sequences. For example, when the computing device corrects the error information in the header of the first error correction linked list through the first designated error correction method sequence, the computing device may also correct the error information in the headers of other first error correction linked lists through other designated error correction method sequences.

For example, the computing device adds a plurality of error messages of the read request to the 4 first error correction linked lists, and then the computing device can simultaneously correct the error messages in the headers of the 4 first error correction linked lists by using a specified error correction method sequence; or, the computing device corrects error information in the headers of the 4 first error correction linked lists simultaneously through 4 designated error correction method sequences, wherein one designated error correction method sequence corresponds to one first error correction linked list. The specified error correction method sequence may be set and changed as needed, for example, the specified error correction method sequence may be: a Calibration error correction method, a RAID error correction method, a Read Retry error correction method, and an SLDPC error correction method; or a RAID error correction method; or an SLDPC error correction method-Calibration error correction method. In the embodiments of the present application, this is not particularly limited.

In another possible implementation manner, when the computing device corrects the error information in the headers of the first error correction linked lists by using the error correction method sequence, the error type of the error information in the header of each first error correction linked list may be determined first, and the first error correction method sequence corresponding to the error type of the error information in the header of each first error correction linked list is determined according to the error type of the error information in the header of each first error correction linked list and the plurality of error correction methods. Error information of different error types is corrected through different error correction method sequences, so that the error information is corrected in a targeted manner, the error correction time is shortened, and the error correction efficiency is improved. When the error information in the headers of the plurality of first error correction linked lists has the error information in the headers with the same error type, the error information in the headers with the same error type can be corrected by a first error correction method in the first error correction method sequence, and when the error information in the headers with failed error correction exists, the error correction is performed by a second error correction method in the first error correction method sequence until the error correction is finished by a last error correction method in the first error correction method sequence.

For example, when the number of the first Error correction linked lists is 4, and the Error types of the Error information in the header of the first Error correction linked list are the same as the Error types of the Error information in the header of the second first Error correction linked list and are both Read uncc Error types, the computing device corrects the Error information in the headers of the two first Error correction linked lists in parallel by using the first Error correction method in the first Error correction method sequence; and if the error types of the error information in the header of the third first error correction linked list are the same as the error types of the error information in the header of the fourth first error correction linked list, performing error correction on the error information in the header of the third first error correction linked list and the error information in the header of the fourth first error correction linked list in parallel according to error correction method sequences corresponding to the other error types.

In the embodiment of the present application, a computing device is taken as an example to correct error information in a header of a first error correction linked list. Accordingly, this step can be realized by the following steps (1) to (4), including:

(1) the computing device determines a first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list.

For a first error correction linked list, the computing device determines error information in a header of the first error correction linked list, and determines a first error correction method sequence of the error information in the header according to the error information in the header.

This step may be realized by the following steps (a1) to (a2), including:

(A1) the computing device determines an error type of the error information in the header of the first error correction linked list.

In one possible implementation, the step of the computing device determining the error type of the error information in the header may be: and the computing equipment determines the error type of the error information in the header according to the error type identifier carrying the current error information in the error indication. In another possible implementation, the step of the computing device determining the error type of the error information in the header may be: the flash memory directly feeds back the error type to the computing equipment, and the computing equipment receives the error type of the error information in the header sent by the flash memory.

In the embodiment of the present application, the types of errors mainly include the following types: media CRC Error (Media Cyclic Redundancy Check Error) Error type, Read uncc Error (Read Uncorrectable Error) Error type, Read Empty Page Error type, and Read ECC Over (Read Error Checking and Correction Over, Read Error Check and Correction Over, end) Error type.

(A2) The computing equipment determines a first error correction method sequence corresponding to the error type according to the error type and the error correction methods.

In this step, the computing device may determine, directly according to the error type and the plurality of error correction methods, a first error correction method sequence corresponding to the error type of the error information in the header. Or acquiring the error number of the error information in the error Block before determining the first error correction method sequence according to the error type and a plurality of error correction methods. Accordingly, this step can be realized by the following steps (A2-1) to (A2-3), including:

(A2-1) the computing device obtains the first error number of the error information in the error Block when the flash memory generates the data error last time.

And when the data error occurs every time, the computing equipment stores the error number of the error information in the error Block when the data error occurs. In the step, when a data error occurs at present, the computing device obtains a first error number of the error information in the error Block when the data error occurs at the last time from the stored error number of the error information in the error Block.

(A2-2) the computing device obtains a second error number of the error information in the error Block when the data error currently occurs.

In the step, when the data error occurs at present, the computing device obtains a second error number of the error information in the error Block with the current data error.

(a2-3) the computing device determines a first error correction method sequence based on the first number of errors, the second number of errors, the type of error, and the plurality of error correction methods.

In one possible implementation manner, when the second error number is not greater than the first error number, the computing device selects a first error correction method sequence corresponding to the error type from a plurality of error correction method sequences based on the error type and the corresponding relationship between the error type and the error correction method sequence, wherein the first error correction method sequence comprises at least one error correction method.

In this implementation, a plurality of first error correction method sequences may be stored in advance in the computing device.

In the embodiment of the present application, the error correction method may be set and changed as needed, for example, the error correction method may be a Read Retry error correction method and a Calibration error correction method. In the embodiment of the present application, the error correction method is not particularly limited. When the Error type is Read un ecc Error type, the obtained first Error correction method sequence may be Read Retry Error correction method-Calibration Error correction method.

In the step, the computing equipment dynamically schedules the error correction method according to the first error number, the second error number, the error type and the plurality of error correction methods, so that the error correction delay is reduced, and the error correction efficiency is improved.

In one possible implementation manner, the computing device selects at least one error correction method from the plurality of error correction methods based on the error type and the corresponding relationship between the error type and the error correction method, and combines the selected at least one error correction method into a first error correction method sequence.

In this implementation, the computing device may store a plurality of error correction methods and correspondence of error types and error correction methods in advance. In the correspondence, one error type may correspond to a plurality of error correction methods, and when one error type corresponds to a plurality of error correction methods, the computing device may select at least one error correction method from the plurality of error correction methods. When the Error type is a Read uncc Error type, the corresponding Error correction method may include a Read Retry Error correction method and a Calibration Error correction method.

The computing device sequentially composes the selected at least one error correction method into a first sequence of error correction methods. For example, when the Error type is a Read uncc Error type and the selected Error correction method is a Read Retry Error correction method and a Calibration Error correction method, the first Error correction method sequence may be a Read Retry Error correction method-Calibration Error correction method.

In the embodiment of the application, the computing device may determine an error correction method sequence according to the error type and a plurality of error correction methods; or the computing device can also determine the error correction method sequence according to the error number, the error type and a plurality of error correction methods. In the embodiments of the present application, this is not particularly limited. When the computing equipment determines the error correction method sequence according to the error number, the error type and the error correction methods, when the magnitude relation between the second error number and the first error number is different, the determined error correction method sequence is different even if the same error type is adopted, and the method can avoid the waste of error correction resources caused by the fact that the determined error correction method sequence comprises useless error correction methods. For example, in this step, when the Error type is Read un ecc Error type, and the second Error number is not greater than the first Error number, the determined Error correction method sequence is Read Retry Error correction method-Calibration Error correction method-slppc Error correction method-RAID Error correction method. And when the second error number is larger than the first error number, the determined error correction method sequence is an SLDPC error correction method-RAID error correction method. This is because when the second error number is greater than the first error number, it may be that Data recovery has a problem, and in this case, the probability of error correction success using the Read Retry error correction method and the Calibration error correction method is low, so that the SLDPC error correction method and the RAID error correction method are directly used, which can reduce error correction delay to a great extent, shorten error correction time, and improve error correction efficiency.

It should be noted that, in the step (a2-3), when the second Error number is greater than the first Error number and the Error type is a Read uncc Error type, the computing device may determine the Error correction method sequence to be the second Error correction method sequence based on the Error type and the corresponding relationship between the Error type and the Error correction method sequence. The second error correction method sequence is elaborated in step (4).

(2) And the computing equipment corrects the error information in the header by the first error correction method sequence.

In one possible implementation, the first sequence of error correction methods includes a Read Retry error correction method. The step of the computing device correcting the error information in the header by the Read Retry error correction method may be implemented by the following steps (B1) to (B2), including:

(B1) the computing device selects a first offset voltage value from the first Retry table, and corrects error information in the header of the table based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value.

The first Retry table is a fast Retry table in the Read Retry error correction method, and a first offset voltage value stored in the first Retry table is a corresponding offset voltage value when the error is successfully corrected in a history time period closest to the current time. A plurality of first offset voltage values may be stored in the first retry table, and the computing device may update the first retry table in real-time or periodically. The computing device also stores a time interval between a time when each of the first offset voltage values was successfully corrected and a time when the error information in the header was erroneous. The process by which the computing device selects the first offset voltage value from the first retry table may be: the computing device selects a first offset voltage value corresponding to the shortest time interval from the plurality of first offset voltage values according to the time interval. In a possible implementation manner, the computing device sorts the plurality of first offset voltage values according to the time interval, where a first offset voltage value corresponding to the shortest time interval is a first offset voltage value in the first retry table, a first offset voltage value corresponding to the second shortest time interval is a second offset voltage value in the first retry table, and the first offset voltage values corresponding to the longest time interval are sequentially arranged, and are last offset voltage values in the first retry table. The computing device sequentially selects the first offset voltage values in the first retry table. In another possible implementation, the computing device may also randomly select an offset first voltage value from the first retry table.

The number of the first offset voltage values in the first retry table may be set and changed as needed, for example, the number of the first offset voltage values may be 3, 4, or 5, etc. In the embodiments of the present application, this is not particularly limited. When the number of the first offset voltage values is 3, the 3 first offset voltage values may be the first offset voltage value with the shortest time interval, the first offset voltage value with the second shortest time interval, and the first offset voltage value with the longest time interval, respectively, see table 1. The calculation device may select a first offset voltage value having the shortest time interval from the 3 first offset voltage values, and correct error information in the header based on the first offset voltage value having the shortest time interval. The reference voltage value may be set and changed as needed, and is not particularly limited in the embodiment of the present application. For example, the reference voltage value may be 0.

The computing device selects a first offset voltage value from the first retry table, and corrects error information in the header according to the selected first offset voltage value. The computing equipment determines a first offset voltage value adopted for error correction in an Executing State, reads data corresponding to error information in a header through the first offset voltage value, switches the State from the Executing State to a Single State Done State after reading the data, and determines whether the data reading is successful or not in the Single State Done State. If the reading is successful, the first offset voltage value is saved, and the State is switched from the Single State Done State to the Done State through the Executing State; and if the reading fails, reselecting the first offset voltage value from the first retry table in the Executing state, and correcting the error according to the reselected first offset voltage value. Switching between states when the computing device corrects errors by the Read Retry error correction method can be seen in fig. 4.

In a possible implementation manner, before step (2-1), the computing device may determine whether error correction is currently performed by the Read Retry error correction method, and when error correction is not currently performed by the Read Retry error correction method, the computing device adds error information in a header to a linked list of the Read Retry error correction method, switches a state from an idle state to an Executing state, and executes step (2-1).

TABLE 1

(B2) When the error information in the header cannot be corrected successfully by the computing device through the reference voltage value and each first offset voltage value in the first retry table, the computing device selects a second offset voltage value from the second retry table, and corrects the error information in the header through the reference voltage value and the selected second offset voltage value.

When the error information in the header cannot be corrected successfully by the computing device according to the reference voltage value and each first offset voltage value in the first retry table, the computing device selects a second offset voltage value from the second retry table for error correction.

The second retry table is a table generated by counting error information before the calculation device and storing offset voltage values when data are successfully read before. The step of the computing device selecting the second offset voltage value from the second retry table and the step of selecting the first offset voltage value in the step (B1) described above may be the same or different. In the embodiments of the present application, this is not particularly limited. The computing device corrects error information in the header based on the selected second offset voltage value.

In this step, when the computing device reads data according to the second offset voltage value, the switching between the states is similar to the switching process between the states when the computing device reads data by using the first offset voltage value, and reference may be continued to fig. 4, which is not described herein again. When the computing device fails to correct errors according to the selected second offset voltage values, one second offset voltage value is reselected from the second retry table, and data is read through the reselected second offset voltage value. If the reading is successful, the computing device updates the second offset voltage value into the first retry table, and takes the second offset voltage value as a first offset voltage value in the first retry table; if the read fails, the computing device reselects the second offset voltage value to read the data.

When the computing device fails to correct the error based on each of the second offset voltage values or the number of reads reaches a second threshold, the computing device determines that the error correction failed.

The second threshold may be set and changed as needed, and in the embodiment of the present application, the second threshold is not particularly limited. For example, the second threshold may be 127 times, 128 times, or 130 times. And, the second threshold value may be equal to or less than the number of the second offset voltage values in the second retry table. In the embodiments of the present application, this is not particularly limited. For example, the second threshold may be equal to the number of second offset voltage values in the second retry table, which are 128 times each. In addition, when the computing device selects the second offset voltage value from the second retry table, the computing device may sequentially select the second offset voltage values, or may randomly select the second offset voltage values, which is not specifically limited in this embodiment of the application.

In the embodiment of the application, when the error correction is performed by the Read Retry error correction method, the offset voltage values in the first Retry table are preferentially adopted, and a plurality of offset voltage values corresponding to successful error correction in a historical time period nearest to the current time are stored in the first Retry table.

In another possible implementation manner, when the computing device fails to correct errors through the Read Retry error correction method, the operation may be directly ended; or error correction by other error correction methods. When the computing device performs error correction through other error correction methods, the first error correction method sequence further includes a Calibration error correction method. Correspondingly, when the error correction by the Read Retry error correction method fails, the error information in the header is added to the linked list in the Calibration error correction method, and the step of the computing device performing error correction on the error information in the header by the Calibration error correction method can be realized by the following steps (C1) to (C3), including:

(C1) the computing device determines a voltage adjustment range of the error information in the header based on the reference voltage value of the Calibration error correction method and the first offset interval.

The first offset interval is a magnitude of a left-bias adjustment or a right-bias adjustment of the reference voltage value based on the reference voltage value. For example, on the basis of the reference voltage value, left-offset by a first offset interval; or right-shifted by a first shift interval based on the reference voltage value.

This step can be achieved by the following steps (C1-1) to (C1-4), including:

(C1-1) the computing equipment reads data from the flash memory based on the reference voltage value of the Calibration error correction method, and according to the difference value between the number of 1 s or the number of 0 s in the read data and the third threshold, the reference voltage value is adjusted to the left by the first offset interval or adjusted to the right by the first offset interval, so that a fourth voltage value is obtained.

In this step, the computing device reads data by using a reference voltage value in an Executing State, after the data is read, the computing device switches the State from the Executing State to a Single State Done State, determines a difference value between the number of 1 s or the number of 0 s in the read data and a third threshold value in the Single State Done State, and adjusts the reference voltage value by a left offset interval or a right offset interval according to the difference value to obtain a fourth voltage value. For example, in the embodiment of the present application, the computing device determines whether to adjust the reference voltage value to the left or to the right according to the difference between the number of 1 s and the third threshold.

When the number of the 1 s is larger than the third threshold value, the computing equipment adjusts the reference voltage value to the left by a first offset interval to obtain a fourth voltage value; and when the number of the 1 s is smaller than the third threshold value, the computing equipment adjusts the reference voltage value to right offset by the first offset interval to obtain a fourth voltage value.

The first offset interval may be set and modified as needed, and in the embodiment of the present application, the first offset interval is not particularly limited. For example, the first offset interval may be 10mV, 16mV, 20 mV.

It should be noted that, when no data error occurs in the flash memory, and the number of 1 s and the number of 0 s in the data are equal, the third threshold is the number corresponding to the case where the number of 1 s and the number of 0 s are equal. For example, when no data error occurs, the number of 1 s and the number of 0 s in the data are equal to 5000, that is, the third threshold is 5000. After data errors occur, the number of 1 in the read data is 5200, and is greater than a third threshold, at this time, the reference voltage value needs to be subjected to left offset adjustment, so that the number of 1 is as close to the third threshold as possible; when the number of 1 in the read data is 4800, which is smaller than the third threshold, it is necessary to perform right bias adjustment on the reference voltage value, so that the number of 1 is as close as possible to the third threshold.

(C1-2) the computing device reads data based on the fourth voltage value, and adjusts the fourth voltage value by the first offset interval for left offset or the first offset interval for right offset according to a difference between the number of 1 s or the number of 0 s in the read data and the third threshold, to obtain a fifth voltage value.

In step (C1-1), the computing device determines a fourth voltage value in the Single State Done State, and then switches the State from the Single State Done State to an Executing State in which data is read using the fourth voltage value. After reading the data, the computing device switches the State from the Executing State to the Single State Done State, determines the difference between the number of 1 s or the number of 0 s in the read data and the third threshold value in the Single State Done State, and adjusts the fourth voltage value by left-hand deviation or right-hand deviation for the first offset interval to obtain a fifth voltage value.

For example, in the step (C1-1), the number of 1 s is greater than the third threshold, and the device left offset adjusts the reference voltage value to obtain a fourth voltage value; and when the calculating equipment still reads the number of 1 s in the data again according to the fourth voltage value, the calculating equipment adjusts the fourth voltage value to the left by the first offset interval to obtain a fifth voltage value.

(C1-3) the computing device reads the data based on the fifth voltage value until a difference between the number of 1 s or the number of 0 s in the currently read data and the third threshold is greater than a difference between the number of 1 s or the number of 0 s in the last read data and the third threshold, and determines the voltage value of the currently read data and the voltage value of the last read data.

After determining a fifth voltage value in a Single State Done State, the computing device switches the State from the Single State Done State to an Executing State, reads data by using the fifth voltage value in the Executing State, switches the State from the Executing State to the Single State Done State, determines a difference value between the number of 1 s or the number of 0 s in the read data and a third threshold in the Single State Done State, repeats the above steps until the difference value is larger than the difference value between the number of 1 s or the number of 0 s in the last read data and the third threshold, and determines the voltage value of the current read data and the voltage value of the last read data. When the computing device corrects errors through the Calibration error correction method, switching between states can be seen in fig. 5.

For example, when a data error occurs in the flash memory, after the computing device reads data by using the reference voltage value, the number of 1 in the data is 5200, the third threshold is 5000, the number of 1 is greater than the third threshold, and the difference is 200. The computing equipment adjusts the left offset of the reference voltage value by the first offset interval of 16mV to obtain a fourth voltage value, after data are read through the fourth voltage value, the number of 1 is 5050, the number of third threshold values is 5000, the number of 1 is still larger than the third threshold values, and the difference value is 50; and the calculating device adjusts the left offset of the fourth voltage value by the first offset interval of 16mV to obtain a fifth voltage value, after the data is read through the fifth voltage value, the number of 1 s is 5100, the difference value is 100, and if the difference value is greater than the last difference value, the calculating device determines the fifth voltage value of the currently read data and the fourth voltage value of the last read data.

(C1-4) the computing device determines a voltage adjustment range according to the voltage value of the current read data and the voltage value of the last read data.

The computing device combines the voltage value of the currently read data and the voltage value of the last read data into the voltage adjustment range.

The reference voltage value of the Calibration error correction method and the reference voltage value of the Read Retry error correction method may be the same or different, and in the embodiment of the present application, this is not specifically limited, for example, the reference voltage value of the Calibration error correction method and the reference voltage value of the Read Retry error correction method are the same, and may both be 0.

In a possible implementation manner, before Executing step (C1), the computing device may determine whether error correction is currently performed by the Calibration error correction method, and when error correction is not currently performed by the Calibration error correction method, the computing device adds error information in the header to a linked list of the Calibration error correction method, switches the state from the idle state to an Executing state in the Calibration error correction method, and executes step (C1), where the computing device determines the first offset interval in the Executing state.

(C2) The computing device determines a third voltage value from the voltage adjustment range.

When determining the third voltage value, the computing device may first select a voltage value from the voltage adjustment range as a basic voltage value, and perform fine adjustment on the basic voltage value to obtain the third voltage value. And the value of the third voltage value is within the voltage regulation range.

For example, the computing device may select the middle value of the voltage adjustment range as the base voltage value, or may trisect the voltage adjustment range and select a voltage value near the current read data voltage value as the base voltage value. In the embodiments of the present application, this is not particularly limited.

The step of the computing device performing fine adjustment on the basic voltage value to obtain a third voltage value may be: the computing device may adjust the second offset interval for left bias or the second offset interval for right bias, centered on the base voltage value, to obtain a third voltage value. The second offset interval is smaller than the first offset interval. For example, the first offset interval may be 16mV and the second offset interval may be any interval less than 16mV, e.g., the second offset interval is 1mV, 2mV, 3mV, etc. In the embodiments of the present application, this is not particularly limited.

The basic voltage value can be adjusted for multiple times by the computing equipment, and a corresponding voltage value is obtained every time of adjustment. The computing device reads data in the Executing State through the voltage value, determines the difference value between the number of 1 s or the number of 0 s in the read data and a third threshold value in the Single State Done State, repeatedly adjusts the voltage value and reads the data until the number of 1 s or the number of 0 s is equal to the third threshold value, and takes the corresponding voltage value as the third voltage value. For example, if the voltage value of the currently read data is the fourth voltage value and the voltage value of the last read data is the fifth voltage value, the value of the third voltage value is between the fourth voltage value and the fifth voltage value. If the number of 1's or the number of 0's cannot be made equal to the third threshold value by each voltage value within the voltage adjustment range, the voltage value corresponding to the case where the difference between the number of 1's or the number of 0's and the third threshold value is the smallest is determined, and this voltage value is taken as the third voltage value.

The process of adjusting the basic voltage value by the computing device for the second offset interval for the left offset or the second offset interval for the right offset is similar to the process of determining the voltage adjustment range by the computing device based on the reference voltage value and the first offset interval in step (C1), and details are not repeated here.

It should be noted that, in the step (C1), the computing device first roughly adjusts the reference voltage value to obtain a voltage adjustment range, and selects the third voltage value in the voltage adjustment range, so that purposeful selection and adjustment of the voltage value are realized, and the error correction efficiency is improved.

(C3) And the computing equipment corrects the error information in the header according to the third voltage value.

And after determining the third voltage value in the Single State Done State, the computing device switches the State from the Single State Done State to the Executing State, reads data by adopting the third voltage value in the Executing State, switches the State from the Executing State to the Single State Done State, and determines whether all data corresponding to the error information in the header are read in the Single State Done State. If all the data corresponding to the error information in the header are read, the State is switched from the Single State Done State to the Current Page Done State through Executing, and then to the Done State, and whether the error correction is successful or not is determined in the Done State. If the data corresponding to the error information in the header is successfully read, determining that the error correction is successful; and if the data corresponding to the error information in the header is not successfully read, determining that error correction fails, initializing a Calibration error correction method by the computing equipment, and switching the state from the Done state to the idle state for correcting the next error information. Switching between states may continue with reference to fig. 5 when the computing device corrects errors via the Calibration error correction method.

In the embodiment of the application, when the error is corrected by the Calibration error correction method, an error correction voltage regulation range is determined first, and the voltage regulation range is regulated, so that blind regulation can be avoided, purposeful regulation in an effective range can be realized, the error correction time can be shortened, and the error correction efficiency can be improved.

In this embodiment of the application, when the error correction is successful or the error correction is finished by the last error correction method in the first error correction method sequence, the computing device deletes the error information in the header, adds the next error information after the header in the first error correction linked list to the header, and then determines the first error correction method sequence of the error information newly added to the header according to the error information newly added to the header until the error correction is finished on the last error information in the first error correction linked list. When the error correction is carried out by the computing equipment, when the error correction of the error information in the header is successful or finished through the error correction method sequence, the error information in the header is deleted, and the next error information is added into the header, so that the error information which is successful or finished in error correction is prevented from occupying resources in the header, and the dynamic update of the error correction linked list is realized.

It should be noted that, when the computing device fails to correct the error information of the first error correction linked list by the first error correction method sequence, the operation may be directly ended. Or, the error information of the error correction failure in the first error correction linked list can be corrected by the second error correction method sequence. In the embodiments of the present application, this is not particularly limited. And (3) when the computing device corrects a plurality of error messages which fail to correct errors in the first error correction linked list through the second error correction method sequence, the computing device executes the steps (3) and (4).

(3) The computing device adds a plurality of error messages that failed to be error corrected by the first error correction method sequence to the second error correction linked list.

In this step, the computing device may add the error information with the failure in error correction of the first error correction method sequence to the second error correction linked list according to the order of the Bit number error of mKB in the error information.

(4) And the computing equipment corrects the error information in the second error correction linked list one by one through a second error correction method sequence.

The second error correction method sequence comprises an SLDPC error correction method and a RAID error correction method. The step of the computing device performing the one-by-one error correction on the error information in the second error correction linked list through the second error correction method sequence may be implemented by the following steps (D1) to (D2), including:

(D1) and when the error is not corrected by the SLDPC error correction method and the RAID error correction method at the current first time, the computing equipment corrects the error information in the second error correction linked list one by the SLDPC error correction method.

In this step, the computing device adds the first error information in the second error correction linked list to the linked list of the SLDPC error correction method, and switches the State from the idle State to the first SLDPC State Manual SD (SLDPC State Manual Soft Decode, Manual Soft Decode of software low density check code) State. In the first slpc State Manual SD State, the computing device acquires a third offset interval from an LLR (Log Likelihood Ratio) table of the slpc error correction method, then switches the State from the first slpc State Manual SD State to a second slpc State Manual SD State, and in the second slpc State Manual SD State, reads data based on the reference voltage value and the third offset interval. And in the second SLDPC State Manual SD State, after a fourth offset interval is acquired from the LLR table, switching the State from the second SLDPC State Manual SD State to a third SLDPC State Manual SD State, and in the second SLDPC State Manual SD State, reading data based on the reference voltage value and the fourth offset interval. And in the third SLDPC State Manual SD State, after the next offset interval is acquired from the LLR table, switching the State from the third SLDPC State Manual SD State to the next SLDPC State Manual SD State, and repeating the steps until the State is switched to the fifth SLDPC State Manual SD State. In the fifth SLDPC State Manual SD State, a reference voltage value and an offset interval used when reading data are determined, the State is switched from the fifth SLDPC State Manual SD State to an SD State Done (Soft Decode State Done) State, and data are read in the SD State Done State. Due to the limitation of hardware resources, when the SLDPC error correction method corrects errors, only one CW (Codeword) can be corrected at a time, one CW is generally 2KB, and the error correction is generally in units of 4KB, so that the computing device determines whether the processing of 4KB of data is completed in the SD State Done State, and when the processing is completed, the computing device switches the State from the SD State Done State to the Done State. When the non-processing is completed, the computing device switches the State from the SD State Done State to the first SLDPC State Manual SD State, and continues to perform error correction. When the computing device corrects errors through the SLDPC error correction method, switching between states can be seen in fig. 6.

Wherein, after the computing device switches State from the SD State Done State to the Done State, it is determined whether data is successfully read. When the data is successfully read, it is determined that the error correction is successful and the computing device ends the operation. And when the data is not successfully read, determining that error correction fails, initializing the SLDPC error correction method by the computing equipment, and switching the state from the Done state to the idle state for correcting the next error message. When the computing device corrects errors through the SLDPC error correction method, switching between states can be seen in fig. 6.

It should be noted that, in the embodiment of the present application, when the computing device corrects errors by using the SLDPC error correction method, the error correction is performed in a serial or single-path manner, that is, only one error message can be corrected at a time, and the error message that is first added to the linked list of the SLDPC error correction method is preferentially processed.

It should be noted that, in the SLDPC error correction method and the RAID error correction method, only one error correction method can perform error correction at the same time. When the error correction is carried out by one error correction method, the error correction is not carried out by the other error correction method, so that the situation that the two error correction methods occupy excessive resources when carrying out error correction simultaneously can be avoided, and the error correction efficiency is improved.

(D2) And for the error information which fails to be corrected by the SLDPC error correction method at present, when the error information is not corrected by the SLDPC error correction method and the RAID error correction method at the present second time, the computing equipment corrects the error information which fails to be corrected by the SLDPC error correction method by the RAID error correction method.

In this step, the computing device adds the error information which fails to be corrected by the SLDPC error correction method to a linked list of the RAID error correction method according to the order of the Bit number error of mKB in each error information, and switches the state from the idle state to the Executing state. After entering the Executing State, the computing device determines the Die where the first error information in the linked list of the RAID error correction method is located, then reads the data on the Dies without errors, and when the data on the Dies without errors are successfully read, the State is switched from the Executing State to the Decode State Done State in the RAID error correction method, and then the State is switched to the Done State, the RAID error correction method is initialized, and the State is switched to the idle State for processing the next error information in the linked list of the RAID error correction method. Switching between states when a computing device corrects errors by a RAID error correction method can be seen in fig. 7.

And when the computing equipment fails to Read the data on the non-Error Die and the Error type is a Read UNECC Error type, starting a Read Retry Error correction method. And correcting errors through a Read Retry error correction method, switching the State from a Decode State Done State to an Executing State when the Read Retry error correction method succeeds in correcting errors, reading data on the next non-error Die in the Executing State, and switching the State from the Executing State to a Decode State Done State in a RAID error correction method by the computing equipment when the data on the next non-error Die is successfully Read. Switching between states while the computing device is error corrected by RAID error correction methods may continue with reference to fig. 7.

If the Read Retry error correction method fails, the state is switched to the Calibration error correction method. After entering the Calibration error correction method, the State is switched from the Calibration error correction method to the Decode State Done State regardless of whether the error correction is successful or not.

When the data on the non-faulty Die is completely read or cannot be read, the computing device switches the State from the Decode State Done State to the Done State. After the Done state is entered, no matter whether the data on the unerring Die is successfully read or not, the error correction is finished, the RAID error correction method is initialized, and the state is switched from the Done state to the idle state.

It should be noted that, in this step, when the computing device fails to Read data on the unerried Die, but the Error type is a Read uncc Error type, the computing device starts a Read Retry Error correction method and a Calibration Error correction method to correct errors, and belongs to a RAID Error correction method. The process of the computing device correcting the first error information by RAID error correction method can be seen in fig. 8. The Error type in fig. 8 is a Media CRC Error type or a Read Empty Page Error type, and the Die N in fig. 8 indicates that the RAID Error correction method fails to Read data on the non-Error Die, but the Error type is a Read un ecc Error type, and the Die is processed separately.

In addition, the non-error Die refers to the rest non-error Die in the flash memory except the Die where the first error message is located, and the computing device can obtain the data on the error Die by reading the data on the non-error Die and then performing exclusive or operation, thereby realizing the error correction of the first error message. When the error is corrected by the RAID error correction method, the error correction is carried out in a serial and single-path mode, namely, only one error message can be corrected at one time, and the task of data error added to the linked list firstly is processed preferentially. The number of the unmistakable Die may be one or more, and in the embodiment of the present application, this is not particularly limited. When the computing device successfully corrects the first error message by the RAID error correction method, the computing device may correct the next error message.

When the second Error number is not greater than the first Error number and the Error type is a Read un ecc Error type, the process of the computing device correcting the Error information through the first method sequence and the second method sequence may be as shown in fig. 9. In fig. 9, in the Error correction process of the RAID Error correction method, the RAID Error correction method reads data on the unerried Die, and when the RAID Error correction method fails to Read the data on the unerried Die, but the Error type is a Read uncc Error type, the computing device starts a Read Retry Error correction method and a Calibration Error correction method to perform Error correction. Die N in fig. 9 represents a Die on which the RAID Error correction method fails to Read data on the uncorrupted Die, but the Error type is Read un ecc Error type, which is handled separately. When the second Error number is greater than the first Error number and the Error type is a Read uncc Error type, a process of the computing device correcting the Error information through the second Error correction method sequence may be as shown in fig. 10. In fig. 10, in the Error correction process of the RAID Error correction method, the RAID Error correction method reads data on the unerried Die, and when the RAID Error correction method fails to Read the data on the unerried Die, but the Error type is a Read uncc Error type, the computing device starts a Read Retry Error correction method and a Calibration Error correction method to perform Error correction. Die N in fig. 10 represents a Die on which the RAID Error correction method fails to Read data on the uncorrupted Die, but the Error type is a Read un ecc Error type, which is handled separately.

In the embodiment of the application, for the error information which is failed to correct the error through the first error correction method sequence, the computing device can also continuously correct the error through the second error correction method sequence, so that the success rate of error correction is improved.

Step 304: when the computing device successfully corrects each error message in each first error correction linked list, the computing device outputs the data stored at the first position.

When the computing device successfully corrects each error message in each first error correction linked list, the computing device successfully reads the data stored at the first position, and the computing device can directly output the data stored at the first position.

The embodiment of the application provides a flash memory error correction method, wherein a computing device receives a read request, the read request carries a position identifier of a first position of a flash memory and is used for reading data stored in the first position, when an error indication returned by the flash memory is received, a plurality of error messages of the read request are added into a plurality of first error correction linked lists, and error correction is performed in parallel according to the error messages in the plurality of first error correction linked lists. According to the method, the error information in the first error correction linked lists is corrected in parallel by adding the error information into the first error correction linked lists, so that the error correction time is shortened, and the error correction efficiency is improved.

An embodiment of the present application provides a flash memory error correction apparatus, which is applied to a computing device, and with reference to fig. 11, the apparatus includes:

a receiving module 1101, configured to receive a read request, where the read request carries a location identifier of a first location of a flash memory, and is used to request to read data stored in the first location;

an adding module 1102, configured to add multiple pieces of error information of the read request to multiple first error correction linked lists when receiving an error indication returned by the flash memory;

and the error correction module 1103 is configured to perform error correction in parallel according to the error information in the multiple first error correction linked lists.

In a possible implementation manner, a module 1102 is added, which is further configured to determine a Die where each error message is located; and for each error message, adding the error message into an error correction linked list corresponding to the Die according to the Die in which the error message is positioned.

In another possible implementation manner, the error correction module 1103 is further configured to correct error information of the first error correction linked list; and in the error correction process, error information in other first error correction linked lists in the plurality of first error correction linked lists is corrected in parallel.

In another possible implementation manner, the error correction module 1103 is further configured to determine a first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list, where the first error correction method sequence includes at least one error correction method; error information in the header is corrected through a first error correction method sequence; when the error correction of the error information in the header is successful or the error correction is finished through the last error correction method in the first error correction method sequence, deleting the error information in the header; and adding the next error information after the head in the first error correction linked list into the head, and then executing the step of determining the first error correction method sequence of the error information in the head according to the error information in the head of the first error correction linked list until the error correction of the last error information in the first error correction linked list is finished.

In another possible implementation manner, the error correction module 1103 is further configured to determine an error type of the error information in the header; and determining a first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods.

In another possible implementation manner, the apparatus further includes:

the acquisition module is used for acquiring a first error number of error information in an error Block when data errors occur in the flash memory last time; acquiring a second error number of error information in the error Block when the data error occurs at present;

the error correction module 1103 is further configured to determine a first error correction method sequence according to the first error number, the second error number, the error type, and the plurality of error correction methods.

In another possible implementation manner, the error correction module 1103 is further configured to select, when the second error number is not greater than the first error number, a first error correction method sequence corresponding to the error type from the multiple error correction method sequences according to the error type and a correspondence between the error type and the error correction method sequence.

the error correction module 1103 is further configured to select a first offset voltage value from the first Retry table, and correct error information in the header based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value; and when the error information in the header cannot be corrected successfully through the reference voltage value and each first offset voltage value in the first retry table, selecting a second offset voltage value from the second retry table, and correcting the error information in the header through the reference voltage value and the selected second offset voltage value.

the error correction module 1103 is further configured to determine a voltage adjustment range of the first error message according to the reference voltage value and the first offset interval of the Calibration error correction method; determining a third voltage value from the voltage regulation range; and correcting error information in the header according to the third voltage value.

In another possible implementation manner, the adding module 1102 is further configured to add a plurality of error messages that have failed to correct the sequence by using the first error correction method to the second error correction linked list;

the error correction module 1103 is further configured to perform error correction on the error information in the second error correction linked list one by one through a second error correction method sequence, where the second error correction method sequence includes at least one error correction method.

the error correction module 1103 is further configured to, when no error correction is performed by the SLDPC error correction method and the RAID error correction method at the current first time, perform error correction on the error information in the second error correction linked list one by the SLDPC error correction method; and for the error information which fails to be corrected by the SLDPC error correction method at present, when the error information is not corrected by the SLDPC error correction method and the RAID error correction method at the present second time, the error information which fails to be corrected by the SLDPC error correction method is corrected by the RAID error correction method.

The embodiment of the application provides a flash memory error correction device, which receives a read request, wherein the read request carries a position identifier of a first position of a flash memory and is used for reading data stored in the first position, when an error indication returned by the flash memory is received, a plurality of error messages of the read request are added into a plurality of first error correction linked lists, and error correction is performed in parallel according to the error messages in the plurality of first error correction linked lists. According to the method, the error information in the first error correction linked lists is corrected in parallel by adding the error information into the first error correction linked lists, so that the error correction time is shortened, and the error correction efficiency is improved.

It should be noted that: in the flash memory error correction apparatus provided in the above embodiment, when the flash memory error is corrected, only the division of the functional modules is illustrated, and in practical application, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the computing device is divided into different functional modules, so as to complete all or part of the functions described above. In addition, the flash memory error correction device provided by the above embodiment and the flash memory error correction method embodiment belong to the same concept, and the specific implementation process thereof is detailed in the method embodiment and will not be described herein again.

Fig. 12 is a schematic structural diagram of a computing device 1200 according to an embodiment of the present invention, where the computing device 1200 may generate a relatively large difference due to a difference in configuration or performance, and may include one or more processors (CPUs) 1201 and one or more memories 1202, where the memory 1202 stores at least one instruction, and the at least one instruction is loaded and executed by the processors 1201 to implement the methods provided by the above method embodiments. Of course, the computing device may also have components such as a wired or wireless network interface, a keyboard, and an input/output interface, so as to perform input/output, and the computing device may also include other components for implementing the functions of the device, which is not described herein again.

The embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the flash memory error correction method of the foregoing embodiment are implemented.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only for facilitating the understanding of the technical solutions of the present application by those skilled in the art, and is not intended to limit the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A flash memory error correction method, the method comprising:

correcting errors in parallel according to the error information in the first error correction linked lists;

the adding a plurality of error messages of the read request to a plurality of first error correction linked lists comprises:

determining a Die where each error message is located;

2. The method of claim 1, wherein performing error correction in parallel according to the error information in the plurality of first error correction linked lists comprises:

3. The method of claim 2, wherein the error correcting the error information of the first error correction linked list comprises:

4. The method according to claim 3, wherein the determining the first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list comprises:

determining an error type of error information in the header;

5. The method according to claim 4, wherein before determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods, the method further comprises:

6. The method of claim 5, wherein determining the first error correction method sequence according to the first number of errors, the second number of errors, the error type, and the plurality of error correction methods comprises:

7. The method of claim 3, wherein the first sequence of error correction methods includes a Read Retry error correction method;

8. The method according to claim 3 or 7, characterized in that the first sequence of error correction methods further comprises calibrating a Calibration error correction method;

determining a third voltage value from the voltage regulation range;

9. The method of claim 3, further comprising:

adding a plurality of error messages which fail in sequence error correction through the first error correction method into a second error correction linked list;

10. The method of claim 9, wherein the second error correction method sequence comprises a software low density parity check code (SLDPC) error correction method and a Redundant Array of Independent Disks (RAID) error correction method;

11. A flash memory error correction apparatus, the apparatus comprising:

the adding module is used for adding a plurality of error messages of the read request to a plurality of first error correction linked lists when receiving error indications returned by the flash memory;

the error correction module is used for correcting errors in parallel according to the error information in the first error correction linked lists;

the adding module is further used for determining a Die where each error message is located; and for each error message, adding the error message into an error correction linked list corresponding to the Die according to the Die where the error message is located.

12. The apparatus of claim 11, wherein the error correction module is further configured to correct error information of the first error correction linked list; and in the error correction process, error information in other first error correction linked lists in the plurality of first error correction linked lists is corrected in parallel.

13. The apparatus according to claim 12, wherein the error correction module is further configured to determine a first sequence of error correction methods for the error information in the header according to the error information in the header of the first error correction linked list, where the first sequence of error correction methods includes at least one error correction method; correcting error information in the header by the first error correction method sequence; when the error correction of the error information in the header is successful or the error correction is finished through the last error correction method in the first error correction method sequence, deleting the error information in the header; and adding the next error information after the header in the first error correction linked list into the header, and then executing the step of determining the first error correction method sequence of the error information in the header according to the error information in the header of the first error correction linked list until the error correction of the last error information in the first error correction linked list is finished.

14. The apparatus of claim 13, wherein the error correction module is further configured to determine an error type of the error message in the header; and determining the first error correction method sequence corresponding to the error type according to the error type and a plurality of error correction methods.

15. The apparatus of claim 13, wherein the first sequence of error correction methods comprises a Read Retry error correction method; the error correction module is further configured to select a first offset voltage value from a first Retry table, and correct error information in the header based on the reference voltage value of the Read Retry error correction method and the selected first offset voltage value; when the error information in the header cannot be corrected successfully through the reference voltage value and each first offset voltage value in the first retry table, selecting a second offset voltage value from a second retry table, and correcting the error information in the header through the reference voltage value and the selected second offset voltage value;

the first error correction method sequence further comprises a Calibration error correction method; the error correction module is further configured to determine a voltage adjustment range of the first error message according to a reference voltage value of the Calibration error correction method and a first offset interval; determining a third voltage value from the voltage regulation range; and correcting error information in the header according to the third voltage value.