CN111863105A - Memory cell detection method and memory detection method - Google Patents
Memory cell detection method and memory detection method Download PDFInfo
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- CN111863105A CN111863105A CN201910335924.XA CN201910335924A CN111863105A CN 111863105 A CN111863105 A CN 111863105A CN 201910335924 A CN201910335924 A CN 201910335924A CN 111863105 A CN111863105 A CN 111863105A
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- 230000006870 function Effects 0.000 claims abstract description 88
- 238000012360 testing method Methods 0.000 claims description 43
- 238000000034 method Methods 0.000 claims description 12
- 238000011990 functional testing Methods 0.000 claims description 6
- 230000005684 electric field Effects 0.000 claims description 5
- 238000010998 test method Methods 0.000 claims description 5
- 230000006386 memory function Effects 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 16
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- 238000013500 data storage Methods 0.000 description 2
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention relates to the technical field of storage unit detection, and provides a storage unit detection method and a storage detection method, wherein a storage unit comprises a storage unit for storing a data signal, and the storage unit detection method comprises the following steps: performing function detection on the storage unit; and when the storage function of the storage unit is qualified, performing at least one function detection on the storage unit. Wherein the function detection comprises: writing a high level signal to the memory cell; checking the level state of the storage unit after a preset time interval; and judging the storage function state of the storage unit according to the level state of the storage unit. The storage function state of the storage unit can be accurately detected.
Description
Technical Field
The invention relates to the technical field of storage unit detection, in particular to a storage unit detection method and a storage detection method.
Background
Dynamic Random Access Memory (DRAM) is a common type of Memory device. A dram generally includes a plurality of memory cells, each of which stores a data signal "0" or "1" via a capacitor.
The time length of each capacitor for storing the high level '1' needs to reach the preset time length, so that the stored data can be prevented from being wrong, and the dynamic storage function of the dynamic random access memory is realized.
Therefore, it is necessary to provide a detection method to perform a functional test on each memory cell in the dram to determine whether the time period for each capacitor to store the high level "1" can reach the preset time period.
It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a storage unit detection method and a storage detection method. The storage unit detection method can realize the detection of the storage function of the storage unit.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.
According to an aspect of the present invention, there is provided a memory cell testing method, the method comprising:
performing function detection on the storage unit;
Wherein the function detection comprises:
writing a high level signal to the memory cell;
checking the level state of the storage unit after a preset time interval;
judging whether the storage function of the storage unit is qualified or not according to the level state of the storage unit;
and when the storage function of the storage unit is qualified, performing at least one more function detection on the storage unit.
In an exemplary embodiment of the present invention, determining a storage function of the memory cell according to a level state of the memory cell includes:
when the upper level state of the storage unit is a high level, judging that the storage function of the storage unit is qualified;
and when the upper level state of the storage unit is a low level, judging that the storage function of the storage unit is unqualified.
In an exemplary embodiment of the invention, the preset time intervals are the same or different in a plurality of times of the function detection of the memory unit.
In an exemplary embodiment of the present invention, the memory unit performs the function detection under a preset test environment, and in a plurality of times of the function detections of the memory unit, the test environments of the function detections are the same or different.
In an exemplary embodiment of the invention, the test environment includes a temperature environment and/or an electric field environment.
In an exemplary embodiment of the present invention, the performing at least one function check on the storage unit further includes:
and performing the function detection on the storage unit once again.
In an exemplary embodiment of the present invention, a preset time interval in the first function detection is greater than a preset time interval in the second function detection.
In an exemplary embodiment of the present invention, the performing at least one function check on the storage unit further includes:
and performing the function detection on the storage unit twice.
According to an aspect of the present invention, there is provided a memory inspection method, wherein the memory includes a plurality of memory cells distributed in an array, and the method includes the above-mentioned memory cell inspection method.
In an exemplary embodiment of the present invention, a memory cell performs function detection in a preset test environment, where in a plurality of times of the function detections for the memory cell, the test environments of the function detections are the same or different, and the test environments include storage states of memory cells around the memory cell.
The invention provides a storage unit detection method and a storage detection method, wherein the storage unit detection method comprises the following steps: performing function detection on the storage unit; and when the storage function of the storage unit is qualified, performing at least one function detection on the storage unit. Wherein the function detection comprises: writing a high level signal to the memory cell; checking the level state of the storage unit after a preset time interval; and judging the storage function state of the storage unit according to the level state of the storage unit. On one hand, the storage unit detection method provided by the disclosure can realize the detection of the storage function of the storage unit; on the other hand, the memory cell detection method provided by the disclosure can more accurately detect the storage function of the memory cell through multiple times of function detection so as to eliminate the memory cells between pass and fail.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of a memory cell in the related art;
FIG. 2 is a schematic diagram of the logic of a related art method for checking a memory cell;
FIG. 3 is a flow chart of an exemplary embodiment of a memory cell detection method of the present disclosure;
FIG. 4 is a logic diagram of an exemplary embodiment of a memory cell detection method of the present disclosure;
FIG. 5 is a logic diagram of another exemplary embodiment of a memory cell detection method of the present disclosure;
FIG. 6 is a block diagram of an exemplary embodiment of a memory.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Fig. 1 is a schematic structural diagram of a memory cell in the related art. The memory cell includes a switching transistor T and a storage capacitor C. The control terminal of the switching transistor T is connected to the word line WL, the first terminal is connected to the data line BL, and the storage capacitor C is connected between the ground terminal GND and the second terminal of the switching transistor T, where the ground terminal may be another potential terminal. The data line BL may write a high level signal "1" to the storage capacitor C when the switching transistor T is turned on by a signal on the word line WL, and the charge on the storage capacitor C slowly leaks out over time after the switching transistor T is turned off by the signal on the word line WL. The time between the storage capacitor C leaking from the high level signal "1" to the low level signal "0" is the data storage time of the storage capacitor C. The data storage time of the storage capacitor C needs to be longer than a preset time to realize the dynamic storage function of the dynamic random access memory.
Fig. 2 is a schematic flow chart of a method for testing a memory cell in the related art. The method comprises the following steps: and writing a high level signal into the storage capacitor of the storage unit through the switching transistor T, and checking the state of the level on the storage capacitor after a preset time interval. If the level on the storage capacitor is high level, judging that the storage unit is qualified; and if the level on the storage capacitor is low, judging that the storage unit is unqualified. However, the storage capacity of some memory cells is between pass and fail, and when the memory cells are subjected to functional test, the test result may be pass. However, the memory cells between pass and fail affect the memory function of the memory in actual use.
Based on this, the present disclosure provides a memory cell testing method, as shown in fig. 3, which is a flowchart of an exemplary embodiment of the memory cell testing method of the present disclosure. The method comprises the following steps:
step S1: performing function detection on the storage unit;
step S2: and when the storage function of the storage unit is qualified, performing at least one function detection on the storage unit.
Wherein the function detection comprises: writing a high level signal to the memory cell; checking the level state of the storage unit after a preset time interval; and judging the storage function state of the storage unit according to the level state of the storage unit. The preset duration interval needs to be greater than the minimum duration of storing high level when the memory cell implements a normal memory function, for example, under JEDEC specifications, the preset duration interval needs to be greater than or equal to 64 ms. Writing a high level signal into the memory cell is writing a high level signal into a storage capacitor of the memory cell through the switching transistor T. The level state of the memory cell is the storage state of the storage capacitor in the memory cell.
The present exemplary embodiment provides a memory cell test method, where the memory cell includes a memory cell for storing a data signal, the memory cell test method including: performing function detection on the storage unit; and when the storage function of the storage unit is qualified, performing at least one function detection on the storage unit. Wherein the function detection comprises: writing a high level signal to the memory cell; checking the level state of the storage unit after a preset time interval; and judging the storage function state of the storage unit according to the level state of the storage unit. On one hand, the storage unit detection method provided by the disclosure can realize the detection of the storage function of the storage unit; on the other hand, the memory cell detection method provided by the disclosure can more accurately detect the storage function of the memory cell through multiple times of function detection so as to eliminate the memory cells between pass and fail.
The above steps are explained in detail below:
in the present exemplary embodiment, determining the storage function of the memory cell according to the level state of the memory cell may include: when the upper level state of the storage unit is a high level, judging that the storage function of the storage unit is qualified; and when the upper level state of the storage unit is a low level, judging that the storage function of the storage unit is unqualified.
In this exemplary embodiment, the preset time interval may affect the detection result of the storage unit, and the preset time intervals may be the same or different in the multiple times of the function detection of the storage unit. The storage unit is detected for multiple times at different preset time intervals, so that the storage unit can be detected in multiple detection states, and the accuracy of the detection result is further improved.
In the exemplary embodiment, different test environments may be responsive to the test results of the memory cells, and the test environments may include one or more of a temperature environment and an electric field environment. In the multiple times of the function detection of the memory unit, the test environments may be the same or different. The accuracy of the detection result can be further improved by detecting the storage unit for multiple times in different test environments.
In the present exemplary embodiment, as shown in fig. 4, a logic diagram of an exemplary embodiment of the memory cell detection method of the present disclosure is shown. Performing at least one more function test on the storage unit may include: and carrying out the function detection on the storage unit again. The preset time interval in the first time of the function detection can be larger than the preset time interval in the second time of the function detection. For example, the preset duration interval in the first function test may be 256ms, and the preset duration interval in the second function test may be 64 ms. In addition, the test environment in the first functional test may be the same as or different from the test environment in the second functional test.
In the present exemplary embodiment, as shown in fig. 5, a logic diagram of another exemplary embodiment of the memory cell detection method of the present disclosure is shown. Performing the function detection on the storage unit at least once again, may further include: and performing the function detection on the storage unit for two times. In the three-time function detection, the preset time intervals may be the same or different, and the test environments may be the same or different.
The exemplary embodiment also provides a memory detection method, wherein the memory comprises a plurality of memory cells distributed in an array, and the method comprises the above memory cell detection method.
The storage state of a memory cell surrounding a certain memory cell in the memory affects the electric field of the memory cell. For example, when all the memory cells around a certain memory cell store high level "1", the electric field of the memory cell is obviously different from that of the memory cells around the certain memory cell store low level "0", which causes the difference of the leakage current of the memory cell, and further affects the test result of the memory time. In this exemplary embodiment, a memory cell performs function detection in a preset test environment, and in a plurality of times of the function detections of the memory cell, the test environments of the function detections are the same or different, where the test environments may include storage states of memory cells around the memory cell.
As shown in fig. 6, which is a schematic structural diagram of an exemplary embodiment of a memory, the memory includes a plurality of the memory units 6 distributed in an array, and this exemplary embodiment is only described by taking a three-by-three array as an example, it should be understood that the memory may have more array structures. Wherein each memory cell 6 is connected to a word line WL and a data line BL. Different level states can be written into different memory cells through the word lines WL and the data lines BL. The states in the memory in which each memory cell 6 stores a charge may constitute different test environments. For example, in the 9 memory cells distributed in the array, when the memory cell located in the middle is checked, the charge storage states of the surrounding 8 memory cells may constitute a test environment of the middle memory cell. Wherein the charge storage state of the memory cell may include storing a high level "1" or storing a low level "0". In the multiple function tests of the memory unit, the test environment of each function test can be the same or different.
The memory detection method provided by the exemplary embodiment has the same technical features and working principles as the above-mentioned memory cell detection method, and the above-mentioned contents have been described in detail and are not described again here.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (10)
1. A memory cell detection method, comprising:
performing function detection on the storage unit;
wherein the function detection comprises:
writing a high level signal to the memory cell;
checking the level state of the storage unit after a preset time interval;
judging whether the storage function of the storage unit is qualified or not according to the level state of the storage unit;
And when the storage function of the storage unit is qualified, performing at least one more function detection on the storage unit.
2. The method of claim 1, wherein determining whether the memory function of the memory cell is qualified according to the level state of the memory cell comprises:
when the level state on the storage unit is high level, judging that the storage function of the storage unit is qualified;
and when the level state on the storage unit is low level, judging that the storage function of the storage unit is unqualified.
3. The memory cell detection method according to claim 1, wherein the preset time intervals are the same or different among the plurality of times of the function detections of the memory cell.
4. The method according to claim 1, wherein the memory cell performs the function test under a preset test environment, and the test environments of the function tests are the same or different among a plurality of times of the function tests of the memory cell.
5. The memory cell detection method of claim 4, wherein the test environment comprises a temperature environment and/or an electric field environment.
6. The storage unit detection method of claim 1, wherein performing at least one of the function detections on the storage unit comprises:
and carrying out the function detection on the storage unit again.
7. The memory cell detection method of claim 6, wherein the predetermined time interval in the first functional test is greater than the predetermined time interval in the second functional test.
8. The storage unit detection method of claim 1, wherein performing at least one of the function detections on the storage unit comprises:
and performing the function detection on the storage unit twice.
9. A method of testing a memory comprising a plurality of said memory cells distributed in an array, the method comprising the method of testing a memory cell of any of claims 1-8.
10. The memory test method according to claim 9, wherein the memory cell performs the function test under a preset test environment, and in the plurality of times of the function tests of the memory cell, the test environments of the function tests are the same or different, and the test environments include the memory states of the memory cells around the memory cell.
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Cited By (2)
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| CN115603713A (en) * | 2022-12-01 | 2023-01-13 | 深圳市恒运昌真空技术有限公司（Cn） | Pulse signal processing method and device and matching circuit |
| US11934683B2 (en) | 2022-03-02 | 2024-03-19 | Changxin Memory Technologies, Inc. | Method and apparatus for testing memory chip, and storage medium |
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| US11934683B2 (en) | 2022-03-02 | 2024-03-19 | Changxin Memory Technologies, Inc. | Method and apparatus for testing memory chip, and storage medium |
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