CN111863073B

CN111863073B - Resistive random access memory and drive control circuit thereof

Info

Publication number: CN111863073B
Application number: CN202010692595.7A
Authority: CN
Inventors: 黄天辉; 陈瑞隆; 王丹云; 刘美冬
Original assignee: Xiamen Semiconductor Industry Technology Research And Development Co ltd
Current assignee: Xiamen Semiconductor Industry Technology Research And Development Co ltd
Priority date: 2020-07-17
Filing date: 2020-07-17
Publication date: 2022-07-19
Anticipated expiration: 2040-07-17
Also published as: CN111863073A

Abstract

The invention discloses a drive control circuit of a resistive random access memory, which comprises: a low voltage drive control unit that generates a low voltage drive signal according to a write signal; the high-voltage transmission gate unit applies the low-voltage driving signal to a corresponding resistive random access memory unit in the resistive random access memory according to a high voltage provided by a preset power supply so as to write in the resistive random access memory unit. The drive control circuit of the embodiment of the invention adopts the low-voltage device and the low-voltage signal to realize low-voltage drive, thereby greatly reducing the occupied area of the SET/RESET drive part and realizing the reduction of the whole area of the resistive random access memory. The invention also discloses a resistive random access memory with the drive control circuit.

Description

Resistive random access memory and drive control circuit thereof

Technical Field

The invention relates to the technical field of storage, in particular to a drive control circuit of a resistive random access memory and the resistive random access memory with the drive control circuit.

Background

In the related art, as shown in fig. 1 and 2, a bipolar resistance change memory includes a plurality of resistance change memory cells 1, and when each resistance change memory cell operates according to the table shown in fig. 3, it is necessary to use devices having a high withstand voltage for the SET/RESET driving section 2 and the Y Select section 3.

However, a device with a higher withstand voltage relatively needs a larger occupied area, and with the continuous forward development of a semiconductor memory process, the area of the resistive random access memory cell RRAM cell is continuously shrunk, which results in that the occupied area of the resistive random access memory cell array is larger and larger under the condition that the PMOS/NMOS of the Y Select part and the SET/RESET driving part are high-voltage devices and cannot be shrunk, in particular, each bit line BL needs a group of Y Select and SET/RESET drivers, and when the area cannot be shrunk synchronously with the RRAM cell, the area of the resistive random access memory cannot be shrunk.

Disclosure of Invention

The present invention is directed to solving at least one of the problems in the art to some extent. Therefore, an object of the present invention is to provide a driving control circuit for a resistive random access memory, which uses a low voltage device and a low voltage signal to implement low voltage driving, so as to greatly reduce the occupied area of the SET/RESET driving portion and reduce the entire area of the resistive random access memory.

A second object of the present invention is to provide a resistive random access memory.

In order to achieve the above object, a driving control circuit of a resistive random access memory according to an embodiment of a first aspect of the present invention includes: a low voltage drive control unit that generates a low voltage drive signal according to the write signal; and the high-voltage transmission gate unit applies the low-voltage driving signal to a corresponding resistive random access memory unit in the resistive random access memory according to a high voltage provided by a preset power supply so as to write in the resistive random access memory unit.

According to the drive control circuit of the resistive random access memory, the low-voltage drive control unit outputs the low-voltage drive signal by adopting the low-voltage signal and the low-voltage device, the low-voltage drive signal is applied to the corresponding resistive random access memory unit in the resistive random access memory only by the high-voltage transmission gate unit according to the high voltage provided by the preset power supply, and the writing operation of the resistive random access memory unit is realized, so that most of circuits which originally need to completely adopt the high-voltage signal and the high-voltage device can use the low-voltage device and the low-voltage signal with smaller area, the occupied area of the SET/RESET drive part can be greatly reduced, the whole area of the resistive random access memory is reduced, and the miniaturization of the resistive random access memory is facilitated.

In addition, the driving control circuit of the resistive random access memory proposed according to the above embodiment of the present invention may further have the following additional technical features:

optionally, according to an embodiment of the present invention, the driving control circuit of the resistive random access memory further includes an isolation high-voltage unit, and the isolation high-voltage unit is disposed between the low-voltage driving control unit and the high-voltage transmission gate unit to isolate a high voltage provided by the preset power supply.

Optionally, according to an embodiment of the invention, the high voltage transmission gate unit includes: a source electrode of the first high-voltage PMOS tube is connected to the preset power supply, a grid electrode of the first high-voltage PMOS tube is connected to an SETB signal end, and a drain electrode of the first high-voltage PMOS tube is connected to a bit line of the resistive random access memory unit; and the source electrode of the second high-voltage PMOS tube is connected to the preset power supply, the grid electrode of the second high-voltage PMOS tube is connected to the RESETB signal end, and the drain electrode of the second high-voltage PMOS tube is connected to the ground wire of the resistive random access memory unit.

Optionally, according to an embodiment of the present invention, the isolation high voltage unit includes: the drain electrode of the first N-type EDMOS tube is connected with the drain electrode of the first high-voltage PMOS tube, the grid electrode of the first N-type EDMOS tube is connected to a selection signal end, and the source electrode of the first N-type EDMOS tube is connected with the first output end of the low-voltage drive control unit; and the drain electrode of the second N-type EDMOS tube is connected with the drain electrode of the second high-voltage PMOS tube, the grid electrode of the second N-type EDMOS tube is connected to the selection signal end, and the source electrode of the second N-type EDMOS tube is connected with the second output end of the low-voltage drive control unit.

Alternatively, according to an embodiment of the present invention, the low voltage driving control unit includes: a first driver and a second driver; a source electrode of the first low-voltage NMOS tube is connected with the first driver, a grid electrode of the first low-voltage NMOS tube is connected to a SET signal end, and a drain electrode of the first low-voltage NMOS tube is used as a first output end of the low-voltage drive control unit; and the source electrode of the second low-voltage NMOS tube is connected with the second driver, the grid electrode of the second low-voltage NMOS tube is connected to a RESET signal end, and the drain electrode of the second low-voltage NMOS tube is used as a second output end of the low-voltage drive control unit.

Alternatively, according to an embodiment of the present invention, a SET signal provided from the SET signal terminal has a level opposite to that of a SETB signal provided from the SETB signal terminal, and a RESET signal provided from the RESET signal terminal has a level opposite to that of the RESETB signal provided from the RESETB signal terminal.

Optionally, according to an embodiment of the present invention, the resistance change memory unit includes a resistance change element and a control transistor, a first end of the control transistor is connected to a bit line of the resistance change memory unit, a control end of the control transistor is connected to a word line of the resistance change memory unit, a second end of the control transistor is connected to one end of the resistance change element, and another end of the resistance change element is connected to a ground line of the resistance change memory unit.

Specifically, in some embodiments of the present invention, the control transistor may be an NMOS transistor.

In order to achieve the above object, a resistive random access memory according to an embodiment of a second aspect of the present invention includes: a plurality of resistance change memory cells; each drive control circuit is connected with the corresponding resistive random access memory unit to control the corresponding resistive random access memory unit to perform writing operation.

According to the resistive random access memory provided by the embodiment of the invention, the corresponding resistive random access memory unit is controlled by the drive control circuit, and under the condition that the resistive random access memory unit is continuously miniaturized, the corresponding drive control circuit adopts the low-voltage device and the low-voltage signal to realize low-voltage drive control, and can synchronously carry out area miniaturization along with the resistive random access memory unit, so that the occupied area of a SET/RESET drive part can be greatly reduced, the whole area is reduced, and the miniaturization is facilitated.

In addition, the resistive random access memory proposed according to the above embodiment of the present invention may further have the following additional technical features:

optionally, in an embodiment of the present invention, a plurality of the resistive random access memory cells are arranged in an array.

Drawings

Fig. 1 is a schematic diagram of a control circuit of a resistance change memory cell in the related art;

fig. 2 is a schematic diagram of a control circuit of a row of resistive random access memory cells in the related art;

FIG. 3 is an operation table of the resistance change memory cell;

fig. 4 is a schematic diagram of a drive control circuit of a resistance change memory according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a driving control circuit of a resistance change memory according to another embodiment of the present invention;

FIG. 6 is a timing diagram of control signals according to one embodiment of the present invention;

FIG. 7 is a voltage comparison diagram of a control signal according to the related art and a control signal according to an embodiment of the invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

According to the resistive random access memory and the drive control circuit thereof, the high-voltage power supply is provided by the high-voltage-resistant high-voltage transmission gate unit, and the high-voltage power supply is blocked by the sampling isolation high-voltage unit, so that a circuit which originally needs to completely adopt high-voltage devices can be mostly changed into low-voltage devices with smaller areas, the areas of the low-voltage devices can be greatly reduced, and the low-voltage drive control unit adopts the low-voltage devices and low-voltage signals to realize low-voltage drive, thereby greatly reducing the occupied area of a SET/RESET drive part, realizing the reduction of the whole area of the resistive random access memory, and facilitating the miniaturization of the resistive random access memory.

In order to better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

A drive control circuit of a resistance change memory and a resistance change memory having the same proposed by an embodiment of the present invention are described below with reference to the drawings.

As shown in fig. 4 and 5, the driving control circuit of the resistive random access memory according to the embodiment of the present invention includes a low voltage driving control unit 101 and a high voltage transmission gate unit 102.

The low voltage driving control unit 101 generates a low voltage driving signal according to a writing signal, such as a SET signal or a RESET signal, and the high voltage transmission gate unit 102 applies the low voltage driving signal to a corresponding resistance change memory unit 200 in the resistance change memory according to a high voltage provided by a preset power supply VH to perform a writing operation on the resistance change memory unit 200.

It should be noted that, in the embodiment of the present invention, the high voltage and the low voltage are relative, that is, the high voltage means that the driving voltage applied to the high-voltage device is high, and the low voltage means that the driving voltage applied to the low-voltage device is low, for example, the high voltage may be 2.8V, the low voltage may be 0.9V, and both are high relative to the low potential of 0V.

Therefore, in the embodiment of the present invention, the low voltage driving control unit 101 may use a low voltage device and a low voltage signal to implement low voltage driving, so that the occupied area of the SET/RESET driving portion may be greatly reduced, and the entire area of the resistive random access memory may be reduced.

Further, in an embodiment of the present invention, as shown in fig. 4 or fig. 5, the driving control circuit of the resistive random access memory further includes an isolation high voltage unit 103, where the isolation high voltage unit 103 is disposed between the low voltage driving control unit 101 and the high voltage transmission gate unit 102 to isolate the high voltage provided by the preset power VH.

The high-voltage power supply VH of the high-voltage transmission gate unit 102 is resisted by the isolation high-voltage unit 103, so that the low-voltage driving control unit 101 can conveniently realize low-voltage driving by adopting low-voltage devices and low-voltage signals, and the low-voltage driving control unit which originally adopts all high-voltage devices can be changed into a low-voltage device with a small area.

Specifically, as shown in fig. 4 or fig. 5, the high voltage transmission gate unit 102 includes a first high voltage PMOS transistor MP1 and a second high voltage PMOS transistor MP 2.

The source of the first high-voltage PMOS transistor MP1 is connected to a preset power supply VH, for example, 2.8V, the gate of the first high-voltage PMOS transistor MP1 is connected to the SETB signal terminal, and the drain of the first high-voltage PMOS transistor MP1 is connected to the bit line BL of the resistance change memory cell 200; the source of the second high-voltage PMOS transistor MP2 is connected to the preset power VH, the gate of the second high-voltage PMOS transistor MP2 is connected to the RESETB signal terminal, and the drain of the second high-voltage PMOS transistor MP2 is connected to the ground line SL of the resistive memory cell 200.

Therefore, in the embodiment of the present invention, only two PMOS transistors with high voltage endurance are needed to provide the high voltage power VH, for example, 2.8V, and since the number of PMOS series devices providing the high voltage power becomes smaller, the area thereof can be reduced.

Also, as shown in fig. 4 or 5, the isolation high-pressure unit 103 includes a first N-type EDMOS tube N1 and a second N-type EDMOS tube N2.

The drain of the first N-type EDMOS transistor N1 is connected to the drain of the first high-voltage PMOS transistor MP1, the gate of the first N-type EDMOS transistor N1 is connected to the selection signal terminal YN, and the source of the first N-type EDMOS transistor N1 is connected to the first output terminal of the low-voltage drive control unit 101; a drain of the second N-type EDMOS transistor N2 is connected to a drain of the second high-voltage PMOS transistor MP2, a gate of the second N-type EDMOS transistor N2 is connected to the selection signal terminal YN, and a source of the second N-type EDMOS transistor N2 is connected to the second output terminal of the low-voltage drive control unit 101.

In this embodiment, by providing the isolated high voltage unit 103, and the isolated high voltage unit 103 employs a NEDMOS transistor to withstand a high potential, the driving control circuit that originally would employ all high voltage devices can be changed to a low voltage device having a smaller area, and thus the occupied area can be greatly reduced.

Alternatively, in one embodiment of the present invention, the low voltage driving control unit 101 includes: the first driver 10 and the second driver 20, the first low voltage NMOS transistor MN1 and the second low voltage NMOS transistor MN 2.

The source of the first low-voltage NMOS transistor MN1 is connected to the first driver 10, the gate of the first low-voltage NMOS transistor MN1 is connected to the SET signal end, and the drain of the first low-voltage NMOS transistor MN1 is used as the first output end of the low-voltage drive control unit 101; the source of the second low voltage NMOS transistor MN2 is connected to the second driver 20, the gate of the second low voltage NMOS transistor MN2 is connected to the RESET signal terminal, and the drain of the second low voltage NMOS transistor MN2 serves as the second output terminal of the low voltage driving control unit 101.

In the low voltage driving control unit 101 of the present embodiment, the originally used high voltage NMOS is changed to a low voltage NMOS device, so that the entire area of the control circuit can be greatly reduced.

In the embodiment of the present invention, as shown in fig. 6, the SET signal provided by the SET signal terminal has a level opposite to that of the SETB signal provided by the SETB signal terminal, and the RESET signal provided by the RESET signal terminal has a level opposite to that of the RESETB signal provided by the RESETB signal terminal.

As shown in fig. 6, in the timing waveform diagram of the driving control circuit according to the embodiment of the present invention, a write operation can be performed on the resistance change memory cell 200 when the SET signal is at a high level or the RESET signal is at a high level by the SET signal, the RESET signal, the YN signal, the SETB signal, the RESETB signal, and the VH signal, and the operation of the resistance change memory cell 200 is as shown in the table in fig. 3.

In the embodiment of the present invention, as shown in fig. 6 and 7 in combination, the high voltage VH is supplied by the high voltage PMOS and withstood by the high voltage VH by the NEDMOS, so that the SET/reset driving part can be replaced with the low voltage NMOS, and the area can be greatly reduced by using the low voltage NMOS.

Therefore, the driving control circuit of the resistive random access memory according to the embodiment of the invention mainly utilizes the high-voltage resistant PMOS to provide the high-voltage power supply VH and the N EDMOS to withstand the high voltage, so that the driving portion which originally needs to adopt all the high-voltage devices can be changed into the low-voltage devices with smaller area. In addition, the area of the PMOS series device for providing the high-voltage power supply is reduced, and the area of the original high-voltage NMOS is also reduced, so that the whole area can be greatly reduced. In addition, the original control circuit needs to provide a high-voltage signal and can also be changed into a low-voltage signal for control, so that the control circuit can be further simplified and reduced, and the miniaturization of the resistive random access memory is realized.

Alternatively, according to an embodiment of the present invention, as shown in fig. 4 or fig. 5, the resistive memory cell 200 includes a resistive element 201 and a control transistor 202, a first end of the control transistor 202 is connected to a bit line BL of the resistive memory cell 200, a control end of the control transistor 202 is connected to a word line WL of the resistive memory cell 200, a second end of the control transistor 202 is connected to one end of the resistive element 201, and another end of the resistive element 201 is connected to a ground line SL of the resistive memory cell 200.

The resistive element 201 may be of a sandwich structure, that is, composed of a top electrode, a resistive dielectric layer, and a bottom electrode. The metal material of the bottom electrode and the top electrode of the resistive switching element may be TiN, and may be other metal materials, which is not specifically limited herein.

Optionally, as an embodiment, the resistive medium layer may be a binary transition metal oxide.

In some embodiments of the invention, when the resistive element is prepared, the etching process and the deposition process can be adopted to intersect, so that the etching process can be simplified, the complexity of etching materials can be reduced, the forming process of the conductive wires can be gathered, the conductive wires are formed and gathered at the top/bottom electrodes, the distribution is uniform and uniform, and the resistance change performance is greatly improved. In addition, the plasma damage area can be disabled, oxidation treatment is not needed, and the process is simple and reliable.

Alternatively, in an embodiment of the present invention, as shown in fig. 4 or fig. 5, the control transistor 202 may be an NMOS transistor.

The writing operation of the resistive element is controlled by the transistor, so that the interference of adjacent resistive memory units can be well isolated, and the method is more suitable for being compatible with a CMOS (complementary metal oxide semiconductor) process.

In addition, as shown in fig. 5, a resistive random access memory 1000 according to an embodiment of the present invention includes a plurality of resistive random access memory cells 200 and a plurality of driving control circuits of the resistive random access memory as described in the above embodiments, wherein each driving control circuit is connected to a corresponding resistive random access memory cell 200 to control the corresponding resistive random access memory cell 200 to perform a writing operation.

Alternatively, in an embodiment of the present invention, the plurality of resistive random access memory cells 200 may be arranged in an array.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above should not be understood to necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A drive control circuit of a resistance change memory, characterized by comprising:

a low voltage drive control unit that generates a low voltage drive signal according to a write signal;

the high-voltage transmission gate unit applies the low-voltage driving signal to a corresponding resistive random access memory unit in the resistive random access memory according to high voltage provided by a preset power supply so as to write in the resistive random access memory unit;

the isolation high-voltage unit is arranged between the low-voltage drive control unit and the high-voltage transmission gate unit and is used for isolating the high voltage provided by the preset power supply;

wherein the high voltage transmission gate unit includes:

a source electrode of the first high-voltage PMOS tube is connected to the preset power supply, a grid electrode of the first high-voltage PMOS tube is connected to a SETB signal end, and a drain electrode of the first high-voltage PMOS tube is connected to a bit line of the resistive random access memory unit;

a source electrode of the second high-voltage PMOS tube is connected to the preset power supply, a grid electrode of the second high-voltage PMOS tube is connected to a RESETB signal end, and a drain electrode of the second high-voltage PMOS tube is connected to a ground wire of the resistive random access memory unit;

wherein the isolation high voltage unit includes:

the drain electrode of the first N-type EDMOS tube is connected with the drain electrode of the first high-voltage PMOS tube, the grid electrode of the first N-type EDMOS tube is connected to a selection signal end, and the source electrode of the first N-type EDMOS tube is connected with the first output end of the low-voltage drive control unit;

a second N-type EDMOS tube, wherein the drain electrode of the second N-type EDMOS tube is connected with the drain electrode of the second high-voltage PMOS tube, the grid electrode of the second N-type EDMOS tube is connected to the selection signal end, and the source electrode of the second N-type EDMOS tube is connected with the second output end of the low-voltage drive control unit;

wherein the low voltage driving control unit includes:

a first driver and a second driver;

a source electrode of the first low-voltage NMOS tube is connected with the first driver, a grid electrode of the first low-voltage NMOS tube is connected to an SET signal end, and a drain electrode of the first low-voltage NMOS tube is used as a first output end of the low-voltage drive control unit;

and the source electrode of the second low-voltage NMOS tube is connected with the second driver, the grid electrode of the second low-voltage NMOS tube is connected to a RESET signal end, and the drain electrode of the second low-voltage NMOS tube is used as a second output end of the low-voltage drive control unit.

2. The drive control circuit of the resistance change memory according to claim 1, wherein a SET signal provided from the SET signal terminal has a level opposite to that of a RESETB signal provided from the RESETB signal terminal, and wherein a RESET signal provided from the RESET signal terminal has a level opposite to that of the RESETB signal provided from the RESETB signal terminal.

3. The drive control circuit of the resistive random access memory according to any one of claims 1 to 2, wherein the resistive random access memory cell includes a resistive random access element and a control transistor, a first end of the control transistor is connected to a bit line of the resistive random access memory cell, a control end of the control transistor is connected to a word line of the resistive random access memory cell, a second end of the control transistor is connected to one end of the resistive random access element, and the other end of the resistive random access element is connected to a ground line of the resistive random access memory cell.

4. The drive control circuit of the resistive random access memory according to claim 3, wherein the control transistor is an NMOS transistor.

5. A resistance change memory characterized by comprising:

a plurality of resistance change memory cells;

the drive control circuit of the resistive random access memory according to any one of claims 1 to 4, wherein each drive control circuit is connected with a corresponding resistive random access memory unit to control the corresponding resistive random access memory unit to perform a writing operation.

6. The resistive random access memory according to claim 5, wherein the plurality of resistive random access memory cells are arranged in an array.