CN111852397A

CN111852397A - Induction heating device for packing

Info

Publication number: CN111852397A
Application number: CN202010907487.7A
Authority: CN
Inventors: 殷孝雎; 王育欣; 王黎明; 王大朋; 金石; 朱连成; 赵琰; 高阳; 杨政; 李英杰; 杨文革; 李云祥; 俞志兴; 王志伟
Original assignee: Liaoning Haile Energy Saving Technology Co Ltd; Shenyang Institute of Engineering
Current assignee: Liaoning Haile Energy Saving Technology Co Ltd; Shenyang Institute of Engineering
Priority date: 2020-09-02
Filing date: 2020-09-02
Publication date: 2020-10-30

Abstract

The invention discloses a heating power supply for a packing of an oil field, belonging to a protection device in the oil extraction process of an oil well. The invention provides a heating power supply device with good use effect. The device mainly comprises a power supply circuit, a high-frequency wire, a fixed high-temperature shell and a high-power quick-connection high-temperature plug, wherein the power supply part comprises a main processor, an FPGA (field programmable gate array), a power main circuit, a current acquisition part, an RS485 bus first monitoring part, an RS485 bus second monitoring part and a driving circuit; the signal transmission port of the current acquisition part is connected with the signal transmission port of the FPGA; and a signal input port of the first monitoring part of the RS485 bus is connected with a signal output port of the driving circuit. The above units are connected with other auxiliary equipment packing heating devices. The oil production well produces heat energy to the inside of the packing exposed outside in the working process, especially in winter, so that crude oil is not waxed, the abrasion between the sucker rod and the sleeve is reduced, the service life of the sucker rod is prolonged, the heat loss is reduced by using the device, meanwhile, the resistance between the sucker rod and the oil pumping pipe is reduced, the efficiency of the oil pumping unit is improved, and the power consumption is reduced.

Description

Induction heating device for packing

Technical Field

The invention belongs to the technical field of power circuits of equipment protection processing technology of oil extraction engineering, and particularly relates to a protection device used in an oil extraction process of an oil pumping unit.

Background

Oil fields in China are mainly distributed in high and cold regions, the temperature is 45 ℃ below zero in the lowest region, the annual average temperature is below 10 ℃, crude oil is easy to condense in a low-temperature environment, particularly in winter, the bottom of a packing exposed outside is frozen, oil extraction output is influenced, the crude oil is easy to wax, wax melting cannot be carried out on the structure of the packing, and the yield is influenced due to the fact that a sucker rod and a sleeve are greatly damaged or the sucker rod is clamped. The heating device is provided aiming at the problem, so that the crude oil is not waxed, the abrasion between the sucker rod and the sleeve is reduced, the service life of the sucker rod is prolonged, the heat loss is reduced by using the heating device, the resistance between the sucker rod and the oil pumping pipe is reduced, the efficiency of the oil pumping unit is improved, and the power consumption is reduced.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a heating power supply device with good use effect. The invention relates to a heating power supply for a packing of an oil field, belonging to a protection device in the oil extraction process of an oil well. The device is characterized by mainly comprising a power supply circuit and a heating body, wherein the heating body is formed by winding a sucker rod (1), an oil pipe (2) and a high-frequency wire (3) in the direction of (4), winding the high-frequency wire on a fixed high-temperature shell (5), connecting the wires by a high-power quick-connection high-temperature plug (9), distributing magnetic force lines in the direction of (6), and forming the whole heating body in the directions of (7) and (8).

The device mainly comprises a power circuit, a high-frequency wire, a fixed high-temperature shell, a high-power quick-connection high-temperature plug, various units connected with each other and a packing heating device of other auxiliary equipment. The oil production well produces heat energy to the inside of the packing exposed outside in the working process, especially in winter, so that crude oil is not waxed, the abrasion between the sucker rod and the sleeve is reduced, the service life of the sucker rod is prolonged, the heat loss is reduced by using the device, meanwhile, the resistance between the sucker rod and the oil pumping pipe is reduced, the efficiency of the oil pumping unit is improved, and the power consumption is reduced.

The invention aims to solve the problems and provides an induction heating power supply circuit with good use effect. In order to achieve the purpose, the invention adopts the following technical scheme that the power monitoring device comprises a main processor, an FPGA, a power main circuit, a current acquisition part, an RS485 bus first monitoring part, an RS485 bus second monitoring part and a driving circuit, and is characterized in that a control signal input port of the driving circuit is connected with a control signal output port of the main processor, a signal transmission port of the driving circuit is connected with a signal transmission port of the FPGA, and a control signal output port of the driving circuit is connected with a control signal input port of the power main circuit;

the signal transmission port of the current acquisition part is connected with the signal transmission port of the FPGA;

a signal input port of the first monitoring part of the RS485 bus is connected with a signal output port of the driving circuit;

a signal input port of a second monitoring part of the RS485 bus is connected with a signal output port of the driving circuit;

the electric energy input end of the power main circuit is connected with single-phase commercial power.

As a preferable scheme, the main processor of the invention adopts an STM32H743IIT6 ARM processor U5,

pins

158, 148, 135, 126, 113, 102, 90, 71, 61, 22 and 14 of U5 are grounded, and

pins

172, 159, 149, 136, 127, 114, 103, 91, 82, 72, 62, 49, 36, 23 and 15 of U5 are connected to + 3.3V;

a pin 1 of an MPM-20-12 chip U55 is connected with a pin 2 of a UU9.8 common mode inductor L5, a pin 1 of L5 is respectively connected with one end of a rheostat R299 and one end of a fuse F1, the other end of F1 is connected with a pin L, the other end of R299 is respectively connected with a pin 3 of N, L5, a pin 4 of L5 is connected with a pin 2 of U55, a pin 3 of U55 is respectively connected with one end of a capacitor C203, the positive pole of the capacitor C204 and +12V, and the other end of C203 is respectively connected with a pin 4 of U55, the negative pole of the C204 and GND;

one end of the resistor R2 is connected with U5_ BOOT0, and the other end of the resistor R2 is connected with GND;

a pin 1 of a chip U60 of SP3485 is connected with a pin U5_ PA3,

pins

2 and 3 of U60 are connected with a pin U5_ PA1, a pin 4 of U60 is connected with a pin U5_ PA2, pins 5-8 of U60 are correspondingly connected with GND, A, B and +3.3V respectively, a resistor R290 is connected with B, GND respectively, and a resistor R291 is connected with A and +3.3V respectively;

a pin 1 of a chip U64 of SP3485 is connected with a pin U5_ PA10,

pins

2 and 3 of U64 are connected with a pin U5_ PA8, a pin 4 of U64 is connected with a pin U5_ PA92,

pins

5, 6, 7 and 8 of U64 are correspondingly connected with GND, A, B and +3.3V respectively, resistors R292 are connected with B, GND respectively, and resistors R293 are connected with A and +3.3V respectively;

the 1 pin of the SP3485 chip U63 is connected with U5_ PA10, the 2 and 3 pins of U63 are connected with U5_ PA8, the 4 pin of U63 is connected with U5_ PA9, the 5, 6, 7 and 8 pins of U63 are correspondingly connected with GND, A, B and +3.3V respectively, the resistors R294 are respectively connected with B, GND, and the resistors R295 are respectively connected with A and + 3.3V;

the capacitors C85 and C69-C82 are connected between +3.3V, GND in parallel;

+3.3V is respectively connected with RESET, one end of a capacitor C84 and one end of a switch SW1 through a resistor R24, and the other end of C84 is respectively connected with GND and the other end of SW 1;

a pin 1 of a U19 of the SD8942/A6166 chip is respectively connected with a pin 6 of U19 and one end of an inductor L3 through a capacitor C19, the other end of L3 is respectively connected with +5V and one end of a resistor R206, the other end of R206 is respectively connected with one end of a resistor R205 and a pin 3 of U19, the other end of R205 is respectively connected with GND and a pin 2 of U19, a pin 4 of U19 is respectively connected with a pin 5, +12V of U19, one end of a capacitor C22, one end of a capacitor C23 and one end of a capacitor C24, and the other end of C22 is respectively connected with the other end of C23, the other end of C24 and GND;

a pin 1 of the 4-pin plug-in P3 is connected with GND, a pin 3 of the P3 is respectively connected with one end of U5_ JTMS and one end of a resistor R19, the other end of the R19 is connected with +3.3V, a pin 2 of the P3 is respectively connected with one end of U5_ JTCK and one end of a resistor R22, the other end of the R22 is connected with GND, and a pin 1 of the P3 is connected with GND;

a pin 4 of a crystal oscillator Y1 is connected with GND, a pin 1 of Y1 is respectively connected with one end of U5_ OSC _ OUT and one end of a capacitor C67, the other end of C67 is respectively connected with GND, a pin 2 of Y1 and one end of a capacitor C68, and the other end of C68 is respectively connected with a pin 3 of Y1 and U5_ OSC _ IN;

one end of the crystal oscillator Y2 is connected to one end of a capacitor C66 and U5_ OSC32_ IN, the other end of C66 is connected to GND and one end of a capacitor C83, and the other end of C83 is connected to the other end of Y2 and U5_ OSC32_ OUT.

As another preferable scheme, the pin 171 of the U5 of the invention is respectively connected with the pin 37 of U5, one end of a capacitor C43, one end of a capacitor C44 and GND through a resistor R5, the other end of a capacitor C43 is respectively connected with the pin 39 of U5, the other end of a capacitor C44 and one end of a resistor R4, and the other end of a resistor R4 is connected with + 3.3V;

a pin 125 of the U5 is respectively connected with GND and one end of a capacitor C39 through a capacitor C41, and the other end of the C39 is connected with a pin 81 of the U5;

a pin 38 of U5 is respectively connected with +3.3V and one end of a capacitor C40, and the other end of C40 is connected with GND;

the 6 pins of U5 are respectively connected with +3.3V and one end of a capacitor C36, the other end of C36 is respectively connected with GND and one end of a resistor R8, and the other end of R8 is connected with the 48 pin of U5;

pin 166 of U5 is connected to U5_ BOOT 0;

RESET is connected to pin 31 of U5.

As another preferable scheme, the FPGA of the present invention employs H7-10, J7-10, B2, B15, C5, C12, D7, D10, E4, and E13 pins of EP4CE10F17C8 chip U22 to GND, G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, E2, H16, and H15 pins of U22 to GND;

a Vin pin of an HT7550-1 chip VR1 is respectively connected with capacitors C31, C32, C53 and +5V, the other end of C31 is respectively connected with GND, the other end of C32, the other end of C53, the GND pin of VR1, one ends of capacitors C33-38, one end of capacitor C42 and one ends of capacitors C45-49, and the other end of capacitor C33 is respectively connected with a Vout pin of VR1, the other ends of C34-38, the other end of capacitor C42, the other ends of capacitors C45-49 and + 3.3V;

a Vin pin of an HT7550-1 chip VR2 is respectively connected with one end of a capacitor C50, one end of a capacitor C51 and one end of a capacitor C55 at +3.3V, the other end of the C50 is respectively connected with GND, the other end of a capacitor C51, the other end of a capacitor C55, a GND pin of VR2, a cathode of the capacitor C52 and one end of a capacitor C56, and a positive electrode of the C52 is respectively connected with a Vout pin of VR2, the other end of the capacitor C56 at + 1.2V;

vin pins of an HT7550-1 chip VR3 are respectively connected with one ends and +5V of capacitors C61-63, the other ends of C61-63 are respectively connected with GND, a GND pin of VR3, a cathode of a capacitor C65, one end of a capacitor C86, one end of a capacitor C88, one end of a capacitor C89 and one end of a capacitor C93, and a positive electrode of C65 is respectively connected with a Vout pin of VR3, the other end of the capacitor C86, the other end of the capacitor C88, the other end of the capacitor C89 and the other end of the capacitor C93 at + 2.5V;

the 1 pin of the SP3485 chip U65 is B4, the 2 and 3 pins of U65 are D5, and the 4 pin of U65 is D6; the

pins

5, 6, 7 and 8 of the U65 are correspondingly connected with GND, A, B and +3.3V respectively, the resistor R275 is connected with B, GND respectively, and the resistor R2765 is connected with A and +3.3V respectively.

As another preferred scheme, the L5 pin of the U22 of the invention is connected with +2.5V, the N4 pin of U22 is connected with +1.2V, the F12 pin of U22 is connected with +2.5V, the D13 pin of U22 is connected with +1.2V, and the E12 pin and the M5 pin of U22 are connected with GND;

an H4 pin of U22 is respectively connected with +2.5V, one end of a resistor R131 and an H12 pin of U22 through a resistor R121, an H3 pin of U22 is connected with GND through a resistor R128, and the other end of R131 is connected with a J5 pin of U22;

the H13 pin of U22 is respectively connected with the G12 pin of U22, GND and one end of a resistor R241, and the other end of R241 is connected with the J3 pin of U22;

the H14 pin of U22 is connected with +3.3V through a resistor R252, the H5 pin of U22 is connected with +3.3V through a resistor R253, and the F4 pin of U22 is connected with +3.3V through a resistor R254;

pins

2 and 10 of a JTAG-10-FPGA interface JTAG1 are connected with GND, and pin 4 of a JTAG1 is connected with + 2.5V;

e3, G3, K3, M3, P4, P7, T1, P10, P13, T16, K14, M14, E14, G14, A16, C10, C13, A1, C4 and C7 of U22 are connected with pins at +3.3V, G6-G10, H6, H11 and K7 of U22 are connected with pins at + 1.2V;

2 pins of the crystal oscillator XTAL1 are connected with GND, 3 pins of the crystal oscillator XTAL1 are connected with CLK _1, and 4 pins of the crystal oscillator XTAL1 are connected with + 3.3V;

pins

6, 5, 2 and 8 of the M25P16 chip U30 are correspondingly connected with EPCS _ CLK, EPCS _ ASDO, EPCS _ DATA0 and +3.3V respectively, pin 4 of U30 is connected with GND,

pins

3 and 7 of U30 are connected with +3.3V, and pin 1 of U30 is connected with EPCS _ CS.

As another preferable scheme, the power main circuit comprises an air switch K1, one end of K1 is connected to the mains supply, the other end of K1 is connected to the primary side of a transformer T1, one end of the first secondary side of T1 is connected to the cathode of a diode D1, the drain of an IGBT Q2 and Q2_ D, the anode of D1 is connected to the source of an IGBT Q1 and Q1_ S, the gate of Q1 is connected to Q1_ B, the drain of Q1 is connected to Q1_ D, the cathode of a diode D2 and the 1 pin of a common mode inductor L2, the anode of D2 is connected to the source of Q2 and Q2_ S, the gate of Q2 is connected to Q2_ B, and the 3 pin of L2 is connected to the other end of the second secondary side of T1;

the 2 pin of L2 is connected with the anode of diode D5 and the cathode of diode D7, the cathode of D5 is connected with the cathode of diode D6 and one end of inductor L1, the other end of L1 is connected with one end of capacitor C6 and the collector of NPN triode Q3, the base of Q3 is connected with Q3_ B, the emitter of Q3 is connected with Q3_ S, one end of capacitors C1-C1, the drain of IGBT Q1 and the drain of IGBT Q1, the other end of C1-C1 is connected with one end of capacitors C1-C1, the source of Q1, Q1_ S, the drain of IGBT Q3, the drain of IGBT Q1 and the primary side of transformer main transformer T1, the primary side of T1 is connected with one end of capacitor C1, one end of capacitor C1 and one end of capacitor C1, the drain of the, The other end of the C6, the anode of the D7 and the anode of the diode D8 are connected, and the cathode of the D8 is respectively connected with the 4 pin of the L2 and the anode of the D6;

one end of a first secondary side of the T2 is connected with one end of each of the capacitors C110-C115, the other end of each of the capacitors C110-C115 is connected with a pin 1 of the two-pin plug-in P8, and a pin 2 of the P8 is connected with the other end of the first secondary side of the T2 through the original side of the current transformer T3.

As another preferred scheme, the current collection part of the invention comprises an adjustable reference source control circuit, a linear driving circuit, a voltage reference array and a voltage comparator array, wherein an output port of the adjustable reference source control circuit is connected with an input port of the voltage reference array, an output port of the voltage reference array is respectively connected with an input end of the voltage comparator array and an FPGA, and an output port of the linear driving circuit is connected with an input end of the voltage comparator array.

As another preferred scheme, the adjustable reference source control circuit of the invention includes an AD/DC _ POW chip U44, wherein pin 1 of U44 is connected to a commercial power L, pin 2 of U44 is connected to a commercial power N, pin 3 of U44 is respectively connected to +15VA, one end of a capacitor C126, an anode of a capacitor C127, one end of a resistor R307, and a collector of an NPN triode Q17, the other end of R307 is respectively connected to a base of Q17 and a collector of an output end of an optocoupler OP3, an emitter of the output end of the optocoupler OP3 is respectively connected to the other end of the capacitor C126, a cathode of the capacitor C127, pin 4 of U44, one end of the resistor R309; an emitter of the Q17 is respectively connected with the other end of the resistor R309 and VRE _1 through a resistor R308;

the anode of the input end of OP3 is respectively connected with one end of a resistor R305 and one end of a resistor R306, the other end of R305 is respectively connected with the anode of a capacitor C123, one end of a capacitor C122 and +15VA, the other end of C122 is respectively connected with GND, the cathode of C123, the pin 2 of a TL431 chip U46, the pin 3 of an X9C103 chip U45, the pin 4 of U45, one end of a capacitor C124 and one end of a capacitor C125; the other ends of C124 and C125 are respectively connected with 8 feet, +3.3V of U45, and 7, 2 and 1 feet of U45 are respectively connected with J12, J14 and J15; the 5 pins of U45 are connected with the 1 pin of U46 and the other end of R306, and the 3 pin of U46 is connected with the cathode of OP3 input terminal.

As another preferable scheme, the voltage reference array comprises a resistor R, one end of the resistor R is connected with VRE _1, the other end of the resistor R is connected with a resistor R, R to R, R to 80, R to 92, R102 to 104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, R149, R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R185, R190, R191, R196, R197, R202 and R203 are connected with a5 pin of an X9C103 chip U, a3 pin of U is respectively connected with a4 pin of V, RE _1, U, one end of a capacitor C, one end of the capacitor C, the other end of the capacitor C is connected with a +3 pin of U, a C +3, a pin of U +3, a capacitor C + 8, a C + 7, a pin of the capacitor C + 7, a C +1, a pin of the capacitor C + L, a capacitor C.

As another preferable scheme, the voltage comparator array of the invention comprises MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, and U17, wherein 4 pins of U1 to U17 are respectively connected with the positive electrode of a capacitor C17, one end of a capacitor C18, and +5V, and 11 pins of U1 to U17 are respectively connected with the negative electrode of a capacitor C17, the other end of a capacitor C18, and GND;

pins

3, 5, 12 and 10 of U1-U17 are connected with ADC0, pins 9 of U1-U17 are correspondingly connected with V15 and V30-V16 respectively, pins 13 of U1-U17 are correspondingly connected with V31 and V14-V0 respectively, pins 6 of U1-U17 are correspondingly connected with V47-V32 respectively, and pins 2 of U1-U17 are correspondingly connected with V63-V48 respectively;

pins 8 of U1-U17 are correspondingly connected with K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16 and F14 through 1K resistors respectively, and K2, F3, D2, D1, G5, F2, F1, G2, G1, G16, G15, F13, F16, F15, B16 and F14 are connected with GND through 2K resistors respectively;

the 14 pins of U1-U17 are correspondingly connected with C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5 and B1 through 1K resistors respectively, and C2, K1, L2, L1, L3, N2, N1, K5, L4, R1, P2, P1, D4, E5, F5 and B1 are connected with GND through 2K resistors respectively;

pins 7 of U1-U17 are correspondingly connected with D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11 and R12 through 1K resistors respectively, and D16, D15, G11, C16, C15, R9, T9, K9, L9, M9, N9, R10, T10, R11, T11 and R12 are connected with GND through 2K resistors respectively;

the 1 legs of U1-U17 are respectively connected with T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11 and N12 through 1K resistors, and T12, K10, L10, P9, P11, R13, T13, M10, N11, T14, T15, R14, P14, L11, M11 and N12 are respectively connected with GND through 2K resistors.

As another preferable scheme, the linear driving circuit comprises a MOSFET-N tube Q21, a drain of Q21 is respectively connected with an ADC0, a cathode of a voltage regulator tube ZD2, and a cathode of a diode D9, a source of Q21 is respectively connected with GND, a cathode of ZD2, one end of a capacitor C16, one end of a secondary side of a current transformer T3, the other end of the secondary side of T3 is respectively connected with one end of a capacitor C15 and an anode of D9, and the other end of C15 is respectively connected with the other end of C16 and FG;

+15VA is respectively connected with one end of a capacitor C121, the anode of a capacitor C120 and one end of a resistor R304, the other end of R304 is respectively connected with one end of a resistor R303 and the anode of the input end of an optical coupler OP2, the cathode of the input end of the optical coupler OP2 is connected with the 3 pin of a TL431 chip U43, the 2 pin of U43 is respectively connected with GND, the other end of the capacitor C121, the cathode of the capacitor C120, the 3 pin of an X9C103 chip U42, the 4 pin of U42, one end of a capacitor C99 and one end of a capacitor C98, the 1 pin of U43 is respectively connected with the other end of the resistor R303 and the 5 pin of U42, the 1 pin, the 2 pin and the 7 pin of U42 are respectively correspondingly connected with J13, J2 and J1, and the 8 pin of;

l is connected with pin 1 of AD/DC _ POW chip U41, pin 2 of U41 is connected with N, pin 3 of U41 is respectively connected with +15VA, one end of capacitor C97, positive electrode of capacitor C96, one end of resistor R302 and collector of NPN triode Q16, the other end of R302 is respectively connected with base of Q16 and collector of output end of OP2, emitter of output end of OP2 is respectively connected with pin 4 of U41, the other end of C97, negative electrode of C96, one end of resistor R300 and GND, the other end of R300 is respectively connected with Q21_ G and one end of resistor R301, and the other end of resistor R301 is connected with emitter of Q16.

As another preferred scheme, the driving circuit of the invention includes KP103 chips U21, U28, U36, U38, pin 4 of U21 connected to +15V, U21 connected to GND, pin 2 of U21 connected to one end of resistor R214 and one end of capacitor C26, the other end of C26 connected to the other end of R214 at +15V, pin 3 of U21 connected to collector of transistor Q9 of S8050, base of Q9 connected to one end of resistor R222 and one end of resistor R223, the other end of R222 connected to A3, and the other end of R223 connected to GND and emitter of Q9; a pin 13 of U21 is connected with a cathode at an input end of an optocoupler U26 through a resistor R224, an anode at an input end of U26 is connected with a pin 18 of U21, an emitter at an output end of U26 is connected with A8, a collector at an output end of U26 is connected with +3.3V, a pin 17 of U21 is respectively connected with one end of a resistor R213, one end of a bidirectional voltage stabilizing diode ZD4 and Q4_ S, pins 16 and 15 of U21 are connected with one end of a resistor R212, the other end of the R212 is respectively connected with the other end of the R213, the other end of ZD4 and Q4_ B, a pin 12 of U21 is connected with an anode of a diode D36;

a5 pin of a4 pin of U28, which is connected with +15V, U28, is connected with GND, a2 pin of U28 is connected with one end of a resistor R233 and one end of a capacitor C57, the other end of C57 is connected with the other end of R233 and +15V, a3 pin of U28 is connected with a collector of an S8050 triode Q12, a base of Q12 is connected with one end of a resistor R238 and one end of a resistor R239, the other end of R238 is connected with B3, and the other end of R239 is connected with GND and an emitter of Q12; a pin 13 of U28 is connected with a cathode of an input end of a U32 optocoupler through a resistor R240, an anode of an input end of U32 is connected with a pin 18 of U28, an emitter of an output end of U32 is connected with B8, a collector of an output end of U32 is connected with +3.3V, a pin 17 of U28 is respectively connected with one end of a resistor R232, one end of a bidirectional voltage stabilizing diode ZD6 and Q5_ S, pins 16 and 15 of U28 are connected with one end of a resistor R230, the other end of R230 is respectively connected with the other end of R232, the other end of ZD6 and Q5_ B, a pin 12 of U28 is connected with an anode of a diode D13 through;

a5 pin of a4 pin of U36, which is connected with +15V, U36, is connected with GND, a2 pin of U36 is connected with one end of a resistor R246 and one end of a capacitor C64, the other end of C64 is connected with the other end of R246 and +15V, a3 pin of U36 is connected with a collector of a triode Q13 of S8050, a base of Q13 is connected with one end of a resistor R248 and one end of a resistor R247, the other end of R247 is connected with C3, and the other end of R248 is connected with GND and an emitter of Q13; a pin 13 of U36 is connected with a cathode of an input end of an optocoupler U37 through a resistor R249, an anode of an input end of U37 is connected with a pin 18 of U36, an emitter of an output end of U37 is connected with C8, a collector of an output end of U37 is connected with +3.3V, a pin 17 of U36 is respectively connected with one end of a resistor R245, one end of a bidirectional voltage stabilizing diode ZD7 and PGND, pins 16 and 15 of U36 are connected with one end of a resistor R244, the other end of R244 is respectively connected with the other end of R245, the other end of ZD7 and Q6_ B, a pin 12 of U36 is connected with an anode of a diode D14 through;

a5 pin of a4 pin of U38 is connected with +15V, U38 and connected with GND, a2 pin of U38 is connected with one end of a resistor R261 and one end of a capacitor C87 respectively, the other end of C87 is connected with the other end of R261 and +15V respectively, a3 pin of U38 is connected with a collector of a triode Q14 of S8050, a base of Q14 is connected with one end of a resistor R265 and one end of a resistor R266 respectively, the other end of R265 is connected with D3, and the other end of R266 is connected with an emitter of GND and Q14 respectively; the pin 13 of U38 connects the negative pole of the input end of the optical coupler U40 through the resistance R267, the positive pole of the input end of U40 connects the 18 pin of U38, the emitter of the output end of U40 connects D8, the collector of the output end of U40 connects +3.3V, the pin 17 of U38 connects one end of resistance R260, one end of the bidirectional voltage stabilizing diode ZD8, PGND separately, the pin 16, 15 of U38 connects one end of resistance R259, the other end of R259 connects the other end of R260, another end of ZD8, Q7_ B separately, the pin 12 of U38 connects the positive pole of diode D15 through the voltage stabilizing diode, the negative pole of D15 connects Q5.

As another preferable scheme, the driving circuit of the invention includes KP103 chips U20, U27, pin 4 of U20 is connected to pin 5 of +15V, U20 and GND, pin 2 of U20 is connected to one end of resistor R211 and one end of capacitor C25, the other end of C25 is connected to the other end of R211 and +15V, pin 3 of U20 is connected to collector of transistor Q8 of S8050, base of Q8 is connected to one end of resistor R217 and one end of resistor R218, the other end of R217 is connected to U33_ PA6, and the other end of R218 is connected to emitters of GND and Q8; a pin 13 of U20 is connected with a cathode of an input end of an optocoupler U25 through a resistor R219, an anode of an input end of U25 is connected with a pin 18 of U20, an emitter of an output end of U25 is connected with U33_ PA7, a collector of an output end of U25 is connected with +3.3V, a pin 17 of U20 is respectively connected with one end of a resistor R210, one end of a bidirectional voltage stabilizing diode ZD3 and Q2_ S, pins 16 and 15 of U20 are connected with one end of a resistor R209, the other end of R209 is respectively connected with the other end of R210, the other end of ZD3 and Q2_ B, a pin 12 of U20 is connected with an anode of a diode D10 through;

a pin 5 of a pin 4 of U27 connected with +15V, U27 is connected with GND, a pin 2 of U27 is connected with one end of a resistor R229 and one end of a capacitor C54 respectively, the other end of C54 is connected with the other end of R229 and +15V respectively, a pin 3 of U27 is connected with a collector of a triode Q11 of S8050, a base of Q11 is connected with one end of a resistor R234 and one end of a resistor R235 respectively, the other end of R234 is connected with U33_ PA4, and the other end of R235 is connected with emitters of GND and Q11 respectively; a pin 13 of U27 is connected with a cathode of an input end of an optocoupler U31 through a resistor R236, an anode of an input end of U31 is connected with a pin 18 of U27, an emitter of an output end of U31 is connected with U33_ PA5, a collector of an output end of U31 is connected with +3.3V, a pin 17 of U27 is respectively connected with one end of a resistor R228, one end of a bidirectional voltage stabilizing diode ZD5 and Q1_ S, pins 16 and 15 of U27 are connected with one end of a resistor R225, the other end of R225 is respectively connected with the other end of R228, the other end of ZD5 and Q1_ B, a pin 12 of U27 is connected with an anode of a diode D12 through;

12-pin U33_ PA6 of the STM32F030F4 chip U33, 13-pin U33_ PA7 of the STM32F030F4 chip U33, 10-pin U33_ PA4 of the STM32F030F4 chip U33, and 11-pin U33_ PA5 of the STM32F030F4 chip U33;

a pin 1 of the U33 is connected with GND through a resistor R250, a pin 1 of a four-pin plug-in P5 is respectively connected with +3.3V and one end of a capacitor C90, the other end of C90 is respectively connected with GND and a pin 4 of P5, and pins 2 and 3 of P5 are respectively correspondingly connected with

pins

19 and 20 of U33;

the capacitors C100-104 are connected in parallel between +3.3V and GND.

As another preferred scheme, the driving circuit of the present invention includes an X9C103 chip U24, a pin 5 of the U24 is respectively connected to one end of a resistor R208 and a pin 1 of a TL431 chip U23, the other end of the R208 is respectively connected to one end of a resistor R207 and an anode of an input end of an optical coupler OP1, a cathode of an input end of an OP1 is connected to a pin 3 of the U23, a pin 2 of the U23 is respectively connected to GND, a pin C27 of a capacitor C28, a pin 3 of the U24, a pin 2 of the U23, a pin 4 of the U24, one end of the capacitor C29, and one end of the capacitor C30, a pin 8 of the U24 is respectively connected to +3.3V, the other end of the capacitor C29, and the other end of the capacitor C30, and a

1, 2 and a pin 7 of the U24 are respectively connected to a pin 34_ PA4, a pin U34_ PA5, a pin 5 and a;

a pin 1 of the AD/DC _ POW chip U29 is connected with a mains supply L, a pin 2 of the U29 is connected with a mains supply N, a pin 3 of the U29 is respectively connected with +15V, one end of a capacitor C59, the anode of a capacitor C60, one end of a resistor R231 and the collector of an NPN triode Q10, the other end of the R231 is respectively connected with the base of a Q10 and the collector of the output end of an OP1, the emitter of the output end of an OP1 is respectively connected with a pin 4 of the U29, the other end of the C59, the cathode of the C60, one end of a resistor R237 and Q3_ S, the other end of the R237 is respectively connected with a Q3_ B;

10, 11 and 12 of an STM32F030F4 chip U34 are correspondingly connected with U34_ PA4, U34_ PA5 and U34_ PA6 respectively, 1 of the U34 is connected with GND through a resistor R251, 1 pin of a four-corner plug P6 is connected with one end of a +3.3V capacitor C91 respectively, the other end of the C91 is connected with 4 pin and GND of the P6 respectively, and 2 pin and 3 pin of the P6 are correspondingly connected with U34_ TMS and U34_ TCK respectively;

the capacitors C105-109 are connected in parallel between +3.3V and GND.

As another preferable scheme, the invention further comprises an input alternating current zero-crossing capturing circuit, wherein the input alternating current zero-crossing capturing circuit comprises a second secondary side of a transformer T1, one end of the second secondary side of T1 is connected with the anode of the input end of the optical coupler U49 through a diode D3 and a resistor R1 in sequence, the cathode of the input end of U49 is connected with the center tap of the second secondary side of T1 and the cathode of the input end of the optical coupler U50 in sequence, and the anode of the input end of U50 is connected with the other end of the second secondary side of T1 through a resistor;

the collector of the output end of the U49 is connected with +3.3V, the emitter of the output end of the U49 is connected with U33_ PB1, the emitter of the output end of the U50 is connected with U33_ PB2, and the collector of the output end of the U50 is connected with + 3.3V.

As another preferable scheme, the RS485 bus first monitoring portion of the present invention includes an SP3485 chip U39, a pin 1 of U39 connected to U33_ PA3, pins 2 and 3 of U39 connected to U33_ PA1, a pin 4 of U39 connected to U33_ PA2, pins 5 to 8 of U39 respectively connected to GND, a, B, and +3.3V, two ends of a resistor R263 are respectively connected to B, GND, and two ends of a resistor R264 are respectively connected to a and + 3.3V.

As another preferable scheme, the RS485 bus second monitoring portion of the present invention includes an SP3485 chip U35, a pin 1 of U35 connected to U34_ PA3, pins 2 and 3 of U35 connected to U34_ PA1, a pin 4 of U35 connected to U34_ PA2, and pins 5, 6, 7, and 8 of U35 connected to GND, a, B, and +3.3V, respectively;

two ends of the resistor R242 are respectively connected with B, GND, and two ends of the resistor R243 are respectively connected with A and + 3.3V.

As another preferable scheme, the invention further comprises a voltage sensor circuit, wherein the voltage sensor circuit comprises an HBV10A3.3 chip VP1, a pin 1 of VP1 is connected with Q3_ S through resistors R216 and R215 in sequence, a pin 2 of VP1 is connected with PGND through resistors R221 and R220 in sequence, and pins 4, 5 and 6 of VP1 are correspondingly connected with U43_ PA7, GND and +3.3V respectively;

one end of the resistor R227 is respectively connected with one end of the U34_ PA7 and one end of the capacitor C58, and the other end of the R227 is respectively connected with the other ends of GND and C58.

The invention relates to a single-phase packing power supply induction heating power circuit; meanwhile, the use effect and the functionality of the outdoor induction heating power supply are improved through the mutual matching of the parts.

Drawings

The invention is further described with reference to the following figures and detailed description. The scope of the invention is not limited to the following expressions.

FIG. 1 is a schematic diagram of the operation of the present invention

Fig. 2 and 3 are schematic diagrams of the main power circuit of the invention.

FIGS. 4-11 and 18 are schematic diagrams of a first monitoring part of an RS485 bus, a second monitoring part of the RS485 bus, a voltage sensor circuit and a driving circuit according to the invention.

FIGS. 12-14 are schematic diagrams of the main processor circuit of the present invention.

FIGS. 15 to 17 are schematic diagrams of the current collecting part of the circuit of the present invention.

FIGS. 19-24 are schematic diagrams of FPGA circuits of the present invention.

Detailed Description

As shown in figure 2, the heating body is formed by winding a sucker rod (1), an oil pipe (2) and a high-frequency wire (3) according to the direction (4), winding the high-frequency wire on a fixed high-temperature shell (5), connecting the wires by a high-power quick-connection high-temperature plug (9), distributing magnetic force lines according to the direction (6), and forming the whole heating body by current directions according to the directions (7) and (8).

As shown in fig. 2-24, the present invention includes a main processor, an FPGA, a power main circuit, a current collection portion, a first monitoring portion of an RS485 bus, a second monitoring portion of the RS485 bus, and a driving circuit, wherein a control signal input port of the driving circuit is connected to a control signal output port of the main processor, a signal transmission port of the driving circuit is connected to a signal transmission port of the FPGA, and a control signal output port of the driving circuit is connected to a control signal input port of the power main circuit;

The main processor adopts an STM32H743IIT6 ARM processor U5, pins 158, 148, 135, 126, 113, 102, 90, 71, 61, 22 and 14 of U5 are grounded, and pins 172, 159, 149, 136, 127, 114, 103, 91, 82, 72, 62, 49, 36, 23 and 15 of U5 are connected with + 3.3V;

a pin 1 of a SP3485 chip U60 is connected with a pin U5_ PA3, pins 2 and 3 of the U60 are connected with a pin U5_ PA1, a pin 4 of the U60 is connected with a pin U5_ PA2, and pins 5-8 of the U60 are respectively connected with GND, A and B (A and B are internal RS485 buses and are used for connecting FPAG and a processor, the main processor U5 controls other microprocessors and FPGA to work in a coordinated mode through RS 485) and +3.3V correspondingly, resistors R290 are respectively connected with B, GND, and resistors R291 are respectively connected with A and + 3.3V;

a pin 1 of a chip U64 of SP3485 is connected with a pin U5_ PA10, pins 2 and 3 of U64 are connected with a pin U5_ PA8, a pin 4 of U64 is connected with a pin U5_ PA92, pins 5, 6, 7 and 8 of U64 are correspondingly connected with GND, A, B and +3.3V respectively, resistors R292 are connected with B, GND respectively, and resistors R293 are connected with A and +3.3V respectively; the thermocouple is used for measuring the temperature of the workpiece to be processed according to the feedback value of the thermocouple; when the temperature is higher, the U33 is controlled through an RS485 internal bus so as to control the conduction time of Q1 and Q2; reducing the voltage of the input end; thereby reducing the heating power of the whole machine and reducing the temperature rise of the workpiece, and vice versa.

the capacitors C85 and C69-C82 are connected between +3.3V, GND in parallel;

The pin 171 of U5 is connected with the pin 37 of U5, one end of a capacitor C43, one end of a capacitor C44 and GND through a resistor R5, the other end of C43 is connected with the pin 39 of U5, the other end of C44 and one end of a resistor R4, and the other end of R4 is connected with + 3.3V;

pin 166 of U5 is connected to U5_ BOOT 0;

RESET is connected to pin 31 of U5.

The FPGA adopts H7-10, J7-10, B2, B15, C5, C12, D7, D10, E4 and E13 pins of an EP4CE10F17C8 chip U22 to be connected with GND, and G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, E2, H16 and H15 pins of U22 are connected with GND;

pins

The L5 pin of U22 is connected with +2.5V, the N4 pin of U22 is connected with +1.2V, the F12 pin of U22 is connected with +2.5V, the D13 pin of U22 is connected with +1.2V, and the E12 pin and the M5 pin of U22 are connected with GND;

pins

pins 6, 5, 2 and 8 of the M25P16 chip U30 are correspondingly connected with EPCS _ CLK, EPCS _ ASDO, EPCS _ DATA0 and +3.3V respectively, pin 4 of U30 is connected with GND, pins 3 and 7 of U30 are connected with +3.3V, and pin 1 of U30 is connected with EPCS _ CS.

The power main circuit comprises an air switch K1, one end of a K1 is connected with a mains supply, the other end of the K1 is connected with a primary side of a transformer T1, one end of a first secondary side of the T1 is respectively connected with a cathode of a diode D1, a drain of an IGBT Q2 and a Q2_ D, an anode of the D1 is respectively connected with a source of the IGBT Q1 and a Q1_ S, a gate of the Q1 is connected with a Q1_ B, a drain of the Q1 is respectively connected with a Q1_ D, a cathode of a diode D2 and a pin 1 of a common-mode inductor L2, an anode of the D2 is respectively connected with a source of the Q2 and the Q2_ S, a gate of the Q2 is connected with a Q2_ B, and a pin 3 of;

The Q4, Q5, Q6 and Q7 can adopt IGBTs of model FZ800R33KF 2C.

In the figure, the parts D1, Q1, D2, Q2 and U33 form a voltage-reducing power regulating circuit, can be flexibly switched on at the zero crossing point of each alternating current period, and can be switched off before reaching or approaching 90 degrees, and can be switched on for the second time after exceeding 90 degrees and before reaching 180 degrees, so that the current impact on the highest potential point of a power grid is greatly reduced; the power factor of the device is greatly improved.

As shown, the T1B winding 35T and the T1A winding 165T boost the single-phase 220V alternating current to 1100V.

The input end of the circuit has a filter capacitor with huge capacity, and the power on the input end of the circuit is similar to a short circuit instantly due to the characteristic of the capacitor, so that the current impact on a front-end rectifier bridge is extremely large, and even the rectifier bridge is broken down. The high-power NPN triode Q3 is arranged between a rectifier bridge and an input filter capacitor, and works in a cut-off region before being electrified; at the moment, the current of the rectifier bridge is 0; after the system is powered on, the voltage of the capacitor end is detected through a microprocessor;

when the system is powered on for the first time, the power supply of the whole microprocessor part is supplied by converting AC220 into DC15, and the whole microprocessor starts to work in preference to the main circuit part. When the self-test of the U5 system is successful, the U34 detects that the voltage of Q3_ S to PGND is lower than 30V through a VP1 voltage sensor, the voltage is sent to a U34 microprocessor and enters a main circuit starting state, when the voltage of Q3_ S to PGND is detected to be lower than 30V (the voltage of Q3_ S to PGND is C1, C2, C3, C4, C9, C10, C11 and C12 filter capacitor terminal), the surge prevention starting is judged to be necessary, and Q3 which works in an amplification area (Q3 and the filter capacitor group are in series connection) is controlled to limit the magnitude of charging current of the capacitor group through the magnitude of IB current, so that the front end circuit is prevented from being damaged by surge.

Wherein the control function for the IB current is:

if(VP1<(220*1.414)/0.75){IB = 0.67mA}else{IB = 1.5A};

the triode Q3 is controlled by the driving circuit to slowly enter the amplification region from the cut-off region, and the current of the rectifier bridge is always limited within the safety range because the triode working in the amplification region is involved; when the voltage of the filter capacitor slowly rises; after 75% of rated voltage is reached; the anti-surge triode Q3 enters an amplification area to fulfill the aim of preventing surge current for one time. Because the anti-surge working time is very short, and when the surge working is not finished, the H-bridge resonant circuit (Q4-Q7) does not work, and the heat dissipation device does not generate temperature rise; therefore, the high-power transistor Q3 and the H-bridge IGBT share the same heat sink and do not need to increase the volume of the original heat sink.

The current acquisition part comprises an adjustable reference source control circuit, a linear driving circuit, a voltage reference array and a voltage comparator array, wherein an output port of the adjustable reference source control circuit is connected with an input port of the voltage reference array, an output end of the voltage reference array is respectively connected with an input end of the voltage comparator array and an FPGA, and an output port of the linear driving circuit is connected with an input end of the voltage comparator array.

The adjustable reference source control circuit comprises an AD/DC _ POW chip U44, wherein a pin 1 of U44 is connected with a mains supply L, a pin 2 of U44 is connected with a mains supply N, a pin 3 of U44 is respectively connected with +15VA, one end of a capacitor C126, a positive electrode of the capacitor C127, one end of a resistor R307 and a collector of an NPN triode Q17, the other end of R307 is respectively connected with a base electrode of Q17 and a collector of an output end of an optical coupler OP3, and an emitter of the output end of the optical coupler OP3 is respectively connected with the other end of the capacitor C126, a negative electrode of the capacitor C127, a pin 4 of the U44; an emitter of the Q17 is respectively connected with the other end of the resistor R309 and VRE _1 through a resistor R308;

The voltage reference array comprises a resistor R, one end of the resistor R is connected with VRE _1, the other end of the resistor R is connected with a resistor R, R-R, R-80, R-92, R102-104, R109, R110, R115, R116, R122, R123, R129, R130, R136, R137, R142, R143, R148, R149, R154, R155, R160, R161, R166, R167, R172, R173, R178, R179, R184, R185, R190, R191, R196, R197, R202 and R203 respectively connected with a pin 5 of an X9C chip U, a pin 3 of U is respectively connected with a pin 4 of RE _1 and U, one end of a capacitor C and one end of the capacitor C, the other end of the capacitor C is respectively connected with a pin 8 of +3.3, a pin of the capacitor C, a pin 103, a pin 7, a pin of the other end of the capacitor C, a corresponding GND, a pin, a corresponding L, a pin.

The voltage comparator array comprises MAX9140 chips U1, U2, U3, U4, U5, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16 and U17, wherein 4 pins of the U1-U17 are respectively connected with the anode of a capacitor C17 and one end, +5V of the capacitor C18, and 11 pins of the U1-U17 are respectively connected with the cathode of the capacitor C17, the other end of the capacitor C18 and GND;

pins 3, 5, 12 and 10 of U1-U17 are connected with ADC0, pins 9 of U1-U17 are correspondingly connected with V15 and V30-V16 respectively, pins 13 of U1-U17 are correspondingly connected with V31 and V14-V0 respectively, pins 6 of U1-U17 are correspondingly connected with V47-V32 respectively, and pins 2 of U1-U17 are correspondingly connected with V63-V48 respectively;

The linear driving circuit comprises a MOSFET-N tube Q21, the drain electrode of Q21 is respectively connected with an ADC0, the cathode of a voltage regulator tube ZD2 and the cathode of a diode D9, the source electrode of Q21 is respectively connected with GND, the cathode of ZD2, one end of a capacitor C16 and one end of the secondary side of a current transformer T3, the other end of the secondary side of T3 is respectively connected with one end of the capacitor C15 and the anode of D9, and the other end of C15 is respectively connected with the other end of C16 and FG;

The current on the output side is collected by a T3A electromagnetic mutual inductance type current sensor, and the current is induction heating load current. The invention collects the current of the output side at high speed through a reference array circuit, a voltage comparator array circuit, a bottom layer variable reference voltage circuit and an FPGA circuit; the high-speed conversion rate of the electromagnetic mutual inductance type current sensor circuit is utilized to convert the current at the output side into a voltage signal in proportion, and the waveform shape and the current true effective value of the actual current are completely restored and stored and are provided to the main processor U5.

The U5 is configured with U5 peripheral after normal start, and accesses RS485 internal bus through U63, and establishes communication connection with microprocessor U33 through U39, and obtains the start state of U33. The U35 is used for establishing communication connection with the microprocessor U34 to acquire the starting state of the U34. The starting state of a U22 Field Programmable Gate Array (FPGA) is obtained through U65.

The U5 controls the U33 to enter a 50% voltage regulation state through an internal RS485 bus, and controls the U34 to enter an anti-surge starting work. U5 communicates with too much U34 to determine the end of the surge protection initiation. The U5 establishes communication with U65 and U22 (FPGA) through an internal RS485 bus, and outputs four paths of H bridge driving signals through U22; an H-bridge circuit (Q4, Q5, Q6 and Q7) is driven by U21, U28, U36 and U38 isolation IGBT driving chips; and performing frequency sweeping. After the U5 obtains the information of the completion of the U22 frequency sweep through an internal RS485 bus; through RS485 bus; controlling the U33 to perform 100 turning states; and carrying out full power output.

U5 obtains the temperature value measured by the external point-checking thermocouple through U64 in the control cycle; and the output power is controlled by the self-tuning PID control U33 voltage regulation value, so that the temperature of the heating workpiece is controlled to accord with the set value of constant temperature. The U22 micro-adjusts the working frequency of the H bridge, so that the whole machine always works at a resonance point with the heating workpiece. If a suitable resonance point is not found during the fine tuning (e.g., the workpiece is heated to curie temperature), the U22 will re-sweep from the lowest frequency to the highest frequency supported by the apparatus to obtain a new resonance point, and continue operating at the new resonance point.

The current acquisition part of the invention comprises a 64-bit voltage division circuit consisting of 63 voltage division resistors and a digital adjustable resistor; the voltage comparator array is composed of 64 ultra-high speed voltage comparisons.

The Q21 works in a variable resistance area to serve as a current-to-voltage circuit, and the T3 electromagnetic mutual inductance type current sensor passes through a formula N1, N2= V1, V2=1/A1:1/A2, the output current of the T3B end of the available mutual inductance type current sensor is a T3A end 1/5000, and the output current is according to ohm's law U = I R; the Q21 works in the variable resistance region through the U22 control; its resistance value of Q21 can change dynamically; the current of T3B is moderate within the sensitive range of its back end sampling array.

The current is collected and passes through a mutual inductor, a rectifying circuit and a resistor to convert the current at the output end into a voltage signal.

Obtaining a current signal with the same current characteristic as the output current and reduced in proportion through a current transformer; the current signal is converted into a voltage signal through a Q21 field effect transistor working in a variable resistance area, the voltage signal is loaded to the in-phase end of a 64-bit voltage comparator through a voltage reference array consisting of a bottom layer variable reference source and a 63-bit divider resistor, and the output end of the voltage comparator is connected to the FPGA. The resistance value of the Q21 in the variable resistor area is controlled by the FPGA through a linear driving circuit, and the resistance value of the bottom-layer reference source of the resistor divider array is driven by the FPGA.

As a result of current-voltage conversion of the mutual inductance type current sensor, the voltage value of VER _1 can be increased proportionally by the resistance of the mutual inductance type current sensor to the ground, namely, the larger the resistance is, the higher the voltage is, and vice versa. When the measured current is larger; the equivalent resistance value of the Q21 field effect transistor in the variable resistor can be reduced to the sensitive range of the back-end acquisition circuit by adjusting the Q21 field effect transistor; similarly, if the measured current is small, the equivalent resistance value of the variable resistance region of the Q21 field effect transistor can be increased to be within the sensitivity range of the rear-end acquisition circuit by adjusting the Q21 field effect transistor, so as to obtain the optimal acquisition precision. The bottom layer variable reference of the resistance voltage division array has the function that when a certain range of the current value to be measured needs high-precision measurement, the voltage reference of the bottom layer is adjusted to the minimum value of the required measurement range to be used as a threshold value for starting the detection range, and the residual range is used as a high-resolution detection range of 63 bits. For example when measuring some 50A high frequency current; measuring the measurement range between 45A and 55A by adjusting the bottom layer variable reference and the inverted input end reference of the voltage comparator array; the accuracy of detecting the current value is improved.

The driving circuit comprises KP103 chips U21, U28, U36, U38, the 5 pin of the 4 pin of U21 +15V, U21 is connected with GND, the 2 pin of U21 is connected with one end of a resistor R214 and one end of a capacitor C26 respectively, the other end of C26 is connected with the other end of R214, +15V respectively, the 3 pin of U21 is connected with the collector of a triode Q9 of S8050, the base of Q9 is connected with one end of a resistor R222 and one end of a resistor R223 respectively, the other end of R222 is connected with A3, and the other end of R223 is connected with the emitters of GND and Q9 respectively; a pin 13 of U21 is connected with a cathode at an input end of an optocoupler U26 through a resistor R224, an anode at an input end of U26 is connected with a pin 18 of U21, an emitter at an output end of U26 is connected with A8, a collector at an output end of U26 is connected with +3.3V, a pin 17 of U21 is respectively connected with one end of a resistor R213, one end of a bidirectional voltage stabilizing diode ZD4 and Q4_ S, pins 16 and 15 of U21 are connected with one end of a resistor R212, the other end of the R212 is respectively connected with the other end of the R213, the other end of ZD4 and Q4_ B, a pin 12 of U21 is connected with an anode of a diode D36;

U21, U28, U36 and U38 are used for driving IGBTs Q4-Q7, and PMM signals or high-low level signals output by a microprocessor U22 or FPGA pass through the circuit; and converting the current into a signal with driving power above the current 9A of positive 15V negative 9V (high level corresponds to +15V to turn on the IGBT, and low level corresponds to-9V to turn off the IGBT) with the same phase, the same frequency and the same pulse width, and connecting the signal with the IGBT controller to turn on and turn off. KP103 has the function of rapidly turning off the IGBT for protection when the IGBT passes through zero.

The overcurrent signal of the Q1 is fed back to the microprocessor U33_ PA7 through the

pins

18 and 13 of the U27 and the U31.

The overcurrent signal of the Q2 is fed back to the microprocessor U33_ PA5 through the

pins

18 and 13 of the U20 and the U25.

The overcurrent signal of the Q4 is fed back to the microprocessor U22_ A8 through the

pins

18 and 13 of the U21 and the U26.

The overcurrent signal of the Q5 is fed back to the microprocessor U22_ B8 through the

pins

18 and 13 of the U28 and the U32.

The overcurrent signal of the Q6 is fed back to the microprocessor U22_ C8 through the

pins

18 and 13 of the U36 and the U37.

The overcurrent signal of the Q7 is fed back to the microprocessor U22_ D8 through the U40 through

pins

18 and 13 of the U38.

The USART3 (synchronous asynchronous serial communication) port of the U5 main processor circuit is connected with U63, U63 is connected to an RS485 bus inside the whole machine, and U5 is connected to the RS485 bus in a host mode of the RS485 bus inside.

An NIOS _ II soft core and an asynchronous serial communication soft core are established in the FPGA (U22) through software, the NIOS _ II soft core and the asynchronous serial communication soft core are connected to the U65 through B4, D5 and D6 of PIO, the NIOS _ II soft core is connected to an RS485 bus in the whole machine through U65, and the U22 is used as an internal RS485 slave mode to be connected to the RS485 bus.

The U22 FPGA is a high-speed H bridge driving signal module established by FPGA hardware units written in Verilog HDL language.

The driving circuit comprises KP103 chips U20 and U27, a5 pin of a4 pin of U20 and +15V, U20 is connected with GND, a2 pin of U20 is respectively connected with one end of a resistor R211 and one end of a capacitor C25, the other end of C25 is respectively connected with the other end of R211 and +15V, a3 pin of U20 is connected with a collector of an S8050 triode Q8, a base of Q8 is respectively connected with one end of a resistor R217 and one end of a resistor R218, the other end of R217 is connected with a U33_ PA6, and the other end of R218 is respectively connected with an emitter of GND and Q8; a pin 13 of U20 is connected with a cathode of an input end of an optocoupler U25 through a resistor R219, an anode of an input end of U25 is connected with a pin 18 of U20, an emitter of an output end of U25 is connected with U33_ PA7, a collector of an output end of U25 is connected with +3.3V, a pin 17 of U20 is respectively connected with one end of a resistor R210, one end of a bidirectional voltage stabilizing diode ZD3 and Q2_ S, pins 16 and 15 of U20 are connected with one end of a resistor R209, the other end of R209 is respectively connected with the other end of R210, the other end of ZD3 and Q2_ B, a pin 12 of U20 is connected with an anode of a diode D10 through;

pins

19 and 20 of U33;

the capacitors C100-104 are connected in parallel between +3.3V and GND.

The sine wave of the input unidirectional alternating current is divided into a positive half shaft, a negative half shaft and 2 steamed bread waves. Q2 is turned on and off on the positive half-axis and Q1 is turned on and off on the negative half-axis. For example, the positive half cycle of Q2 is used for positive half cycle power control, and the negative half cycle control principle is the same as that of the positive half shaft Q1, and only the control cycle is the negative half shaft of the input alternating current.

The timer overflow interrupt time is set to 1/100 times per half cycle by the interrupt of an internal timer T1 of the microprocessor, the maximum count value is two-way 50 by a two-way counter, the count value is decreased from 50 from the zero crossing point of the positive half cycle, the count value is 0 at the maximum value of the positive half cycle, then the count value is increased, and the count value is 50 by the end of the positive half cycle. Designing a voltage adjustment value of 0-50, wherein 0 is the highest voltage and 50 bits are the lowest voltage, and after the interrupt counter changes every time T1 occurs; when the adjusting value is larger than the counting value, the Q2 tube is closed, otherwise, the Q2 tube is opened. When the positive half cycle of the next cycle passes through the zero point, the switch is turned on again.

According to an RS485 communication command of U5; when the maximum power output is needed, each half period of Q2 and Q1 is switched on, and the rear-end rectifying and filtering circuit receives a complete steamed bread wave waveform; the voltage amplitude is highest.

The driving circuit comprises an X9C103 chip U24, a pin 5 of U24 is respectively connected with one end of a resistor R208 and a pin 1 of a TL431 chip U23, the other end of R208 is respectively connected with one end of a resistor R207 and the anode of the input end of an optical coupler OP1, the cathode of the input end of OP1 is connected with a pin 3 of U23, a pin 2 of U23 is respectively connected with GND, the negative electrode of a capacitor C27, the negative electrode of a capacitor C28, a pin 3 of U24, a pin 2 of U23, a pin 4 of U24, one end of a capacitor C29 and one end of a capacitor C30, a pin 8 of U24 is respectively connected with +3.3V, the other end of a capacitor C29 and the other end of a capacitor C30, pins 1, 2 and 7 of U24 are respectively connected with U34_ PA4, U34_ PA5 and U5_ PA5, and +15V are respectively connected with the other;

the capacitors C105-109 are connected in parallel between +3.3V and GND.

The U34 is respectively connected with 1 pin, 2 pins and 7 pins of the U24 through 10 pins, 11 pins and 12 pins; the U24 chip model X9C103 is a digital variable resistance chip, and the function of the chip is to change the resistance value between 5 pins and 3 pins by controlling 1 pin, 2 pins and 7 pins of the chip. The model number of the U24 chip is TL431, and the function of the U24 chip is a 2.5V reference source chip. The function of the chip is that the voltage between the pin 1 and the pin 2 of the chip is always kept at 2.5V; when the voltage is higher than 2.5V, the chip can reduce the resistance value from 3 feet to 2 feet, when the level of 2 feet is lower than 2.5V, the resistance value from 3 feet to 2 feet can be increased, and the circuit and the optical coupler are combined to form an isolation voltage sampling feedback circuit.

The microprocessor U34 controls the resistance of the pin 5 and pin 3 of U24 through 3 GPIO pins.

The resistor R208 and the

pins

5 and 3 of the U24 form a resistor divider circuit.

The primary sides of U23 and OP1 form a series circuit, and the current of the primary side of OP1 is limited by R207 and U23; wherein the resistance of R207 is fixed.

According to the characteristics of the chip TL431 of the U23, the current of the OP1 can be controlled by changing the partial pressure of the 1 pin and the 2 pin, so that the conduction depth of the OP1 secondary side phototriode is changed.

The U29 is AD220V changes DC15V power converter, this 15V power passes Q10 and R226 to the B pole of Q3, IB current of Q10 is controlled by the secondary side of OP1, when OP1 secondary side conduction depth is big, IB current of Q10 reduces vice versa, IB current of Q10 reduces, cause the entering of Q10 to the amplification zone, thus control IB current of Q3, control the operating condition of Q3. The U34 microprocessor is controlled to make Q3 work in linear region (amplification region) to protect equipment from surge.

The power supply circuit also comprises an input alternating current zero-crossing capturing circuit (the U33 acquires an input alternating current zero-crossing capturing signal, the Q1 and the Q2 are controlled to realize the voltage reduction and power regulation functions, and the U5 communicates with the U33 through RS485 to transmit a control value to the U33).

The input alternating current zero-crossing capturing circuit comprises a second secondary side of a transformer T1, one end of the second secondary side of a T1 is connected with the anode of the input end of an optical coupler U49 through a diode D3 and a resistor R1 in sequence, the cathode of the input end of the U49 is connected with a center tap of the second secondary side of the T1 and the cathode of the input end of an optical coupler U50 in sequence, and the anode of the input end of a U50 is connected with the other end of the second secondary side of the T1 through a resistor;

The RS485 bus first monitoring part comprises an SP3485 chip U39, a pin 1 of U39 is connected with U33_ PA3, pins 2 and 3 of U39 are connected with U33_ PA1, a pin 4 of U39 is connected with U33_ PA2, pins 5-8 of U39 are correspondingly connected with GND, A, B and +3.3V respectively, two ends of a resistor R263 are connected with B, GND respectively, and two ends of a resistor R264 are connected with A and +3.3V respectively.

And the microprocessor (U33) and the RS485 communication bus circuit are used as RS485 slaves to monitor message data on the RS485 bus at any time. And controlling the on-off time of the IGBT tubes Q1 and Q2 according to a command sent by an RS485 host computer on the bus to the device. The U33 program configures the internal timer TIM1 which generates a timer overflow interrupt every 100uS and disables the timer (configured but not started). An external falling edge interruption pin PB1 and a pin PB2 are arranged, a PB1 is externally connected to the secondary side of an input alternating current zero-crossing protection circuit U49, a PB2 is connected to U50, T1C and D windings are a set of voltage-reduction auxiliary windings of an alternating current input main transformer, and the windings are provided with center taps; according to the homonymous terminal relation, after the alternating current input goes to zero from the positive half cycle (the homonymous terminal is at high level), the alternating current input can go to the zero-crossing point of the negative half cycle of a rectangular wave at the secondary side (PB 1) of U49 through diodes D3 to U49; conduction of Q1 begins. And vice versa, the turn-on start time of Q2 (zero-crossing capture circuits of Q2 are D4 and U50). The falling edge obtained at the secondary side of U49 triggers the PB1 falling edge external interrupt service function of the microprocessor circuit U33; firstly, a Q1 tube is conducted in a function of the method, and a global counter COUN1 is assigned with 0; enabling a TIM1 timer, generating a TIM1 overflow interruption for one time after TIM1 is enabled, and comparing the value of the COUN1 value with the value of the transmission conduction time of the host computer on the RS485 bus after entering the service function each time; when the value of COUN1 is equal to its value; causing Q1 to turn off immediately. And disable the TIM1 timer. When the secondary half period ends, U50 secondary side will generate a falling edge; the PB2 inputs the falling edge interrupt service function at this time, and controls the Q2 on-time accordingly by count of count 1, which is implemented in the same manner as the Q1.

The second monitoring part of the RS485 bus comprises an SP3485 chip U35, a pin 1 of U35 is connected with U34_ PA3, pins 2 and 3 of U35 are connected with U34_ PA1, a pin 4 of U35 is connected with U34_ PA2, and pins 5, 6, 7 and 8 of U35 are correspondingly connected with GND, A, B and +3.3V respectively;

And the microprocessor (U34) and the RS485 communication bus circuit are used as RS485 slaves to monitor message data on the RS485 bus at any time. And correspondingly controlling the IB current of the transistor Q3 to work in an amplification region or a saturation region according to a command sent by the RS485 host computer on the bus to the computer. In the initial stage of power-on of the whole machine; q3 because the command of the host computer on the RS485 communication bus is not obtained, the microprocessor controls Q3 to work in the cut-off region, and no current flows through Q3. When the host controller U5 enters a starting mode, after the minimum circuit (U34) of the microprocessor is instructed to enter the starting mode through an RS485 communication bus, the microprocessor slowly enters an amplification region from a cut-off region by controlling IB current of Q3, and voltage between Q3_ S and PGND is detected through VP 1; when the voltage reaches 2/3(× 220 × 1.414), the Q3 is controlled to enter the saturation region, and the normal operation mode is performed. The U24, U29, U23, OP1 and peripheral circuits form a digital controllable linear driving circuit, and the resistance value between the pin 5 and pin 3 of the U24 can be controlled by the microprocessor U34 through 3-bit GPIO. When the resistance value of the pin 3 of the pin 5 of the U24 changes, the reference voltage of the pin 1 of the U23 changes, so that the resistance of the pin 2 of the pin 3 of the U23 changes, and the change of the luminous power of the primary side of the OP1 causes the influence of the secondary side on the IB of the Q10; thereby changing the IB current of Q3; the controller U34 is in the operating range and operating region of the load.

The voltage sensor circuit comprises an HBV10A3.3 chip VP1, a pin 1 of VP1 is connected with Q3_ S through resistors R216 and R215 in sequence, a pin 2 of VP1 is connected with PGND through resistors R221 and R220 in sequence, and pins 4, 5 and 6 of VP1 are correspondingly connected with U43_ PA7, GND and +3.3V respectively;

The voltage sensor VP1 collects the voltages across Q3_ S and PGND (main storage filter capacitor voltage). By taking this position voltage: input anti-surge protection, output power calculation of equipment and voltage reduction regulation and control.

It should be understood that the detailed description of the present invention is only for illustrating the present invention and is not limited by the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention can be modified or substituted equally to achieve the same technical effects; as long as the use requirements are met, the method is within the protection scope of the invention.

Claims

1. A heating power supply for oil field packing belongs to a protection device in the oil extraction process of an oil well; the device is characterized by mainly comprising a power supply circuit and a heating body, wherein the heating body is formed by winding a sucker rod (1), an oil pipe (2) and a high-frequency wire (3) in the direction of (4), winding the high-frequency wire on a fixed high-temperature shell (5), connecting the wires by a high-power quick-connection high-temperature plug (9), distributing magnetic force lines in the direction of (6), and forming the whole heating body in the directions of (7) and (8).

2. An induction heating power supply circuit for a packing comprises a main processor, an FPGA, a power main circuit, a current acquisition part, an RS485 bus first monitoring part, an RS485 bus second monitoring part and a drive circuit, and is characterized in that a control signal input port of the drive circuit is connected with a control signal output port of the main processor, a signal transmission port of the drive circuit is connected with a signal transmission port of the FPGA, and a control signal output port of the drive circuit is connected with a control signal input port of the power main circuit;

the electric energy input end of the power main circuit is connected with single-phase commercial power;

a pin 1 of a chip U60 of SP3485 is connected with a pin U5_ PA3, pins 2 and 3 of U60 are connected with a pin U5_ PA1, a pin 4 of U60 is connected with a pin U5_ PA2, pins 5-8 of U60 are correspondingly connected with GND, A, B and +3.3V respectively, a resistor R290 is connected with B, GND respectively, and a resistor R291 is connected with A and +3.3V respectively;

a pin 1 of a chip U64 of SP3485 is connected with a pin U5_ PA10, pins 2 and 3 of U64 are connected with a pin U5_ PA8, a pin 4 of U64 is connected with a pin U5_ PA92, pins 5, 6, 7 and 8 of U64 are correspondingly connected with GND, A, B and +3.3V respectively, resistors R292 are connected with B, GND respectively, and resistors R293 are connected with A and +3.3V respectively;

the capacitors C85 and C69-C82 are connected between +3.3V, GND in parallel;

3. The induction heating power supply circuit for the packing according to the claim, characterized in that the pin 171 of U5 is connected with the pin 37 of U5, one end of a capacitor C43, one end of a capacitor C44 and GND through a resistor R5, the other end of C43 is connected with the pin 39 of U5, the other end of C44 and one end of a resistor R4, and the other end of R4 is connected with + 3.3V;

the 6 pins of U5 are respectively connected with +3.3V and one end of a capacitor C36, the other end of C36 is respectively connected with GND and one end of a resistor R8, and the other end of R8 is connected with the 48 pin of U5; pin 166 of U5 is connected to U5_ BOOT 0; RESET is connected to pin 31 of U5.