CN111849735A - Chip with composite layer and application thereof in biological detection - Google Patents
Chip with composite layer and application thereof in biological detection Download PDFInfo
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- CN111849735A CN111849735A CN201910346219.XA CN201910346219A CN111849735A CN 111849735 A CN111849735 A CN 111849735A CN 201910346219 A CN201910346219 A CN 201910346219A CN 111849735 A CN111849735 A CN 111849735A
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- 238000001514 detection method Methods 0.000 title claims abstract description 18
- 239000002131 composite material Substances 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000004033 plastic Substances 0.000 claims abstract description 22
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- 239000000758 substrate Substances 0.000 claims description 29
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- 238000012163 sequencing technique Methods 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 8
- 239000009719 polyimide resin Substances 0.000 claims description 8
- 108020004707 nucleic acids Proteins 0.000 claims description 6
- 102000039446 nucleic acids Human genes 0.000 claims description 6
- 150000007523 nucleic acids Chemical class 0.000 claims description 6
- 239000011188 CEM-1 Substances 0.000 claims description 3
- 101100257127 Caenorhabditis elegans sma-2 gene Proteins 0.000 claims description 3
- 238000004166 bioassay Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 5
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
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- C—CHEMISTRY; METALLURGY
- C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
- C12Q—MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS; COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES
- C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
- C12Q1/68—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids
- C12Q1/6869—Methods for sequencing
Abstract
The invention provides a chip with a composite layer and application thereof in biological detection, wherein the chip comprises a first base layer and a second base layer which are at least arranged up and down, the first base layer is provided with at least one first blind hole leading to the second base layer, the chip is also provided with at least one metallized through hole penetrating through the second base layer, an electrode is arranged below the first blind hole, the chip is provided with a contact, and the electrode is connected with the contact through a circuit. The chip with the composite layer is developed by combining plastic and metal, the basic functions of the chip are realized by reasonably distributing the base layer, the circuit layer and the internal circuit of the chip, and the chip is simple to manufacture and low in cost.
Description
Technical Field
The invention belongs to the technical field of chips, and particularly relates to a chip with a composite layer and application thereof in biological detection.
Background
With the rapid development of electronics and information technology, China has entered the information age. The chip is used as a micro integrated circuit, is widely applied to various electronic products and systems such as computers, mobile phones, household appliances, automobiles, high-speed rails, power grids, medical instruments, robots, industrial control and the like, and is a core cornerstone of high-end manufacturing industry. The chip is composed of a base layer and a circuit, wherein the base layer is made of a monocrystalline silicon wafer, components such as a metal-oxide semiconductor field effect transistor (MOSFET) or a Bipolar Junction Transistor (BJT) are made by adopting technologies such as photoetching, doping and Chemical Mechanical Polishing (CMP), and the circuit is made by utilizing a thin film and the CMP technology, so that the chip is manufactured.
Currently, the mainstream chip base layer is monocrystalline silicon. In electronic components and chips made of silicon crystal, the carrier energy can be 0.1m2High mobility fast transport of/v.s. However, the cost of the current silicon crystal production process is very expensive, and the cost which is too high is often difficult to bear for the consumer electronics industry with huge demand, and the popularization and the use of the chip are not facilitated. Consequently, researchers are working to find and develop other inexpensive alternatives. Plastic has entered the field of scientists as a cheap, extremely plastic material. At present, the main research direction is to physically and chemically modify the insulating plastic material to make it conductive. For example, austria scientists have successfully fabricated a solar cell from plastics such as polystyrene with an efficiency of 3%; in 2011, scientists at the microelectronics research center belgium developed a plastic chip prototype; the dutch philips company has introduced a thin, light and flexible plastic computer display screen made of plastic-based semiconductors; japanese scientists have developed flexible conductive plastics containing hundreds of organic computer chips and new types of flat panel displays and electronic tags have been made using such conductive plastics. Although there have been some efforts in the research of plastic-based semiconductors or conductive plastics, there is a great gap from large-scale, low-cost applications.
At present, the packaging material of the chip generally adopts plastics and metals, and is suitable for most chip application scenes. If ordinary plastic materials can be applied to the chip base layer, the production cost of the chip is greatly reduced. However, this is a problem.
Patent CN201710699800.0 discloses an online automatic monitoring system in filthy district based on wireless remote control, and the conductance sensor of this system includes that the upper surface is corrugated insulating plastic substrate, and insulating porcelain has been plated to the upper surface of insulating plastic substrate, and insulating plastic substrate both ends respectively are provided with the metal clamping piece, and the metal clamping piece closely laminates with insulating porcelain, and metal clamping piece periphery cover has the lag, the conductance sensor still include with two the drive chip that the metal clamping piece is connected, drive chip is connected to the mainboard. The invention connects electrodes on the metal clip to realize the operation of the whole monitoring system.
In addition, the chip has important application value in the biological field, especially in the aspect of gene detection, the chip can replace the traditional laser lens, a fluorescent staining agent and the like to become a new sequencer, and the application of the multifunctional chip is the future development direction in the face of massive gene detection and analysis data. At present, the new generation gene sequencing technology utilizes nano-sized pores as sensors, detects ion current passing through each nano-pore when nucleic acid molecules pass through the nano-pores, and determines the gene sequence of each genome segment by tracking the change of the current according to the current characteristics when different bases pass through the pores. For example, patent CN201810019657.0 discloses a disposable nanopore biosensor, which comprises a substrate, an electrode layer and a top cover stacked in sequence, wherein the top cover is provided with micropores with a diameter of 5-200 μm for injecting nanopores and a phospholipid film, the substrate and the top cover are both plastic layers, the electrodes are a pair of silver electrodes arranged on the surface of the substrate, the micropores are opened on an insulating cover covering the surface of one silver electrode, and the micropores are arranged on the top of the silver electrode, so that the silver electrode is exposed only through the micropores.
Patent CN200880126160.3 discloses a method for forming a layer separating two volumes of aqueous solution, in which the upper part is a device comprising a chamber, the lower part comprises at least one body of non-conductive material opening into a recess of the chamber, a bio-layer lipid membrane (BLM) is formed between the chamber and the recess, the device has a pair of electrodes, the upper electrode is located in the chamber and leads out of the chamber, and the lower electrode is located at the lower part of the recess and leads out of the body of non-conductive material.
Along with the chip is gradually applied to nanopore gene detection, the structure of the chip is suitable for the requirement of mass gene detection, so that the structure is more reasonable, the operation is more convenient, and the functions are more various. According to the invention, a plastic material and a metal material are combined to develop the chip with the composite layer, and the basic function of the chip applied to nanopore gene detection is realized through the reasonable layout of the composite layer of the chip.
Disclosure of Invention
In order to achieve the above purpose, the present invention provides a chip with a composite layer, the chip includes at least a first base layer and a second base layer arranged up and down, the first base layer is provided with at least one first blind hole leading to the second base layer, the chip is further provided with at least one metallized via hole penetrating through the second base layer, an electrode is arranged below the first blind hole, the chip is provided with a contact, and the electrode is connected with the contact through a circuit.
The chip is characterized in that first electrodes are further arranged on the upper surface and the lower surface of the first base layer or above the first base layer, the chip is further provided with a first contact, and the first electrodes are connected with the first contact through circuits.
Preferably, the second base layer is provided with an inner layer circuit, and more preferably, the inner wall of the metalized via hole is provided with an outwardly extending inner layer circuit, and the inner layer circuit extends and is embedded into the first base layer and the second base layer to form an interconnection circuit; the interconnection circuit can extend to and connect other circuit components inside the chip, realizes interconnection of a plurality of components, and is favorable for the chip to realize multiple functions.
Preferably, at least one third base layer is further arranged between the first base layer and the second base layer. More preferably, 1-5 third base layers are arranged between the first base layer and the second base layer. For example, 1, 2, 3, 4 or 5 third base layers are further arranged between the first base layer and the second base layer.
In one form of the chip of the present invention, the first substrate is further provided with at least one second blind via leading to the second substrate, and the first electrode is disposed under the second blind via. At least two metalized through holes penetrating through the second base layer are formed in the chip, and inner-layer circuits are arranged on the outer walls of the metalized through holes. The first electrode is communicated with the first metalized through hole through the metal circuit, and the electrode is communicated with the second metalized through hole through the metal circuit. The inner layer circuit of the first metalized via hole or the first metalized via hole is provided with a first contact on the extended metal circuit on the lower surface of the second base layer; and contacts are arranged on the inner layer circuit of the second metalized through hole or the extended metal circuit of the lower surface of the second base layer of the second metalized through hole.
In an embodiment of the present invention, the first base layer is provided with a second blind hole leading to the second base layer, a first electrode is disposed below the second blind hole, the first electrode is communicated with the first metalized via through an extended metal line, and the first contact is disposed on the extended metal line of the first metalized via on the lower surface of the second base layer; the first metalized via and the second metalized via penetrate through the second base layer but do not penetrate through the first base layer; the first metalized via hole and the second metalized via hole are provided with inner layer lines in the second base layer, and the inner layer lines are unfolded around the hole walls of the first metalized via hole and the second metalized via hole. The contacts are located on the extended metal lines of the second metallized via on the lower surface of the second base layer. The electrode is arranged at the bottom of the first blind hole and is connected with the second metallized through hole through the extending metal circuit, so that the electrode is indirectly connected with the inner layer circuit and the annular metal circuit on the lower surface of the second base layer and is further connected with the contact.
When the conductive electrode is used, the first contact and the contact are connected with a power supply, voltage can be formed between the first electrode and the electrode, and conductive media are communicated above the first blind hole and the second blind hole.
In another form of the chip according to the present invention, the first electrode is disposed on the upper surface of the first base layer, preferably, the first electrode is disposed at an edge of an upper end of the first metalized via, and more preferably, the first electrode is disposed near the upper end of the first metalized via.
The electrode is arranged on the lower surface of the bottom of the first base layer and passes through the bottom of the first blind hole, more preferably, the electrode is arranged between the first base layer and the second base layer, more preferably, the electrode covers the whole bottom surface of the first blind hole, and particularly preferably, the electrode extends to the second metallized through hole.
The first blind hole is located on the first base layer, an electrode is arranged at the bottom of the first blind hole, and the first blind hole, the first electrode and the electrode form a hole electrode.
The first contact is located on the extended metal line of the first metalized via hole on the upper surface of the first base layer or the lower surface of the second base layer, and the contact is located on the extended metal line of the second metalized via hole on the upper surface of the first base layer or the lower surface of the second base layer. The first electrode can be connected with the first contact through the annular metal circuit and the inner layer circuit of the first base layer upper surface or the second base layer lower surface of the first metalized through hole, and the electrode can be connected with the contact through the annular metal circuit and the inner layer circuit of the first base layer upper surface or the second base layer lower surface of the second metalized through hole.
More preferably, the metal circuit and the inner layer circuit are copper foils.
The first base layer and the second base layer are made of plastic.
Preferably, the material of the first base layer is plastic, preferably, the material of the first base layer is polyimide resin board, FR-4 board, FR-1 board or CEM-1/3 board, more preferably, the FR-4 board is glass fiber board or epoxy resin board with FR-4 grade. In one embodiment of the present invention, the material of the first base layer is a polyimide resin plate.
The thickness of the first base layer is 0.05-0.5mm, and preferably, the thickness of the first base layer is 0.08-0.2 mm. In one embodiment of the present invention, the first base layer has a thickness of 0.1 mm.
The first blind hole and the second blind hole are arranged on the upper surface of the first base layer, and preferably, the first blind hole and the second blind hole are circular holes; preferably, the aperture of the first blind hole is 0.05-0.2mm, and more preferably, the aperture of the first blind hole is 0.1-0.15 mm. The first blind hole may be formed by a laser drilling technique. Preferably, the aperture of the second blind hole is 0.5-2mm, and more preferably, the aperture of the second blind hole is 1-1.5 mm. The second blind hole may be formed by a laser drilling technique.
The material of the second base layer is plastic, preferably, the material of the second base layer is polyimide resin plate, FR-4 plate, FR-1 plate or CEM-1/3 plate, more preferably, the material of the second base layer is FR-4 plate, more preferably, the FR-4 plate is glass fiber plate or epoxy resin plate with FR-4 grade. In one embodiment of the present invention, the material of the second substrate is FR-4 epoxy resin board.
The materials of the first base layer and the second base layer are insulated, so that the current signals of the chip can only be conducted by the metal circuit and the inner layer circuit, and the metal circuit and the inner layer circuit with different structures can be designed conveniently according to actual requirements; the materials of the first base layer and the second base layer are corrosion-resistant, and have strong impact resistance while ensuring certain strength, so that the application range of the chip is wide; the plasticity of the first base layer and the second base layer is strong, and the chip is convenient to manufacture by utilizing a PCB processing technology.
In one embodiment of the invention, the chip comprises a first base layer and a second base layer.
In another embodiment of the present invention, the chip includes a first base layer, a second base layer, and a third base layer between the first base layer and the second base layer.
The invention also provides the application of the chip in biological detection, preferably the application of the chip in nucleic acid sequencing, and more preferably the application of the chip in nanopore nucleic acid sequencing.
The inner layer circuit of the chip can be connected with required detection and analysis equipment, the hole electrode, the first contact and the contact of the chip are connected with current, and the current is conducted to the required detection and analysis equipment through the inner layer circuit, so that the chip has a control effect on the detection and analysis equipment.
The invention also provides application of the chip as a chip for biological monitoring, preferably application of the chip as a chip for a nucleic acid sequencing device, and more preferably application of the chip as a chip for a nanopore sequencing device. Compared with a chip of a silicon substrate, the chip can realize circuit arrangement among multiple layers of base layers, and is low in cost and simple and convenient in process.
Drawings
FIG. 1 is a diagram of the chip architecture of the present invention.
Fig. 2 is an alternative chip architecture diagram of the present invention.
FIG. 3 is a structural diagram of a nanopore gene sequencing device to which the chip of the present invention is applied.
FIG. 4 is a block diagram of the chip of the present invention applied to an alternative nanopore gene sequencing device.
Fig. 5 is a top surface structure diagram of the chip of the present invention.
Fig. 6 is an alternative chip architecture diagram of the present invention.
In the figure, 1-a first base layer, 2-a second base layer, 3-a first blind hole, 4-a metal line, 401-a first electrode, 402-an electrode, 5-a first metalized via hole, 501-a second metalized via hole, 6-an inner layer line, 7-a first contact, 8-a contact, 9-a third base layer, 10-an electrolyte chamber, 11-a phospholipid membrane, and 12-a second blind hole.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The invention provides a chip with a composite layer, which comprises a first base layer 1 and a second base layer 2 which are arranged at least up and down, wherein the first base layer 1 is provided with at least one first blind hole 3 leading to the second base layer 2, the chip is also provided with at least one metalized through hole penetrating through the second base layer 2, an electrode 402 is arranged below the first blind hole 3, the chip is provided with a contact 8, and the electrode 402 is connected with the contact 8 through a circuit.
All metal lines in the following examples are copper foils.
Example 1
The chip structure of the present embodiment is as shown in fig. 1, wherein a first base layer 1 is located on the upper portion of the chip, the first base layer 1 is a polyimide resin plate, and the thickness of the first base layer 1 is 0.1 mm; a hole electrode is arranged on the first base layer 1, a first blind hole 3 is arranged on the upper surface of the first base layer 1, the first blind hole 3 is a circular hole, the aperture is 0.1mm, the first blind hole 3 is formed by a laser drilling technology, a metal circuit 4 is arranged at the bottom of the first blind hole 3, and the first blind hole 3 and the metal circuit 4 form the hole electrode; a first electrode 401 is arranged in the vicinity of the upper end of the first metallized via 5, an electrode 402 is arranged between the first base layer 1 and the second base layer 2 and covers the entire bottom surface of the first blind via 3, the electrode 402 extends to the second metallized via 501; the second base layer 2 is positioned below the first base layer 1 and clings to the first base layer 1, and the second base layer 2 is an FR-4 epoxy resin plate; the first metalized via hole 5 and the second metalized via hole 501 penetrate through the first base layer 1 and the second base layer 2, inner layer lines 6 are arranged on the hole walls of the first metalized via hole 5 and the second metalized via hole 501, a plurality of metal lines of the inner layer lines 6 extend into the first base layer 1 and the second base layer 2, and the metal lines 4 of the hole electrodes are connected with the inner layer lines 6 of the second metalized via holes 501; the first contact 7 is arranged on a metal circuit at the top or the bottom of the first metalized via hole 5, the contact 8 is arranged on a metal circuit at the top or the bottom of the second metalized via hole 501, the first electrode 401 is connected with the first contact 7 through the metal circuit of the first metalized via hole 5 and the inner layer circuit 6, the electrode 402 is connected with the contact 8 through the metal circuit of the second metalized via hole 501 and the inner layer circuit 6, interconnection is realized, and further, circuit arrangement of the first base layer 1 and the second base layer 2 is realized.
Example 2
The chip structure of the present embodiment is as shown in fig. 2, wherein a first base layer 1 is located on the upper portion of the chip, the first base layer 1 is a polyimide resin plate, and the thickness of the first base layer 1 is 0.1 mm; a hole electrode is arranged on the first base layer 1, a first blind hole 3 is arranged on the upper surface of the first base layer 1, the first blind hole 3 is a circular hole, the aperture is 0.1mm, the first blind hole 3 is formed by a laser drilling technology, a metal circuit 4 is arranged at the bottom of the first blind hole 3, and the first blind hole 3 and the metal circuit 4 form the hole electrode; a first electrode 401 is arranged in the vicinity of the upper end of the first metallized via 5, an electrode 402 is arranged between the first base layer 1 and the third base layer 9 and covers the entire bottom surface of the first blind via 3, the electrode 402 extending to the second metallized via 501; the third base layer 9 is positioned below the first base layer 1 and clings to the first base layer 1, the second base layer 2 is positioned below the third base layer 9 and clings to the third base layer 9, and the second base layer 2 and the third base layer 9 are both made of FR-4 epoxy resin plates; the first metalized via hole 5 and the second metalized via hole 501 penetrate through the first base layer 1, the third base layer 9 and the second base layer 2, inner layer lines 6 are arranged on the hole walls of the first metalized via hole 5 and the second metalized via hole 501, a plurality of metal lines of the inner layer lines 6 extend into the first base layer 1, the third base layer 9 and the second base layer 2, and the metal lines 4 of the hole electrodes are connected with the inner layer lines 6 of the second metalized via holes 501; the first contact 7 is arranged on a metal circuit at the top or the bottom of the first metalized via hole 5, the contact 8 is arranged on a metal circuit at the top or the bottom of the second metalized via hole 501, the first electrode 401 is connected with the first contact 7 through the metal circuit of the first metalized via hole 5 and the inner layer circuit 6, the electrode 402 is connected with the contact 8 through the metal circuit of the second metalized via hole 501 and the inner layer circuit 6, interconnection is realized, and circuit arrangement of the first base layer 1, the third base layer 9 and the second base layer 2 is further realized.
Example 3
The structure of the nanopore gene sequencing device with the chip applied is shown in fig. 3, wherein the first base layer 1 is positioned on the upper part of the chip, the first base layer 1 is a polyimide resin plate, and the thickness of the first base layer 1 is 0.1 mm. The upper part of the chip is provided with an electrolyte chamber 10 for containing electrolyte containing a DNA detection sample; be equipped with the hole electrode on the first basic unit 1, the upper surface of first basic unit 1 is equipped with first blind hole 3, and first blind hole 3 is the circular port, and the aperture is 0.1mm, and first blind hole 3 forms through laser drilling's technique, and the bottom of first blind hole 3 is equipped with metal circuit 4, and first blind hole 3 and metal circuit 4 constitute the hole electrode. A first electrode 401 is arranged in the vicinity of the upper end of the first metallized via 5, an electrode 402 is arranged between the first base layer 1 and the second base layer 2 and covers the entire bottom surface of the first blind via 3, the electrode 402 extending to the second metallized via 501. The second substrate 2 is positioned below the first substrate 1 and clings to the first substrate 1, and the second substrate 2 is an FR-4 epoxy resin board. The first metalized via hole 5 and the second metalized via hole 501 penetrate through the first base layer 1 and the second base layer 2 and are located outside the electrolyte chamber 10, inner layer lines 6 are arranged on the hole walls of the first metalized via hole 5 and the second metalized via hole 501, a plurality of metal lines of the inner layer lines 6 extend into the first base layer 1 and the second base layer 2, and the metal lines 4 of the hole electrodes are connected with the inner layer lines 6 of the second metalized via holes 501. The first contact 7 is arranged on a metal circuit at the top or the bottom of the first metalized via hole 5, the contact 8 is arranged on a metal circuit at the top or the bottom of the second metalized via hole 501, the first electrode 401 is connected with the first contact 7 through the metal circuit of the first metalized via hole 5 and the inner layer circuit 6, the electrode 402 is connected with the contact 8 through the metal circuit of the second metalized via hole 501 and the inner layer circuit 6, interconnection is realized, and further, circuit arrangement of the first base layer 1 and the second base layer 2 is realized.
A phospholipid bilayer membrane 11 is arranged between the electrolyte chamber 10 and the first blind hole 3, so that the electrolyte chamber 10 and the first blind hole 3 form two chambers, protein with a nanopore structure is embedded on the phospholipid bilayer membrane 11, when the first contact 7 and the contact 8 are powered on, namely the first electrode 401 and the electrode 402 are powered on, a DNA detection sample in the electrolyte chamber 10 moves under the action of current and enters the first blind hole 3 through the nanopore of the protein, the current change of different bases on the DNA when passing through the nanopore is recorded, and the DNA sequence is analyzed.
Example 4
The structure of the chip applied to an optional nanopore gene sequencing device is shown in fig. 4, wherein a first base layer 1 is positioned on the upper portion of the chip, the first base layer 1 is a polyimide resin plate, and the thickness of the first base layer 1 is 0.1 mm. The upper part of the chip is provided with an electrolyte chamber 10 for containing electrolyte containing a DNA detection sample; be equipped with the hole electrode on the first basic unit 1, the upper surface of first basic unit 1 is equipped with first blind hole 3, and first blind hole 3 is the circular port, and the aperture is 0.1mm, and first blind hole 3 forms through laser drilling's technique, and the bottom of first blind hole 3 is equipped with metal circuit 4, and first blind hole 3 and metal circuit 4 constitute the hole electrode. A first electrode 401 is disposed at the upper portion of the electrolyte chamber 10 and extends to the outside for connection to a power source, an electrode 402 is disposed between the first and second base layers 1 and 2 and covers the entire bottom surface of the first blind via 3, and the electrode 402 extends to the second metalized via 501. The second substrate 2 is positioned below the first substrate 1 and clings to the first substrate 1, and the second substrate 2 is an FR-4 epoxy resin board. The second metalized via hole 501 penetrates through the first base layer 1 and the second base layer 2 and is located outside the electrolyte chamber 10, an inner layer line 6 is arranged on the hole wall of the second metalized via hole 501, a plurality of metal lines of the inner layer line 6 extend into the first base layer 1 and the second base layer 2, and the metal line 4 of the hole electrode is connected with the inner layer line 6 of the second metalized via hole 501. The first contact 7 is arranged on the first electrode 401, the contact 8 is arranged on the metal circuit at the top or the bottom of the second metalized via hole 501, and the electrode 402 is connected with the contact 8 through the metal circuit of the second metalized via hole 501 and the inner layer circuit 6 to realize interconnection, so that the circuit arrangement of the first base layer 1 and the second base layer 2 is realized.
A phospholipid bilayer membrane 11 is arranged between the electrolyte chamber 10 and the first blind hole 3, so that the electrolyte chamber 10 and the first blind hole 3 form two chambers, protein with a nanopore structure is embedded on the phospholipid bilayer membrane 11, when the first contact 7 and the contact 8 are powered on, namely the first electrode 401 and the electrode 402 are powered on, a DNA detection sample in the electrolyte chamber 10 moves under the action of current and enters the first blind hole 3 through the nanopore of the protein, the current change of different bases on the DNA when passing through the nanopore is recorded, and the DNA sequence is analyzed.
Example 5
As shown in fig. 5, the upper surface structure of the chip is that the first contact 7 is located on the extended metal line of the first metalized via 5 on the upper surface of the first base layer 1, the first electrode 401 is connected to the first contact 7 through the annular metal line of the metalized via 5 on the upper surface of the first base layer 1, the electrode 402 is located at the bottom of the first blind via 3, and the electrode 402 is connected to the contact 8 through the inner wall of the second metalized via 501 and the annular metal line on the upper surface of the first base layer 1.
Example 6
As shown in fig. 6, the chip structure of this embodiment is that a second blind hole 12 leading to a second base layer 2 is formed in a first base layer 1, a first electrode 401 is disposed below the second blind hole 12, the first electrode 401 is communicated with a first metalized via 5 through an extended metal line 4, and a first contact 7 is disposed on the extended metal line of the first metalized via 5 on the lower surface of the second base layer 2; the first metallized via 5 and the second metallized via 501 penetrate the second base layer 2, but do not penetrate the first base layer 1; the first and second metalized vias 5 and 501 are provided with an inner layer line 6 in the second base layer 2, and the inner layer line 6 is spread around the hole walls of the first and second metalized vias 5 and 501. Contact 8 is located on the extended metal line of the second metallized via 501 on the lower surface of the second base layer 2. The electrode 402 is disposed at the bottom of the first blind via 3 and is connected to the second metalized via 501 via the extended metal trace 4, thereby indirectly connecting the inner trace 6 to the annular metal trace on the lower surface of the second substrate 2 and further connecting the contact 8.
When the conductive blind via is used, the first contact 7 and the contact 8 are connected with a power supply, namely, a voltage can be formed between the first electrode 401 and the electrode 402, and the conductive medium is communicated above the first blind via 3 and the second blind via 12.
Claims (13)
1. The chip with the composite layer and the application thereof in biological detection are characterized in that the chip comprises a first base layer and a second base layer which are arranged at least up and down, wherein at least one first blind hole leading to the second base layer is formed in the first base layer, at least one metalized through hole penetrating through the second base layer is further formed in the chip, an electrode is arranged below the first blind hole, a contact is arranged on the chip, and the electrode is connected with the contact through a circuit.
2. The chip of claim 1, wherein a first electrode is disposed on the upper and lower surfaces of the first substrate or above the first substrate, the chip further having a first contact, and the first electrode is connected to the first contact via a wire.
3. The chip of claim 2, wherein the first substrate further comprises at least one second blind via opening to the second substrate, and the first electrode is disposed below the second blind via opening.
4. The chip of claim 3, wherein at least two metalized vias are disposed through the second substrate, and the outer walls of the metalized vias are provided with inner layer lines.
5. The chip of claims 3 and 4, wherein the first electrode is in communication with the first metalized via through a metal line, and the electrode is in communication with the second metalized via through a metal line.
6. The chip of claim 5, wherein the inner layer trace of the first metalized via or the first metalized via is provided with a first contact on the extended metal trace on the lower surface of the second base layer; and contacts are arranged on the inner layer circuit of the second metalized through hole or the extended metal circuit of the lower surface of the second base layer of the second metalized through hole.
7. The chip of claims 1 and 2, wherein the metalized via penetrates through the first base layer and the second base layer, the first contact is located on an extended metal line of the first metalized via on the upper surface of the first base layer or on the lower surface of the second base layer, the first electrode is arranged on the upper end edge of the first metalized via, and the first electrode is connected with the first contact through a ring-shaped metal line of the first metalized via on the upper surface of the first base layer or on the lower surface of the second base layer and an inner line.
8. The chip of claim 1, wherein the contact is located on an extended metal line of the second metalized via on the upper surface of the first base layer or the lower surface of the second base layer; the electrode can be connected with the contact through the annular metal circuit and the inner layer circuit of the second metalized through hole on the upper surface of the first base layer or the lower surface of the second base layer.
9. The chip of claim 1, wherein the second substrate has an inner layer circuit disposed therein.
10. The chip of claim 1, wherein at least one third substrate is disposed between the first and second substrates.
11. The chip of claim 1, wherein the material of the first and second substrates is plastic, and preferably, the material of the first and second substrates is polyimide resin board, FR-4 board, FR-1 board or CEM-1/3 board.
12. The chip according to claims 1 and 3, wherein the first blind hole has a hole diameter of 0.1-0.15mm, and the second blind hole has a hole diameter of 1-1.5 mm.
13. Use of the chip according to claim 1 in biological assays, preferably in nucleic acid sequencing, more preferably in nanopore nucleic acid sequencing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910346219.XA CN111849735A (en) | 2019-04-26 | 2019-04-26 | Chip with composite layer and application thereof in biological detection |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910346219.XA CN111849735A (en) | 2019-04-26 | 2019-04-26 | Chip with composite layer and application thereof in biological detection |
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| Publication Number | Publication Date |
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| CN111849735A true CN111849735A (en) | 2020-10-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113899803A (en) * | 2021-11-09 | 2022-01-07 | 北京航空航天大学 | ISFETs sensing structure with 3D pore channel |
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2019
- 2019-04-26 CN CN201910346219.XA patent/CN111849735A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113899803A (en) * | 2021-11-09 | 2022-01-07 | 北京航空航天大学 | ISFETs sensing structure with 3D pore channel |
| CN113899803B (en) * | 2021-11-09 | 2022-12-30 | 北京航空航天大学 | ISFETs sensing structure with 3D pore channel |
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