CN111835341B

CN111835341B - Automatic search apparatus and method for downsampling phase-locked loop SS-PLL lock acquisition

Info

Publication number: CN111835341B
Application number: CN202010075439.6A
Authority: CN
Inventors: 左永荣; 姚智伟; 吴王华
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-04-23
Filing date: 2020-01-22
Publication date: 2022-07-29
Anticipated expiration: 2040-01-22
Also published as: CN111835341A

Abstract

An apparatus and method are provided. The apparatus includes a phase-locked loop (PLL) configured to generate a reference signal; a downsampling PLL (SS-PLL) connected to the PLL and configured to downsample the reference signal; a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs averages zero.

Description

Automatic search apparatus and method for downsampling phase-locked loop SS-PLL lock acquisition

Technical Field

The present disclosure relates generally to electronic circuits, and more particularly, to an apparatus and method for automatic search for sub-sampling Phase Locked Loop (PLL) lock acquisition.

Background

SS-PLLs are used for frequency synthesis in communication systems due to their excellent phase noise performance. However, due to the sinusoidal nature of the down-sampled phase detector (SSPD) or sampler, the SS-PLL cannot distinguish between different harmonics of the reference frequency and has a very limited frequency acquisition range.

For an SS-PLL to lock successfully and reliably, the Voltage Controlled Oscillator (VCO) frequency of the PLL must be very close to the locking frequency with the help of an additional Frequency Locking Loop (FLL) or digital counter/calibrator. Generating such VCO frequencies is challenging for SS-PLLs operating at tens of gigahertz (GHz) for applications such as millimeter wave (mmWave) applications. In addition to frequency accuracy requirements, any frequency disturbance or charge redistribution during switching from the FLL or digital counter to the SS-PLL may cause the VCO frequency to deviate from the narrow locking range of the SS-PLL.

Disclosure of Invention

According to one embodiment, an apparatus comprises: a PLL configured to generate a reference signal; an SS-PLL connected to the PLL and configured to down-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow the output voltage of the SS-PLL to transition to an operating voltage to indicate that the difference between the two voltage inputs averages to zero.

According to one embodiment, an apparatus comprises: a PLL configured to generate a reference signal; an SS-PLL connected to the PLL and configured to down-sample the reference signal; a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs averages to zero; a Frequency Locked Loop (FLL) connected to the SS-PLL; a switch connected between the FLL and SS-PLL outputs; and a coarse tuner connected between the output of the SS-PLL and the input of the SS-PLL.

According to one embodiment, a method comprises: generating a reference signal by a Phase Locked Loop (PLL); down-sampling the reference signal by a down-sampling PLL (SS-PLL) connected to the PLL; and transitioning, by a first pre-charge circuit connected to the SS-PLL, the output voltage of the SS-PLL to an operating voltage to indicate that the difference between the two voltage inputs averages zero.

According to one embodiment, a method comprises: generating a reference signal by a PLL; down-sampling the reference signal by an SS-PLL connected to the PLL; transitioning, by a first pre-charge circuit connected to the SS-PLL, an output voltage of the SS-PLL to an operating voltage to indicate that a difference between the two voltage inputs averages zero; the FLL connected to the SS-PLL locks the frequency of the SS-PLL; switching the output of the SS-PLL to the FLL by a switch connected between the FLL and the output of the SS-PLL; and coarse tuning the SS-PLL by a coarse tuner coupled between an output of the SS-PLL and an input of the SS-PLL.

Drawings

The above and other aspects, features and advantages of particular embodiments of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a block diagram of an SS-PLL and an FLL according to one embodiment;

FIG. 2 shows another block diagram of an SS-PLL and an FLL in accordance with one embodiment.

FIG. 3 illustrates transconductance (g) of an SS-PLL according to one embodiment _m ) A diagram of a stage device;

FIG. 4A illustrates g of the present invention with precharging in accordance with one embodiment _m A view of a stage device;

FIG. 4B illustrates g of the present invention with precharging in accordance with one embodiment _m Another view of a stage device;

FIG. 5 shows a block diagram of an SS-PLL according to one embodiment;

FIG. 6 shows another block diagram of an SS-PLL and an FLL in accordance with one embodiment.

FIG. 7A shows a block diagram of the SS-PLL of the present invention with pre-charging according to one embodiment;

fig. 7B shows another block diagram of the SS-PLL of the present invention with pre-charging, in accordance with one embodiment.

FIG. 8A shows a block diagram of the SS-PLL of the present invention with coarse tuning according to one embodiment;

fig. 8B shows another block diagram of the SS-PLL of the present invention with coarse tuning according to one embodiment;

FIG. 9A shows a block diagram of the SS-PLL of the present invention with FLL and coarse tune, according to one embodiment;

FIG. 9B shows another block diagram of the SS-PLL of the present invention with FLL and coarse tune, according to one embodiment;

FIG. 10A illustrates g of the present invention for an SS-PLL with current bleeding according to one embodiment _m A view of a stage device;

FIG. 10B shows g of the invention with a current bleeding SS-PLL according to one embodiment _m Another view of a stage device;

FIG. 10C shows g of the invention with a current bleeding SS-PLL according to one embodiment _m Another view of a stage device; and

fig. 11 illustrates a flow diagram of a method of the present invention that provides automatic searching for SS-PLL lock acquisition, according to one embodiment.

Detailed Description

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that, although the same elements are shown in different drawings, they will be denoted by the same reference numerals. In the following description, only specific details such as detailed configurations and components are provided to assist in an overall understanding of embodiments of the present disclosure. Thus, it will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the disclosure. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. The terms described below are terms defined in consideration of functions in the present disclosure, and may be different according to a user, a user's intention, or a habit. Therefore, the definition of the terms should be determined based on the contents throughout the specification.

The present disclosure may have various modifications and various embodiments, wherein the embodiments are described in detail below with reference to the accompanying drawings. It should be understood, however, that the disclosure is not limited to the embodiments, but includes all modifications, equivalents, and alternatives falling within the scope of the disclosure.

Although terms including ordinal numbers such as first, second, etc., may be used to describe various elements, structural elements are not limited by the terms. These terms are only used to distinguish one element from another. For example, a first structural element may be termed a second structural element without departing from the scope of the present disclosure. Similarly, the second structural element may also be referred to as the first structural element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated items.

The terminology used herein is for the purpose of describing various embodiments of the disclosure only and is not intended to be limiting of the disclosure. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In the present disclosure, it is to be understood that the terms "comprises" or "comprising" mean the presence of the features, numbers, steps, operations, structural elements, components or combinations thereof, and do not preclude the presence or possibility of one or more other features, numbers, steps, operations, structural elements, components or combinations thereof.

Unless defined differently, all terms used herein have the same meaning as understood by those skilled in the art to which this disclosure belongs. Unless explicitly defined in the present disclosure, the meaning of a term such as that defined in a general dictionary should be construed to be the same as the contextual meaning in the related art, and should not be construed to have an ideal or excessively formal meaning.

FIG. 1 shows a block diagram of an SS-PLL101 and an FLL103 according to one embodiment.

Referring to FIG. 1, SS-PLL101 includes SSPD 105, pulser or pulser 107, Charge Pump (CP)109, resistor R ₁ 111. A first capacitor C ₁ A second capacitor C ₂ And a VCO 113. Resistor R ₁ 111. A first capacitor C ₁ And a second capacitor C ₂ Forming a low pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. The FLL103 includes a Phase Frequency Detector (PFD)115, a dead zone compensator (DZ)117, a Charge Pump (CP)119, and a frequency divider 121.

SSPD 105 includes a first input for receiving a reference signal Ref, a second input from the output of VCO 113, and an output. Pulser 107 includes an input for receiving reference signal Ref, and an output. The CP 109 of the SS-PLL101 includes a first input connected to the output of the SSPD 105, a second input connected to the output of the pulser 107, and an output. Resistor R ₁ Connected between the output of the CP 109 of the SS-PLL101 and the first capacitor C ₁ In the meantime. A first capacitor C ₁ Connected to a resistor R ₁ And ground potential. A second capacitor C ₂ Connected between the output of the CP 109 of the SS-PLL101 and ground potential. VCO 113 includes an input connected to the output of CP 109 of SS-PLL101, and an output connected to a second input of SSPD 105.

The PFD 115 includes a first input for receiving a reference signal Ref, a second input and an output. The DZ 117 includes an input connected to the output of the PFD 115, and an output. The CP 119 in the FLL103 includes an input connected to the output of the DZ 117, and an output connected to the input of the VCO 113. The divider 121 includes an input connected to the output of the VCO 113, and an output connected to a second input of the PFD 115.

FLL103 assists VCO 113 in locking to the target frequency before switching to SS-PLL 101. FLL103 brings the frequency of VCO 113 close enough to the target frequency to assist in frequency lock so that SS-PLL101 can then successfully take over.

Fig. 2 shows a block diagram of an SS-PLL201 and an FLL203 according to an embodiment.

Referring to fig. 2, the SS-PLL201 includes a Pulse Detector (PD)/(SAMP)205, a transconductance (g) _m ) Stage device 207, summing node 209 (e.g., adder, multiplexer, etc.) (where g _m The outputs of stage 207 and CP 217 are connected together and only one of these outputs is enabled), Low Pass Filter (LPF)211 and VCO 213. The FLL203 includes a PFD 215, a DZ 216, a CP 217, and a divider 219.

PD/SAMP 205 includes a first input for receiving a reference clock signal (CLKREF), a second input, and a differential output. In an embodiment, the differential output of PD/SAMP 205 may be a single ended output. g _m Stage device 207 includes a positive input connected to a first output of PD/SAMP 205, a negative input connected to a second output of PD/sampler 205, and an output. The summing junction 209 includes a node connected to g _m A first input, a second input and an output of the stage device 207. Summing node 209 acts as a multiplexer. The multiplexer may be implemented explicitly or implicitly. When the FLL203 is locked, the FLL203 enters DZ and automatically turns off the output, and then g can be enabled by switching the control signal _m The output of stage device 207. The switching control signal may be generated from a lock detector, which is omitted from the figure for simplicity. Otherwise, the switching control signal may come from an external control signal to switch from FLL203 to SS-PLL 201. The LPF211 includes an input connected to the output of the summing junction 209, and an output. VCO 213 includes an input connected to the output of LPF211, and an output connected to a second input of PD/SAMP 205, where the output of VCO 213 is the VCO clock signal (CLKVCO).

PFD 215 includes a first input connected to PD/SAMP 205 for receiving CLKREF, a second input, a first (up) output, and a second (down) output. The DZ 216 comprises a first input connected to a first output of the PFD 215, a second input connected to a second output of the PFD 215, a first output and a second output. CP 217 includes a first input connected to a first output of DZ 216, a second input connected to a second output of DZ 216, and an output connected to a second input of summing node 209. The divider 219 includes an input connected to the output of the VCO 213 and an output connected to a second input of the PFD 215.

The device includes an FLL203 or digital counter to first obtain frequency lock before switching to the SS-PLL 201. The loop in the SS-PLL201 and the loop in the FLL203 may have different loop dynamics, requiring different LPFs. With a digital counter, the control voltage (e.g., VCTRL) is set to a constant voltage (e.g., the power supply voltage (e.g., VDD) divided by 2 (e.g., VDD/2).

FIG. 3 illustrates g of an SS-PLL201 according to one embodiment _m Illustration of stage device 207.

Referring to FIG. 3, g _m Stage device 207 includes a first p-channel metal-oxide-semiconductor field effect transistor (PMOSFET)301, a first n-channel metal-oxide-semiconductor field effect transistor (NMOSFET)303, a second PMOSFET 305, a second NMOSFET 307, and a current source 309.

The first PMOSFET 301 includes a source, a gate for receiving the positive input SmpP, and a drain. The first NMOSFET 303 includes a drain connected to the drain of the first PMOSFET 301, a gate connected to the drain of the first PMOSFET 301, and a source connected to ground potential. The second PMOSFET 305 includes a source, a gate for receiving a negative input SmpM, and a drain. The second NMOSFET 307 includes a drain connected to the drain of the second PMOSFET 305, a gate connected to the drain of the first PMOSFET 301, and a source connected to ground potential, wherein the drain of the second NMOSFET 307 provides the control voltage VCTRL. The current source 309 is connected between a power supply (e.g., VDD) and the sources of the first PMOSFET 301 and the second PMOSFET 305.

The inputs SmpP and SmpM are differentially sampled outputs from SS-PLL samplers (e.g., SSPD in fig. 1). g _m The control voltage VCTRL of the stage device 207 enters the LPF211 and adjusts the frequency of the VCO 213.

When the SS-PLL is used in applications such as 5 th generation (5G) mmWave applications, the SS-PLL may operate at frequencies of tens of GHz. The feedback divider for the FLL operating at the frequency required by such an SS-PLL has a high power consumption. To incorporate an FLL, the frequency accuracy requirements of the FLL may be as small as less than 1 megahertz (MHz), depending on the particular PLL design parameters. The VCO of such an SS-PLL may require very fine resolution (e.g., Least Significant Bit (LSB) resolution), which may introduce large parasitic capacitances and is therefore not preferred for mmWave applications, especially those requiring a wide frequency tuning range. Furthermore, during the switch from FLL to SS-PLL, any frequency perturbations or charge redistribution may shift the VCO frequency out of the acquisition range where the SS-PLL can successfully lock.

FIG. 4A illustrates g of SS-PLL201 with precharge according to one embodiment _m Illustration of stage device 207.

Referring to FIG. 4A, g _m The stage device 207 includes a first PMOSFET transistor 401, a first NMOSFET 403, a second PMOSFET 405, a second NMOSFET 407, a current source 409, and a switch 411.

The first PMOSFET 401 includes a source, a gate for receiving the positive input SmpP, and a drain. The first NMOSFET 403 includes a drain connected to the drain of the first PMOSFET 401, a gate connected to the drain of the first PMOSFET 401, and a source connected to ground potential. The second PMOSFET 405 includes a source, a gate for receiving a negative input SmpM, and a drain. The second NMOSFET 407 includes a drain connected to the drain of the second PMOSFET 405, a gate connected to the drain of the first PMOSFET 401, and a source connected to ground potential, where the drain of the second NMOSFET 407 provides the control voltage VCTRL. A current source 409 is connected between a power supply (e.g., VDD) and the sources of the first PMOSFET 401 and the second PMOSFET 405, and delivers a current I _gm . The switch 411 is connected between VDD and the drain of the second NMOSFET 407.

The SS-PLL may erroneously lock to other frequencies or may not recover from a large frequency/phase error. G of SS-PLL according to one embodiment _m The stage device 207 includes an output node (i.e., the drain of the second NMOSFET 407) having a switch 411, and when the switch 411 is closed, the control voltage VCTRL is precharged to a desired voltage (e.g., VDD), and then VCTRL is released by opening the switch 411. Such asIf SS-PLL is not locked, the control voltage VCTRL is reduced to g _m Stage output operating point, due to g _m The differential inputs SmpP and SmpM received by the stage device 207 are sine waves, where SmpP is in anti-phase with SmpM and therefore has a value that averages zero volts. Frequency f of each sine wave _SMP Is a reference frequency f _REF And the VCO frequency f _VCO The difference between divided by the harmonic N (e.g., f) _SMP ＝f _REF -f _VCO and/N). When g is _m The output node drops due to leakage current when the stage input has a zero volt input until the output node reaches its operating point, which may be a value that is close to ground by design.

When the SS-PLL is unlocked and the VCO frequency is outside the narrow locking range of the SS-PLL, the PD/SAMP of the SS-PLL generates a differential output voltage that averages zero volts, which feeds g _m The input of stage device 207. When in g _m G when the desired voltage is not present at the input of stage 207 _m The control voltage VCTRL of the stage device 207 drops from VDD (e.g., 1V) to its operating point (e.g., 0.2V).

The harmonic N is determined by the harmonics available in the VCO frequency range. Thus, there may be multiple solutions for N. When the SS-PLL loop is not locked, g is reached _m The average voltage input to the stage device 207 will be equal to the median (Vmid) of the sine wave swings of both SmpP and SmpM. Thus, in the direction of g _m The active differential input of stage device 207 is zero volts and its control voltage VCTRL stabilizes to its operating point, which is chosen by design to be a low voltage. For example, if VDD is 0.8V, and g _m Stage output operating point of 0.2V, then g _m The control voltage VCTRL of the stage device 207 continuously drops from 0.8V to 0.2V.

If the control voltage VCTRL for SS-PLL locking is within 0.2V to 0.8V, e.g., VCTRL is 0.5V, the SS-PLL201 will automatically lock at VCTRL 0.5V when the control voltage VCTRL drops from 0.8V to 0.5V, but will not continue to drop because g will drop when the SS-PLL is locked _m The differential input voltage of the stage device 207 is no longer zero volts. There is a fixed voltage difference between SmpP and SmpM. The input voltage difference will be g _m The control voltage VCTRL of the stage device 207 is maintained at a desired voltage value. VCTRL adjusts VCO 213Frequency. When VCTRL falls, the frequency of VCO goes from high frequency F _H Swept to a low frequency F _L . If the target frequency is at low frequency F _L And a high frequency F _H Within, then VCTRL remains at a value corresponding to the target frequency. At this time, PD/SAMP 205 of the SS-PLL is g _m The input SmpP/SmpM of the stage device 207 generates the required Direct Current (DC) voltage to support VCTRL in maintaining this value. The SS-PLL automatically locks. Output of PD/SAMP 205 or g when SS-PLL is locked _m The input of the stage device 207 becomes two fixed voltages. g _m The input of stage 207 will be g _m The control voltage VCTRL of stage device 207 is driven to a particular value that adjusts the VCO to oscillate at a desired frequency.

According to one embodiment, since there is only one desired harmonic of the input reference frequency when VCTRL drops from 0.8V to 0.2V, the SS-PLL does not lock to the wrong harmonic, and therefore the apparatus and method of the present invention may include one of: 1) a high reference frequency (e.g., 6GHz) and a VCO with a tuning range less than the reference frequency (e.g., from 16GHz to 20GHz) so there is only one harmonic solution in the VCO tuning range (e.g., 3 times the harmonic in this case), and/or (2) coarse VCO tuning to divide the entire VCO tuning range into a number of sub-ranges until there is only one harmonic in each sub-range. The coarse tuning may be implemented by a digital counter search or FLL loop.

The apparatus and method of the present invention is more robust, does not require the VCO to have very fine resolution or strict VCO frequency accuracy prior to switching to the SS-PLL, and is more resistant to frequency transients/disturbances or charge redistribution prior to switching to the SS-PLL than conventionally adding an FLL/digital counter for frequency lock.

FIG. 4B illustrates g of SS-PLL201 with precharge according to one embodiment _m Another view of stage device 207.

Referring to FIG. 4B, g _m Stage device 207 includes a first NMOSFET 421, a first PMOSFET 423, a second NMOSFET 425, a second PMOSFET 427, a current source 429, and a switch 431.

The first NMOSFET 421 includes a source, a gate for receiving the positive input SmpP, and a drain. First PMThe OSFET 423 includes a drain connected to the drain of the first NMOSFET 421, a gate connected to the drain of the first NMOSFET 421, and a source connected to a power supply (e.g., VDD). The second NMOSFET 425 includes a source, a gate for receiving a negative input SmpM, and a drain. The second PMOSFET 427 includes a drain connected to the drain of the second NMOSFET 425, a gate connected to the drain of the first NMOSFET 421, and a source connected to a power supply (e.g., VDD), wherein the drain of the second PMOSFET 427 provides the control voltage VCTRL. A current source 429 is connected between ground and the sources of the first NMOSFET 421 and the second NMOSFET 425 and delivers a current I _gm . The switch 431 is connected between the ground potential and the drain of the second PMOSFET 427.

Fig. 5 shows a block diagram of an SS-PLL501 according to one embodiment.

Referring to FIG. 5, SS-PLL501 includes VCO 503, Sampler (SAMP)505, g _m A stage device 507, a resistor 509, a first capacitor 511 and a second capacitor 513. The resistor 509, the first capacitor 511 and the second capacitor 513 form a low-pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. PLL 515 is connected to SS-PLL 501.

The VCO 503 includes an input and an output. SAMP 505 includes a first input connected to the output of VCO 503, a second input, a first output, and a second output. g _m Stage device 507 includes a positive input connected to a first output of SAMP 505, a negative input connected to a second output of SAMP 505, and an output that generates a control voltage VCTRL connected to an input of VCO 503. Resistor 509 is connected at g _m Between the output of the stage device 507 and the first capacitor 511. The first capacitor 511 is connected between the resistor 509 and the ground potential. A second capacitor 513 is connected to g _m Between the output of stage device 507 and ground potential. PLL 515 has an output connected to a second input of SAMP 505.

For example, the VCO 503 generates an 18GHz Local Oscillation (LO) frequency for a 5G mmWave transceiver. The tuning range of VCO 503 is less than 6GHz, which is less than its input reference frequency from PLL 515. Thus, the SS-PLL501 can only lock to 3 times the input clock, while the tuning range of the VCO 503 ensures that there is only one harmonic to which the SS-PLL501 can lock. The SS-PLL501 receives a 6GHz input from PLL 515 and generates an 18GHz output.

Even if the target frequency (e.g., 3 times the harmonic) need not be selected from among multiple harmonics of the input reference frequency, the SS-PLL501 will not lock in most cases due to its very limited acquisition range. Generally, before the SS-PLL501 can lock, VCTRL should be within a final value of 50mV or less, depending on the particular design. Outside this range, the SS-PLL501 samples the effective average of zero volts and the loop still cannot lock.

Fig. 6 shows another block diagram of an SS-PLL601 and an FLL according to an embodiment.

Referring to FIG. 6, SS-PLL601 includes VCO 603, SAMP 605, g _m A stage device 607, a first switch 609, a resistor 611, a first capacitor 613 and a second capacitor 615. The resistor 609, the first capacitor 613 and the second capacitor 615 form a low pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. PLL 617, feedback divider (FB DIV)619, PFD 621, CP 623, and second switch 625 are connected to SS-PLL 601.

The VCO 603 includes an input and an output. SAMP 605 includes a first input connected to the output of VCO 603, a second input, a first output, and a second output. g _m Stage device 607 includes a positive input connected to a first output of SAMP 605, a negative input connected to a second output of SAMP 605, and an output. The first switch 609 is connected to g _m Between the output of the stage device 607 and the input of the VCO 603, a control voltage VCTRL is generated where the first switch 609 is connected to the VCO 603. A resistor 611 is connected between the input of the capacitor VCO 603 and the first capacitor 613. The first capacitor 613 is connected between the resistor 611 and the ground potential. A second capacitor 615 is connected between the input of the VCO 603 and ground. PLL 617 has an output connected to a second input of SAMP 605.

FB DIV 619 includes an input connected to the output of VCO 603, and an output. PFD 621 includes an input connected to the output of FB DIV 619, and an output. CP 623 includes an input connected to the output of PFD 621, and an output. A second switch 625 is connected between the output of the CP 623 and the input of the VCO 603, wherein the second switch 625 may be an explicit switch or an implicit switch implemented by DZ in the PFD.

FB DIV 619, PFD 621, CP 623, and second switch 625 are FLLs that facilitate frequency locking. The first switch 609 and the second switch 625 are used to switch between the FLL and the SS-PLL 601. FB DIV 619 or digital counters must operate above 18GHz, which is a design challenge and typically results in high power consumption.

Fig. 7A shows a block diagram of an SS-PLL with precharge 701 according to one embodiment.

Referring to FIG. 7A, SS-PLL701 includes VCO 703, SAMPs 705, g _m Stage device 707, resistor 709, first capacitor 711, second capacitor 713, and switch 715. The PLL 717 is connected to the SS-PLL 701. The resistor 709, the first capacitor 711, and the second capacitor 713 form a low pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure.

The VCO 703 includes an input and an output. SAMP 705 includes a first input connected to the output of VCO 703, a second input, a first output, and a second output. g _m Stage device 707 includes a positive input connected to a first output of SAMP 705, a negative input connected to a second output of SAMP 705, and an output that generates a control voltage VCTRL connected to an input of VCO 703. Resistor 709 is connected at g _m Between the output of the stage device 707 and the first capacitor 711. The first capacitor 711 is connected between the resistor 709 and the ground potential. The second capacitor 713 is connected to g _m Between the output of stage device 707 and ground potential. Switch 715 is connected to g _m The output of stage device 707 and a power supply (e.g., VDD). PLL 717 has an output connected to a second input of SAMP 705.

Initially, switch 715 is closed and VCTRL is precharged to VDD. Then, switch 715 is opened and VCTRL falls and stops at a value that causes the SS-PLL to lock.

When the VCO 703 has a large tuning range containing multiple harmonics of the input reference frequency, it is desirable that the gain Kvco of the VCO 703 be small in order to more easily keep the loop stable.

Fig. 7B shows another block diagram of the SS-PLL with precharge 701 according to one embodiment.

Referring to FIG. 7B, SS-PLL701 includes VCO 723, SAMP 725, g _m Stage 727, resistor 729, first capacitor 731, second capacitor 733, and switch 735. The PLL 737 is connected to the SS-PLL 701. The resistor 729, the first capacitor 731, and the second capacitor 733 form a low-pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure.

The VCO 723 includes an input and an output. SAMP 725 includes a first input connected to the output of VCO 723, a second input, a first output, and a second output. g _m Stage device 727 includes a positive input connected to a first output of SAMP 725, a negative input connected to a second output of SAMP 725, and an output generating a control voltage VCTRL connected to an input of VCO 723. Resistor 729 is connected at g _m Between the output of the stage device 727 and the first capacitor 731. The first capacitor 731 is connected between the resistor 729 and ground potential. The second capacitor 733 is connected to g _m Between the output of stage device 727 and ground potential. Switch 735 is connected at g _m Between the output of stage device 727 and ground potential. PLL 737 has an output connected to a second input of SAMP 725.

Initially, switch 735 is closed and VCTRL is precharged to ground. Then, switch 735 is opened and VCTRL rises and stops at a value that causes SS-PLL to lock.

When the VCO 723 has a large tuning range containing multiple harmonics of the input reference frequency, it is desirable that the gain Kvco of the VCO 723 be small in order to more easily keep the loop stable.

Fig. 8A shows a block diagram of an SS-PLL801 with coarse tuning, according to one embodiment.

Referring to FIG. 8A, SS-PLL801 includes VCO 803, SAMP 805, g _m Stage 807, resistor 809, first capacitor 811, second capacitor 813, first switch 815, and second switch 817. The resistor 809, the first capacitor 811, and the second capacitor 813 form a low pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. Frequency calculation logic (FCAL LD)819, Digital Counter (DCNT)821, and PLL 823 are connected to SS-PLL 801. FCAL LD 819 and DCNT 821 may configure a coarse tuner.

The VCO 803 includes a first input, a second input, and an output. SAMP 805 includes a first input connected to the output of VCO 803, a second input, a first output, and a second output. g is a radical of formula _m Stage device 807 includes a positive input connected to a first output of SAMP 805, a negative input connected to a second output of SAMP 805, and an output that generates a control voltage VCTRL connected to a first input of VCO 803. Resistor 809 is connected at g _m Between the output of stage 807 and a first capacitor 811. The first capacitor 811 is connected between the resistor 809 and the ground potential. The second capacitor 813 is connected to g _m Between the output of stage device 807 and ground potential. The first switch 815 is connected to g _m Between the output of stage device 807 and a power supply (e.g., VDD). A second switch 817 is connected to g _m Between the output of stage device 807 and one-half of the power supply (e.g., VDD/2). During FCAL, switch 817 is closed to set VCTRL to VDD/2. After FCAL is complete, switch 817 is open. The FCAL LD 819 includes an input and an output connected to a second input of the VCO 803. DCNT 821 includes an input connected to the output of VCO 803 and an output connected to the input of FCAL LD 819. PLL 823 has an output connected to a second input of SAMP 805.

A coarse tuning scheme is added to first select the correct frequency sub-range of the VCO 803 and then perform an automatic search as described above. Coarse tuning is achieved by searching for DCNT 821 and FCAL LD 819. The SS-PLL801 includes DCNT 821 and FCAL LD 819 for providing coarse tuning for the VCO 803. First, VCTRL is precharged to VDD/2 by closing the second switch 817. Then, coarse adjustment is performed. After coarse tuning is completed, the second switch 817 is opened and VCTRL is precharged to VDD by closing the first switch 815. Then, the first switch 815 is opened and VCTRL drops to the voltage for automatic locking.

Fig. 8B shows another block diagram of an SS-PLL801 with coarse tuning, according to one embodiment. Referring to FIG. 8B, SS-PLL801 includes VCO 833, SAMP 835, g _m Stage device 837, resistor 839, first capacitor 841, second capacitor 843, first switch 845, and second switch 847. The resistor 839, the first capacitor 841, and the second capacitor 843 form a low-pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. FCAL LD 849, DCNT 851, and PLL 853 are connected to SS-PLL 801. FCAL LD 849 and DCNT 851 may configure a coarse tuner.

VCO 833 includes a first input, a second input, and an output. SAMP 835 includes a first input connected to the output of VCO 833, a second input, a first output, and a second output. g _m Stage device 837 includes a positive input connected to a first output of SAMP 835, a negative input connected to a second output of SAMP 835, and an output that generates a control voltage VCTRL connected to a first input of VCO 833. A resistor 839 is connected at g _m Between the output of the stage device 837 and the first capacitor 841. The first capacitor 841 is connected between the resistor 839 and the ground potential. A second capacitor 843 is connected to g _m Between the output of stage device 837 and ground potential. First switch 845 is connected to g _m Between the output of stage device 837 and ground potential. A second switch 847 is connected to g _m Between the output of stage device 837 and one-half of the power supply (e.g., VDD/2). During FCAL, switch 847 closes to set VCTRL to VDD/2. After FCAL is complete, switch 847 is opened. FCAL LD 849 includes an input and an output connected to a second input of VCO 833. DCNT 851 includes an input connected to the output of VCO 833 and an output connected to the input of FCAL LD 849. PLL 853 has an output connected to a second input of SAMP 835.

A coarse tuning scheme is added to first select the correct frequency sub-range of the VCO 833 and then perform an automatic search as described above. Coarse tuning is achieved by searching for DCNT 851 and FCAL LD 849. SS-PLL801 includes DCNT 851 and FCAL LD 849 for providing coarse tuning for VCO 833. First, VCTRL is precharged to VDD/2 by closing the second switch 847. Then, coarse adjustment is performed. After the coarse tuning is completed, the second switch 847 is opened and VCTRL is precharged to ground by closing the first switch 845. Then, the first switch 845 is turned off and VCTRL rises to a voltage for automatic locking.

FIG. 9A shows a block diagram of an SS-PLL 901 and an FLL with coarse tuning, according to one embodiment.

Referring to FIG. 9A, SS-PLL 901 includes VCO903, SAMP 905, g _m A stage device 907, a first switch 909, a resistor 911, a first capacitor 913, a second capacitor 915, and a second switch 917. The resistor 911, the first capacitor 913, and the second capacitor 915 form a low-pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. The PLL 919, FB DIV 921, PFD 923, CP 925, second switch 927, Comparator (COMP)929, and FCAL LD 931 are connected to the SS-PLL 901. The PLL 919, FB DIV 921, PFD 923, CP 925, second switch 927, COMP 929, and FCAL LD 931 may configure a coarse tuner.

VCO903 comprises a first input, a second input, and an output. SAMP 905 includes a first input connected to the output of VCO903, a second input, a first output, and a second output. g _m Stage device 907 includes a positive input connected to a first output of SAMP 905, a negative input connected to a second output of SAMP 905, and an output. First switch 909 is connected at g _m Between the output of the stage device 907 and the first input of the VCO903, where VCTRL is generated where the first switch 909 is connected to the VCO 903. A resistor 911 is connected between the first input of the VCO903 and the first capacitor 913. The first capacitor 913 is connected between the resistor 911 and the ground potential. A second capacitor 915 is connected between the first input of the VCO903 and ground. The second switch 917 is connected between a power supply voltage (e.g., VDD) and the first input of the VCO 903. PLL 919 has an output connected to a second input of SAMP 905.

FB DIV 921 includes an input connected to the output of VCO903, and an output. PFD 923 includes an input connected to the output of FB DIV 921, and an output. CP 925 includes an input connected to the output of PDF 923, and an output. A second switch 927 is connected between the output of the CP 925 and the first input of the VCO 903. The COMP 929 includes a first input for receiving a high voltage threshold VH, a second input for receiving a low voltage threshold VL, a third input connected to the first input of the VCO903, and an output. FCAL LD 931 includes an input connected to the output of COMP 929 and an output connected to the second input of VCO 903.

Coarse tuning is achieved in the FLL loop by COMP 929 and FCAL LD 931. After the coarse tuning is completed, VCTRL is precharged to VDD to perform an automatic search for SS-PLL lock acquisition.

Fig. 9B shows another block diagram of the SS-PLL 901 and the FLL with coarse tuning, according to one embodiment.

Referring to FIG. 9B, SS-PLL 901 includes VCO 933, SAMP 935, g _m A stage device 937, a first switch 939, a resistor 941, a first capacitor 943, a second capacitor 945, and a second switch 947. The resistor 941, the first capacitor 943, and the second capacitor 945 form a low pass filter. However, the present disclosure is not limited to this type of low pass filter, and any other type of low pass filter may be implemented without departing from the scope of the present disclosure. PLL949, FB DIV 951, PFD 953, CP 955, second switch 957, COMP 959, and FCAL LD 961 are connected to SS-PLL 901. The PLL949, FB DIV 951, PFD 953, CP 955, second switch 957, COMP 959, and FCAL LD 961 may configure a coarse tuner.

VCO 933 includes a first input, a second input, and an output. SAMP 935 includes a first input connected to the output of VCO 933, a second input, a first output, and a second output. g _m Stage device 937 includes a positive input connected to a first output of SAMP 935, a negative input connected to a second output of SAMP 935, and an output. A first switch 939 is connected at g _m Between the output of the stage device 937 and the first input of the VCO 933, VCTRL is generated at a position where the first switch 939 is connected to the VCO 933. A resistor 941 is connected between the first input of the VCO 933 and the first capacitor 943. A first capacitor 943 is connected between the resistor 941 and ground potential. The second capacitor 945 is connected between the first input of the VCO 933 and ground. A second switch 947 is connected between ground and the first input of VCO 933. PLL949 has an output connected to a second input of SAMP 935.

FB DIV 951 includes an input connected to the output of VCO 933, and an output. The PFD 953 includes an input connected to the output of FB DIV 951, and an output. CP 955 includes an input connected to the output of PFD 953, and an output. A second switch 957 is connected between the output of the CP 955 and a first input of the VCO 933. COMP 959 includes a first input for receiving a high voltage threshold VH, a second input for receiving a low voltage threshold VL, a third input connected to the first input of VCO 933, and an output. FCAL LD 961 includes an input connected to the output of COMP 959 and an output connected to a second input of VCO 933.

Coarse tuning is achieved in the FLL loop by COMP 959 and FCAL LD 961. After coarse tuning is complete, VCTRL is precharged to ground to automatically search for SS-PLL lock acquisition.

The digital counter based search or FLL loop can operate independently to accomplish frequency acquisition before switching to the SS-PLL. The benefits of adding an automatic search are: (1) the requirement for how close the frequency lock must be to the final frequency is relaxed; (2) the higher resistance to switching transients/disturbances from the digital counter/FLL to the SS-PLL ensures SS-PLL locking as long as the coarse tuning selects the correct harmonic frequency sub-range of the VCO. The SS-PLL can lock in this way as long as there is only one harmonic of the reference frequency within the selected sub-range. This relaxes the VCO LSB design, which is challenging especially in the tens of GHz range for mmWave applications with a wide tuning range.

FIG. 10A illustrates g for an SS-PLL with current bleeding according to one embodiment _m Illustration of stage device 207.

Referring to FIGS. 10A, g _m Stage device 207 includes a first PMOSFET 1001, a first NMOSFET 1003, a second PMOSFET 1005, a second NMOSFET 1007, a current source 1009, and a bleeding current source 1011.

The first PMOSFET 1001 includes a source for receiving a positive voltageA gate to which SmpP is input, and a drain. The first NMOSFET 1003 includes a drain connected to the drain of the first PMOSFET 1001, a gate connected to the drain of the first PMOSFET 1001, and a source connected to ground potential. The second PMOSFET 1005 includes a source, a gate for receiving a negative input SmpM, and a drain. The second NMOSFET 1007 includes a drain connected to the drain of the second PMOSFET 1005, a gate connected to the drain of the first PMOSFET 1001, and a source connected to ground potential, wherein the drain of the second NMOSFET 1007 provides the control voltage VCTRL. A current source 1009 is connected between a power supply (e.g., VDD) and the sources of the first and

second PMOSFETs

1001 and 1005, and delivers a current I _gm . A bleed current source 1011 is connected between VDD and the drain of the second NMOSFET 1007 and bleeds a bleed current I _bleed 。

The bleeder current source 1011 is an actual current source, except for the precharge circuit. Discharging current source 1011 from g _m The output node of stage device 207 draws/pulls (sink/source) additional current, thus g _m The stage device 207 must provide equal amounts of current in opposite directions in order to achieve zero net output current for the PLL lock condition. Thus, g _m The input of the stage device 207 must carry an input voltage instead of a zero input to support this current, which is commonly referred to as an input offset voltage. By manually controlling the input offset voltage, it is possible to operate at g _m The output operating point is adjusted in the presence of zero voltage at the input of stage device 207. Thus, g _m The output voltage range of the stage device 207 is extended where the SS-PLL lock state can be searched.

FIG. 10B shows g for an SS-PLL with current bleeding according to one embodiment _m Another view of stage device 207.

Referring to FIG. 10B, g _m The stage device 207 includes a first PMOSFET 1021, a first NMOSFET 1023, a second PMOSFET 1025, a second NMOSFET 1027, a current source 1029, a first bleed current source 1031, and a second bleed current source 1033.

The first PMOSFET 1021 includes a source, a gate for receiving the positive input SmpP, and a drain. The first NMOSFET 1023 includes a drain connected to the drain of the first PMOSFET 1021, a first PM connectedA gate of a drain of the OSFET 1021, and a source connected to ground potential. The second PMOSFET 1025 comprises a source, a gate for receiving a negative input SmpM, and a drain. The second NMOSFET 1027 includes a drain connected to the drain of the second PMOSFET 1025, a gate connected to the drain of the first PMOSFET 1021, and a source connected to ground, where the drain of the second NMOSFET 1027 provides the control voltage VCTRL. A current source 1029 is connected between a power supply (e.g., VDD) and the sources of the first and

second PMOSFETs

1021, 1025 and delivers a current I _gm . A first bleed current source 1031 is connected between VDD and the drain of the second NMOSFET 1027 and bleeds a bleed current I _bleed1 . A second bleed current source 1033 is connected between the ground potential and the drain of the second NMOSFET 1027 and bleeds a bleed current I _bleed2 。

The first and second bleed

current sources

1031, 1033 are actual current sources, except for the pre-charge circuit. The first and second bleeding

current sources

1031, 1033 from g _m The output node of stage 207 draws/pulls additional current such that g _m The stage device 207 must provide equal amounts of current in opposite directions in order to achieve zero net output current for the PLL lock condition. Thus, g _m The input of the stage device 207 must carry an input voltage instead of a zero input to support current, which is commonly referred to as an input offset voltage. By manually controlling the input offset voltage, it is possible to operate at g _m The output operating point is adjusted in the presence of zero voltage at the input of the stage device 207. Thus, g _m The output voltage range of the stage device 207 is extended where the SS-PLL lock state can be searched.

FIG. 10C shows g of an SS-PLL with current bleeding according to one embodiment _m Another view of stage device 207.

Referring to FIG. 10C, g _m The stage device 207 includes a first NMOSFET 1041, a first PMOSFET 1043, a second NMOSFET 1045, a second PMOSFET 1047, a current source 1049, a first bleed current source 1051, and a second bleed current source 1053.

The first NMOSFET 1041 includes a source, a gate for receiving the positive input SmpP, and a drain. The first PMOSFET 1043 includes a connectionA drain connected to the drain of the first NMOSFET 1041, a gate connected to the drain of the first NMOSFET 1041, and a source connected to a power supply (e.g., VDD). The second NMOSFET 1045 includes a source, a gate for receiving the negative input SmpM, and a drain. The second PMOSFET 1047 includes a drain electrode connected to the drain electrode of the second NMOSFET 1045, a gate electrode connected to the drain electrode of the first NMOSFET 1041, and a source electrode connected to a power source (e.g., VDD), wherein the drain electrode 1047 of the second PMOSFET provides the control voltage VCTRL. A current source 1049 connected between ground potential and the sources of the first NMOSFET 1041 and the second NMOSFET 1045 and delivering a current I _gm . The first bleed current source 1051 is connected between VDD and the drain of the second PMOSFET 1047, and bleeds a bleed current I _bleed1 . The second bleed current source 1053 is connected between the ground potential and the drain of the second PMOSFET 1047, and bleeds a bleed current I _bleed2 。

The first bleeding current source 1051 and the second bleeding current source 1053 are actual current sources except for the precharge circuit. The first and second bleed

current sources

1051 and 1053 are driven from g _m The output node of stage 207 draws/pulls additional current such that g _m Stage 207 must provide equal amounts of current in opposite directions to achieve zero net output current for the PLL lock condition. Thus, g _m The input of the stage device 207 must carry an input voltage instead of a zero input to support this current, which is commonly referred to as an input offset voltage. By manually controlling the input offset voltage, it is possible to operate at g _m The output operating point is adjusted in the presence of zero voltage at the input of stage device 207. Thus, g _m The output voltage range of the stage device 207 is extended where the SS-PLL lock state can be searched.

Can pass through g _m Offset compensation of the stage devices extends the locking range of the SS-PLL. The acquisition range of the automatic search is between VDD and g _m The operating point of stage device 207 minus the SSPD lock-in range. G caused by mismatch _m The input offset of stage device 207 may be g _m The output operating point is driven to a higher voltage, which reduces the SS-PLL locking range. Some offset control may be added to mitigate mismatch. Adding current bleeding tog _m The output of stage device 207. G can be adjusted by adding bleed current to extend the locking range _m The operating point of the output of the stage device 207 is controlled below, for example, 0.2V.

The SS-PLL lock for a VCO with a high reference frequency (e.g., 6GHz) and a tuning range less than the reference frequency (e.g., from 15GHz to 21GHz), there may be only one harmonic solution (e.g., 3 times the harmonic) for the VCO tuning range. The apparatus and method of the present invention can be used for frequency locking with FLL/digital counters. However, this embodiment would be more robust without requiring the VCO to have very fine resolution or strict frequency accuracy prior to switching to the SS-PLL, and would be more resistant to frequency transients/disturbances or charge redistribution prior to switching to the SS-PLL.

According to one embodiment, an SS-PLL for enabling SS-PLL locking includes g within the SS-PLL _m Stage device, connection at g _m A switch between the output of the stage device and an operating supply Voltage (VDD), wherein the switch is initially closed to couple g _m The output voltage of the stage device is precharged to VDD. Then, when g is _m When the difference between the two input voltages of the stage device averages zero volts, the switch is opened to allow g _m The output voltage of the stage device drops to its operating voltage.

According to one embodiment, g is a differential input stage with NMOSFET _m The stage device generates a switch at an output node of the control voltage VCTRL, which is precharged to a desired voltage (e.g., 0V) by closing the switch. The switch is then opened to allow VCTRL to rise to the lock-out voltage.

Fig. 11 illustrates a flow diagram of a method of providing automatic search for SS-PLL lock acquisition, according to one embodiment.

Referring to fig. 11, at 1101, a reference signal for a PLL is generated. At 1103, a Local Oscillation (LO) signal is generated by the VCO. At 1105, the difference between the LO signal and the reference signal is determined by a sampler connected to the VCO and the PLL. At 1107, from g connected to the sampler _m The stage device generates an output for changing the frequency of the LO signal.

The resistor is connected to g _m Stage deviceA first capacitor connected between the resistor and ground potential and a second capacitor connected between g _m Between the stage device and ground potential. g _m The output of the stage device may be precharged through a switch connected between the gm stage device and a supply Voltage (VDD).

In an embodiment, g may be _m The stage devices are precharged to VDD and a coarse tune of the VCO may be performed. After the coarse tuning is completed, the coarse tuning is completed by connecting at g _m A second switch pair g between the stage device and a second supply voltage different from VDD (e.g., VDD/2) _m The output of the stage device is precharged.

The coarse tuning of the VCO may be performed by a digital counter connected to the VCO, which counts the period of the LO signal, and FCAL logic connected between the digital counter and the VCO, which divides the tuning range of the LO signal such that the tuning range includes only one harmonic of the reference signal.

An electronic device according to various embodiments may be one of various types of electronic devices. The electronic device may comprise, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to various embodiments, the electronic device is not limited to those described above.

It should be understood that various embodiments of the present disclosure and terms used therein are not intended to limit technical features set forth herein to particular embodiments, but include various changes, equivalents, or substitutions for corresponding embodiments. With respect to the description of the figures, like reference numerals may be used to refer to like or related elements. It should be understood that the singular form of a noun corresponding to an item may include one or more things unless the relevant context clearly dictates otherwise. As used herein, each phrase such as "a or B," "at least one of a and B," "at least one of a or B," "A, B or C," "at least one of A, B or C," and "at least one of A, B or C" may include any and all possible combinations of the items listed together in the respective one of the phrases. As used herein, terms such as "first" and "second" may be used to simply distinguish the corresponding component from another component and not otherwise limit the components (e.g., importance or order). It will be understood that if an element (e.g., a first element) is referred to as being "coupled to," "coupled to," coupled with, "connected with," or "connected to" another element (e.g., a second element), with or without the terms "operable" or "communicable", it means that the element can be directly (e.g., wired), wirelessly, or coupled with the other element (e.g., the second element) via the third element.

As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms, such as "logic," logic block, "" component, "or" circuit. A module may be a single integral component or a minimal unit or portion thereof adapted to perform one or more functions. For example, the modules may be implemented in the form of Application Specific Integrated Circuits (ASICs).

The various embodiments set forth herein may be implemented as software comprising one or more instructions stored in a machine-readable storage medium. For example, a processor of a machine may invoke and execute at least one of one or more instructions stored in a storage medium with or without one or more other components under the control of the processor. This allows the machine to be operated to perform at least one function in accordance with the at least one instruction called. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Where the term "non-transitory" simply means that the storage medium is a tangible device and does not include a signal (e.g., an electromagnetic wave), the term does not distinguish between the case where data is semi-permanently stored on the storage medium and the case where data is temporarily stored on the storage medium.

Methods according to various embodiments of the present disclosure may be includedAnd provided in a computer program product. The computer program product may be used as a product for conducting transactions between sellers and buyers. The computer program product may be distributed in the form of a machine-readable storage medium, such as a compact disc read only memory (CD-ROM), or via an application store, such as a PlayStore ^TM ) The computer program product is online (e.g. downloaded or uploaded) or distributed directly between two user devices (e.g. smartphones). If distributed online, at least a portion of the computer program product may be temporarily generated or at least temporarily stored in a machine-readable storage medium, such as a memory of a manufacturer server, a server of an application store, or a relay server.

According to various embodiments, each of the above-described components (e.g., modules or programs) may comprise a single entity or multiple entities. One or more of the above components may be omitted, or one or more other components may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In such a case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as the functions performed by the corresponding component in the plurality of components prior to integration. Operations performed by a module, program, or another component may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more operations may be performed in a different order or omitted, or one or more other operations may be added.

While specific embodiments of the present disclosure have been described in the detailed description thereof, the present disclosure may be modified in various forms without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure should be determined not only based on the described embodiments, but also based on the appended claims and their equivalents.

Claims

1. An apparatus, comprising:

a phase-locked loop (PLL) configured to generate a reference signal;

a downsampling phase-locked loop (SS-PLL) connected to the PLL and configured to downsample the reference signal; and

a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs averages zero.

2. The apparatus of claim 1, wherein the first pre-charge circuit connects the SS-PLL to a first supply voltage VDD.

3. The apparatus of claim 1, wherein the first pre-charge circuit connects the SS-PLL to a ground potential.

4. The apparatus of claim 2, further comprising: a second pre-charge circuit connected between a sampling device of the SS-PLL and a second power supply voltage less than the first power supply voltage VDD.

5. The apparatus of claim 1, wherein the SS-PLL comprises:

a voltage controlled oscillator, VCO, configured to generate a local oscillation, LO, signal;

the sampling device connected to the VCO and the PLL and configured to output a difference between the LO signal and the reference signal;

transconductance g _m A stage device connected to the sampling device and configured to generate an output for varying the frequency of the LO signal; and

a low pass filter connected to the g _m And (4) stages.

6. The apparatus of claim 1, further comprising: a coarse timer connected to the VCO.

7. The apparatus of claim 5, wherein the g _m The stage device includes:

a current source including a first terminal and a second terminal connected to a supply voltage VDD;

a first p-channel metal oxide semiconductor field effect transistor (PMOSFET) comprising a drain, a gate connected to the first output of the sampling device, and a source connected to the second terminal of the current source;

a second PMOSFET comprising a drain, a gate connected to the second output of the sampling device, and a source connected to the second terminal of the current source;

a first n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) comprising a drain connected to the drain of the first PMOSFET, a gate connected to the drain of the first PMOSFET, and a source connected to a ground potential; and

a second NMOSFET including a drain connected to the drain of the second PMOSFET, a gate connected to the gate of the first NMOSFET, and a source connected to a ground potential.

8. The apparatus of claim 5, wherein the g _m The stage device includes:

a current source comprising a first terminal and a second terminal connected to a ground potential;

a first n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) comprising a drain, a gate connected to the first output of the sampling device, and a source connected to the second terminal of the current source;

a second NMOSFET comprising a drain, a gate connected to the second output of the sampling device, and a source connected to the second terminal of the current source;

a first p-channel metal oxide semiconductor field effect transistor (PMOSFET) including a drain connected to the drain of the first NMOSFET, a gate connected to the drain of the first NMOSFET, and a source connected to a supply voltage VDD; and

a second PMOSFET including a drain connected to the drain of the second NMOSFET, a gate connected to the gate of the first PMOSFET, and a source connected to VDD.

9. The apparatus of claim 5, further comprising: a source of bleed current comprising a voltage source connected to the supply voltage VDDA first terminal and a second terminal connected to the g _m A second terminal of the output of the stage.

10. The apparatus of claim 5, further comprising: a source of leakage current including a first terminal connected to ground potential and connected to the g _m A second terminal of the output of the stage.

11. An apparatus, comprising:

a phase-locked loop (PLL) configured to generate a reference signal;

a downsampling phase-locked loop (SS-PLL) connected to the PLL and configured to downsample the reference signal;

a first pre-charge circuit connected to a sampling device of the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs averages zero;

a frequency locked loop FLL connected to the SS-PLL;

a switch connected between the FLL and an output of the SS-PLL; and

a coarse tuner connected between an output of the SS-PLL and an input of the SS-PLL.

12. The apparatus of claim 11, wherein the first pre-charge circuit connects the SS-PLL to a supply voltage VDD.

13. The apparatus of claim 11, wherein the first pre-charge circuit connects the SS-PLL to a ground potential.

14. A method, comprising:

generating a reference signal by a Phase Locked Loop (PLL);

-down-sampling said reference signal by a down-sampling phase locked loop SS-PLL connected to said PLL; and

the output voltage of the SS-PLL is transitioned to an operating voltage by a first pre-charge circuit of a sampling device connected to the SS-PLL to indicate that the difference between the two voltage inputs averages to zero.

15. The method of claim 14, wherein the first pre-charge circuit connects the SS-PLL to a first supply voltage VDD.

16. The method of claim 14, wherein the first pre-charge circuit connects the SS-PLL to a ground potential.

17. The method of claim 15, further comprising: the output voltage of the SS-PLL is precharged by a second precharge circuit connected between a sampling device of the SS-PLL and a second supply voltage less than the first supply voltage VDD.

18. The method of claim 14, wherein the SS-PLL comprises:

a low pass filter connected to the g _m And (4) stages.

19. The method of claim 14, further comprising coarsely tuning the SS-PLL by a coarse tuner coupled to the VCO.

20. The method of claim 18, wherein the g is _m The stage device includes:

21. The method of claim 18, wherein the g is _m The stage device includes:

22. The method of claim 18, further comprising bleeding a current source from the g _m A stage device for bleeding current, the source of the bleeding current comprising a first terminal connected to a supply voltage VDD and a second terminal connected to the g _m A second terminal of the output of the stage.

23. The method of claim 18, further comprising bleeding a current source from the g _m A stage device for bleeding current, the source of the bleed current comprising a first terminal connected to ground potential and a second terminal connected to the ground potential _m A second terminal of the output of the stage.

24. A method, comprising:

generating a reference signal by a Phase Locked Loop (PLL);

-down-sampling said reference signal by a down-sampling phase locked loop SS-PLL connected to said PLL;

transitioning, by a first pre-charge circuit of a sampling device connected to the SS-PLL, an output voltage of the SS-PLL to an operating voltage to indicate that a difference between two voltage inputs averages to zero;

locking, by a frequency-locked loop FLL connected to the SS-PLL, a frequency of the SS-PLL;

switching an output of the SS-PLL to the FLL by a switch connected between the FLL and the output of the SS-PLL; and

the SS-PLL is coarsely tuned by a coarse tuner connected between the output of the SS-PLL and the input of the SS-PLL.

25. The method of claim 24, wherein the first pre-charge connects the SS-PLL to a supply voltage VDD.

26. The method of claim 24, wherein the first pre-charge circuit connects the SS-PLL to a ground potential.