CN111833738A

CN111833738A - Array substrate, display panel and display device

Info

Publication number: CN111833738A
Application number: CN202010460870.2A
Authority: CN
Inventors: 许传志; 张露; 谢正芳
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2020-05-27
Filing date: 2020-05-27
Publication date: 2020-10-27
Anticipated expiration: 2040-05-27
Also published as: CN111833738B

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate is provided with a first area, a second area and a transition area, wherein the second area is at least partially arranged around the first area, the transition area is positioned between the first area and the second area, the first area is provided with more than two light transmission areas which are arranged at intervals through a middle area in the first direction, the light transmittance of the light transmission areas is greater than that of the second area, the array substrate comprises a first pixel circuit, a second pixel circuit and first to third groups of signal lines, and any two first signal lines in the first group of signal lines are electrically connected with each other. According to the embodiment of the invention, the display uniformity can be improved.

Description

Array substrate, display panel and display device

Technical Field

The invention relates to the field of display, in particular to an array substrate, a display panel and a display device.

Background

With the rapid development of electronic devices, the demand of users for display screens is more and more personalized. For example, on electronic devices such as mobile phones and tablet computers, users want to integrate a plurality of front light sensing components on one side of a display panel to meet higher front shooting requirements.

In some embodiments, a plurality of slots (notches) or openings may be disposed on the electronic device, and external light may enter the photosensitive element located below the screen through the slots or openings on the screen. In other embodiments, a plurality of light-transmitting areas may be disposed on the electronic device, and the photosensitive assembly is correspondingly disposed on the back of the light-transmitting areas, so that full-screen display of the electronic device is achieved under the condition that the photosensitive assembly normally works.

Due to the existence of a plurality of slotted or perforated areas or a plurality of light-transmitting areas, the load of the signal lines in the row direction or the column direction corresponding to the areas is inconsistent with the load of the signal lines in other areas of the display screen, and the uniformity of display of different areas of the display screen is influenced.

Disclosure of Invention

The embodiment of the invention provides an array substrate, a display panel and a display device, aiming at improving the consistency of signal line loads of all areas and further improving the display uniformity.

In a first aspect, an embodiment of the present invention provides an array substrate, which includes a first region, a second region, and a transition region, where the second region is at least partially disposed around the first region, the transition region is located between the first region and the second region, the first region includes two or more light-transmitting regions spaced apart from each other in a first direction through a middle region, and a light transmittance of the light-transmitting regions is greater than a light transmittance of the second region, the array substrate includes:

the first pixel circuits are arranged in the transition region and the middle region;

a plurality of second pixel circuits disposed in the second region;

at least one first group of signal lines arranged in the middle area, wherein each first signal line in the first group of signal lines extends along a first direction and is electrically connected with the first pixel circuit;

the second group of signal lines are positioned on at least one side of the first area in the first direction, each second signal line in the second group of signal lines extends along the first direction and is electrically connected with the second pixel circuit, and part of the second signal lines extends to the transition area and is electrically connected with the first pixel circuit in the transition area;

a third group of signal lines arranged in the second region and positioned on at least one side of the first region in the second direction, wherein each third signal line in the third group of signal lines extends along the first direction and is electrically connected with the second pixel circuit;

wherein any two first signal lines in the first group of signal lines are electrically connected with each other.

In a possible implementation manner of the first aspect, the array substrate further includes a signal bus located at an edge of the array substrate in a first direction and extending along a second direction intersecting the first direction, and the first signal line, the second signal line, and the third signal line are all electrically connected to the signal bus;

preferably, the array substrate further includes a first connection line, and a first signal line of the first group of signal lines is electrically connected to the signal bus line through the first connection line.

In a possible implementation manner of the first aspect, any two adjacent first signal lines in the first group of signal lines are connected in series with each other.

In a possible implementation manner of the first aspect, at least two adjacent first signal lines in the first group of signal lines are connected in parallel, and the first signal lines connected in parallel are connected in series with the adjacent first signal lines.

In a possible implementation manner of the first aspect, in the first group of signal lines, the first signal lines are connected in parallel with each other;

preferably, the first signal lines are connected in parallel by a second connecting line extending along the second direction;

preferably, the second connecting line passes through a center point of the intermediate region.

In one possible implementation manner of the first aspect, one of the plurality of second signal lines is multiplexed as the first connection line.

In a possible implementation manner of the first aspect, in the second direction, the array substrate includes an upper edge and a lower edge which are opposite to each other, the first region is disposed near the upper edge of the array substrate, and one of the second signal lines, which is closest to the upper edge, is multiplexed as the first connection line.

In a possible implementation manner of the first aspect, the signal buses include a first signal bus and a second signal bus, and the first signal bus and the second signal bus are respectively located at one edge of the array substrate in the first direction;

each second signal line on one side of the first area is electrically connected with the first signal bus, and each second signal line on the other side of the first area is electrically connected with the second signal bus;

one end of each third signal wire is electrically connected with the first signal bus, and the other end of each third signal wire is electrically connected with the second signal bus;

the first connecting wire is electrically connected with the first signal bus and the second signal bus at the same time.

In a second aspect, an embodiment of the present invention provides a display panel, which includes the array substrate according to any one of the embodiments of the first aspect.

In a third aspect, an embodiment of the present invention provides a display device, which includes the display panel according to any one of the second aspect.

According to the array substrate, the display panel and the display device provided by the embodiment of the invention, the light transmittance of the light-transmitting area is greater than that of the second area, the light-transmitting area can be a slotted area or a slotted area, and the photosensitive assembly can be integrated in the slot or the hole. Or, can be at the integrated photosensitive assembly in the back in printing opacity district, realize for example that the screen of the photosensitive assembly of camera is integrated down, the printing opacity district can show the picture simultaneously, improves the display area of display screen, realizes comprehensive screen design.

The array substrate provided by the embodiment of the invention is provided with a first area, a second area and a transition area, wherein the first area comprises more than two light-transmitting areas which are arranged at intervals through a middle area in a first direction, the light-transmitting areas can display pictures, and first pixel circuits corresponding to the light-transmitting areas are arranged in the middle area and the transition area, so that the light transmittance of the light-transmitting areas can be improved.

The array substrate comprises a first group of signal lines, a second group of signal lines and a third group of signal lines, wherein the second group of signal lines are arranged in the second area and are positioned on at least one side of the first area in the first direction, each second signal line in the second group of signal lines extends along the first direction and is electrically connected with the second pixel circuit, and part of the second signal lines extends to the transition area and is electrically connected with the first pixel circuit in the transition area. The third group of signal lines are arranged in the second area and are positioned on at least one side of the first area in the second direction, and each third signal line in the third group of signal lines extends along the first direction and is electrically connected with the second pixel circuit. The middle area comprises at least one first group of signal lines, each first signal line in the first group of signal lines extends along the first direction and is electrically connected with the first pixel circuit, and any two first signal lines in the first group of signal lines are electrically connected with each other.

The data lines of the array substrate extend along the second direction and are insulated and crossed with the first signal lines, the second signal lines and the third signal lines extending along the first direction, signals of the data lines are changed in real time, small capacitors are formed among the first signal lines, the second signal lines, the third signal lines and the data lines, when the first signal lines, the second signal lines and the third signal lines transmit signals to pixel circuits of the array substrate, the small capacitors formed with the data lines can be charged and discharged, and namely loads on the first signal lines, the second signal lines and the third signal lines comprise the small capacitors. Any two first signal lines in the first group of signal lines in the middle area are electrically connected with each other, namely, a plurality of small capacitors formed by the first signal lines and the data lines are connected in series, so that the load on the first signal lines is increased, the load on the first signal lines is kept consistent with the load of at least one of the second signal lines and the third signal lines in the second area as much as possible, the load consistency of the signal lines in different areas of the array substrate is further improved, and the display uniformity is improved.

Drawings

Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 illustrates a schematic top view of an array substrate according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of a pixel circuit according to an embodiment of the invention;

FIG. 3 is a schematic top view of an array substrate according to another embodiment of the present invention;

FIG. 4 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;

FIG. 5 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;

FIG. 6 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;

FIG. 7 shows a schematic top view of a display panel according to an embodiment of the invention;

FIG. 8 shows a schematic top view of a display device according to an embodiment of the invention;

fig. 9 shows a cross-sectional view a-a in fig. 8, provided as an example.

Description of reference numerals:

100-an array substrate;

a1 — first region; a11 — light-transmitting zone; a 12-middle region; TA-transition region; a2 — second region; NA-non-display area;

11-a first pixel circuit; 12-a second pixel circuit;

20-a signal bus; 21-a first signal bus; 22-a second signal bus;

30-a first set of signal lines; 31-a first signal line; 40-a second set of signal lines; 41-second signal line; 50-a third set of signal lines; 51-a third signal line; 60-data lines;

71-a first connection line; 72-a second connecting line;

200-a display panel; 300-a photosensitive component; 1000-display device.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

In some embodiments, as shown in fig. 1, the array substrate 100 provided by the embodiment of the invention has a first region a1, a second region a2 and a transition region TA. The second region a2 is at least partially disposed around the first region a1, the transition region TA is located between the first region a1 and the second region a2, and the first region a1 has two or more light-transmitting regions a11 spaced apart by an intermediate region a12 in the first direction X, that is, the first region a1 includes at least two light-transmitting regions a11 and an intermediate region a 12. The light transmittance of the light-transmitting region a11 is greater than that of the second region a 2.

In order to improve the screen ratio and realize the full screen design, the first area a1, the second area a2 and the transition area TA are display areas. It is to be understood that the light-transmitting region a11 in the first region a1 may also be a non-display region, and the middle region a12 may be a display region, i.e., the light-transmitting region a11 is configured as a slotted region or an opening region. Illustratively, the shape of the light-transmitting area a11 may be rectangular, circular, oval, etc., which is not limited in the present invention.

Herein, the light transmittance of the light-transmitting region a11 may be 15% or more. In order to ensure that the light transmittance of the light-transmitting region a11 is greater than 15%, even greater than 40%, or even higher, the light transmittance of a portion of the functional film layer of the array substrate 100 in this embodiment may be greater than 80%, and even the light transmittance of at least a portion of the functional film layer may be greater than 90%.

The luminousness of light-transmitting area A11 is greater than the luminousness of second district A2 for array 100 can integrate photosensitive assembly at the back of light-transmitting area A11, realizes for example that the screen of the photosensitive assembly of camera is integrated down, and light-transmitting area A11 can show the picture simultaneously, improves array substrate 100's display area, realizes display device's comprehensive screen design.

The number of the light-transmitting regions a11 may be two or more. The plurality of light-transmitting regions a11 may be arranged along the first direction X, or may be arranged in an array. For example, the connecting center points of the three light-transmitting areas a11 form a triangle, or the connecting center points of the four light-transmitting areas a11 form a rectangle. The number and distribution of the light-transmitting areas a11 are not limited in the present invention.

With reference to fig. 1, the array substrate 100 may include a first pixel circuit 11, a second pixel circuit 12, a first group of signal lines 30, a second group of signal lines 40, and a third group of signal lines 50.

The plurality of first pixel circuits 11 are provided in the intermediate area a12 and the transition area TA, and drive the sub-pixels provided in the intermediate area a12 and the transition area TA to emit light for display. A plurality of second pixel circuits 12 are provided in the second area a2 for driving the sub-pixels provided in the second area a2 to emit light for display.

The second group of signal lines 40 are disposed in the second region a2 and are located on at least one side of the first region a1 in the first direction X. Illustratively, as shown in fig. 1, the first region a1 is located at about the middle of the array substrate 100 in the first direction X, and the second region a2 is disposed on both sides of the transition region TA in the first direction X, and the second group of signal lines 40 is located on both sides of the first region a1 in the first direction X. Alternatively, as shown in fig. 3, the first region a1 is close to the right edge of the array substrate 100 in the first direction X, and further, the second region a2 is absent on the right side of the transition region TA in the first direction X, and the second group signal lines 40 are located on the left side of the first region a1 in the first direction X. The specific position of the first area a1 may be set according to practical situations, and the present invention is not limited thereto.

The second group signal lines 40 include a plurality of second signal lines 41, and the second signal lines 41 extend in the first direction X and are electrically connected to the second pixel circuits 12. The plurality of second signal lines 41 are spaced from each other in the second direction Y. The area of the first region a1 is relatively small with respect to the area of the second region a2, and in order to improve the light transmittance of the light-transmitting region a11, the pixel density of the light-transmitting region a11 may be set to be smaller than the pixel density of the second region a 2. In addition, in order to avoid a significant display difference between the regions, the pixel density of the transition region TA may be set to be greater than or equal to the pixel density of the light-transmitting region a11 and less than the pixel density of the second region a 2. Therefore, the number of first pixel circuits located in the transition area TA and the intermediate area a12 is relatively small. The number of rows of the first pixel circuits 11, which are generally located in the transition area TA, is smaller than the number of rows of the second signal lines 41. Therefore, a part of the second signal line 41 may be extended to the transition area TA.

Illustratively, as shown in fig. 1, the number of the second signal lines 41 is twice the number of the rows of the first pixel circuits 11 in the transition region TA, and the odd-numbered second signal lines 41 may be extended to the transition region TA to be electrically connected to the first pixel circuits 11 in the transition region TA, and the even-numbered second signal lines 41 may be electrically connected to only the second pixel circuits 12 of the second region a 2. The number of the first pixel circuits 11 electrically connected to the second signal lines 41 is relatively small, and therefore, a difference in load between the odd-numbered second signal lines 41 and the even-numbered second signal lines 41 is negligible. In addition, since a portion of the second signal line 41 directly extends to the transition region TA and is electrically connected to the first pixel circuit 11 in the transition region TA, the signal line does not need to be additionally disposed to provide a signal to the first pixel circuit 11 in the transition region TA, so that the number and complexity of the signal lines in the array substrate can be reduced.

The third group of signal lines 50 is disposed in the second region a2 and is located on at least one side of the first region a1 in the second direction Y. Illustratively, as shown in fig. 1, the first region a1 is close to the upper edge of the array substrate 100 in the second direction Y, and thus the second region a2 is absent from the upper side of the first region a1 and the third group of signal lines 50 are located at the lower side of the first region a1 in the second direction Y. The first region a1 may be located approximately at the middle of the array substrate 100 in the second direction Y, and the second region a2 is disposed at both sides of the transition region TA in the second direction Y, and the third group of signal lines 50 are located at both sides of the first region a1 in the second direction Y. The specific position of the first area a1 may be set according to practical situations, and the present invention is not limited thereto.

The third group of signal lines 50 includes a plurality of third signal lines 51, and the third signal lines 51 extend in the first direction X and are electrically connected to the second pixel circuits 12. The plurality of third signal lines 51 are spaced from each other in the second direction Y.

The intermediate area a12 may include at least one set of the first set of signal lines 30. Each first signal line 31 in the first group of signal lines 30 extends in the first direction X and is electrically connected to the first pixel circuit 11. Any two first signal lines 31 in the first group of signal lines 30 are electrically connected to each other.

In the drawings of the present application, it is only shown that the middle area a12 includes one set of first group signal lines 30, and when the middle area a12 includes a plurality of sets of first group signal lines 30, the connection manner of the first signal lines 31 in each set of first group signal lines 30 may be the same.

The array substrate 100 further includes data lines 60, and the data lines 60 extend along the second direction Y and are arranged at intervals in the first direction X. The data line 60 is electrically connected to the second pixel circuit 12, and a part of the data line 60 is also electrically connected to the first pixel circuit 11.

In order to better understand the function of the connection manner of the first signal line 31 in the first group of signal lines 30, the pixel circuit and the first signal line 31 according to the embodiment of the present invention will be described below. In the present application, the circuit structures of the second pixel circuit 12 and the first pixel circuit 11 may be the same, or the circuit structure of the first pixel circuit 11 is simpler than the circuit structure of the second pixel circuit 12, and for example, the number of thin film transistors included in the first pixel circuit 11 may be smaller than the number of thin film transistors included in the second pixel circuit 12.

In some embodiments, the circuit structure of the pixel circuit may be any one of a 3T1C circuit, a 6T1C circuit, a 6T2C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit. Herein, the "3T 1C circuit" refers to a pixel circuit including 3 thin film transistors (T) and 1 capacitor (C) in the pixel circuit, and the other "7T 1C circuit", "7T 2C circuit", "9T 1C circuit", and the like are analogized. The second pixel circuit 12 and the first pixel circuit 11 are exemplified as the 7T1C circuit.

As shown in fig. 2, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor Cst, and an organic light emitting diode OLED. The transistors T1-T7 respectively have a control terminal, a first terminal and a second terminal. The organic light emitting diode OLED may be a sub-pixel disposed corresponding to each region.

A first terminal of the second transistor T2 is electrically connected to the data signal (Vdata) input terminal, a control terminal of the second transistor T2 is electrically connected to the second Scan signal (Scan2) input terminal, and a second terminal of the second transistor T2 is electrically connected to the first terminal of the first transistor T1 and the second terminal of the fifth transistor T5.

The first transistor T1 is a driving transistor, a first terminal of the first transistor T1 is electrically connected to the second terminal of the second transistor T2 and the second terminal of the fifth transistor T5, a second terminal of the first transistor T1 is electrically connected to the first terminal of the sixth transistor T6, and a control terminal of the first transistor T1 is electrically connected to the first terminal of the third transistor T3, the first terminal of the fourth transistor T4, and the second terminal of the capacitor Cst.

A first terminal of the third transistor T3 is electrically connected to the first terminal of the fourth transistor T4, the control terminal of the first transistor T1, and the second terminal of the capacitor Cst, a control terminal of the third transistor T3 is electrically connected to the second Scan signal (Scan2) input terminal, and a second terminal of the third transistor T3 is electrically connected to the second terminal of the first transistor T1 and the first terminal of the sixth transistor T6.

A first terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3, the control terminal of the first transistor T1, and the second terminal of the capacitor Cst, a control terminal of the fourth transistor T4 is electrically connected to the first Scan signal (Scan1) input terminal, and a second terminal of the fourth transistor T4 is electrically connected to the reference signal (Vref) input terminal.

A first terminal of the fifth transistor T5 is electrically connected to the first power supply signal (ELVDD) input terminal and the first pole of the capacitor Cst, a control terminal of the fifth transistor T5 is electrically connected to the emission control signal (EM) input terminal, and a second terminal of the fifth transistor T5 is electrically connected to the first terminal of the first transistor T1 and the second terminal of the second transistor T2.

A first terminal of the sixth transistor T6 is electrically connected to the second terminal of the first transistor T1 and the second terminal of the third transistor T3, a control terminal of the sixth transistor T6 is electrically connected to an emission control signal (EM) input terminal, and a second terminal of the sixth transistor T6 is electrically connected to the second terminal of the seventh transistor T7 and the anode of the organic light emitting diode OLED.

A first terminal of the seventh transistor T7 is electrically connected to the reference signal (Vref) input terminal and the second terminal of the fourth transistor T4, a control terminal of the seventh transistor T7 is electrically connected to the third Scan signal (Scan1) input terminal, and a second terminal of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode OLED and the second terminal of the sixth transistor T6.

The cathode of the organic light emitting diode OLED is electrically connected to the second power signal (ELVSS) input terminal.

In the present application, the first signal line 31, the second signal line 41, and the third signal line 51 may all be a reference voltage signal line (Vref line). The reference voltage signal can be provided to each pixel circuit through the reference voltage signal line so as to initialize the gate and the storage capacitor of the driving transistor in the pixel circuit, and to better write the light-emitting signal into the driving transistor. If the loads on the different reference voltage signal lines are not consistent, the initialization degrees of the pixel circuits electrically connected with the different reference voltage signal lines are different, and further, the degrees of writing the light-emitting signals into the driving transistors are not consistent, so that the display brightness of different areas is different.

In this document, the first signal line 51, the second signal line 31, and the third signal line 41 are all reference voltage signal lines as an example.

In some embodiments, the load on each signal line may be determined according to the number of pixel circuits electrically connected thereto, and particularly, the load on the signal line may be determined according to the capacitance value of the capacitor Cst in the pixel circuit. As described above, the load difference of the second signal lines 41 of the odd-numbered and even-numbered pieces is negligible. For example, the second signal line 41 is electrically connected to 10 pixel circuits, each of the 10 pixel circuits is electrically connected to the data line at the same time, the second signal line 41 extends in the first direction X, the data line extends in the second direction Y, the two lines are insulated and crossed, and the signal on the data line is changed, that is, a small capacitor C1 is formed between the second signal line 41 and the data line, and when the second signal line 41 transmits a signal to the pixel circuit electrically connected thereto, the second signal line 41 charges and discharges each small capacitor C1. Therefore, the total load value of the second signal line 41 can be equivalent to the sum of the capacitance values of the 10 capacitors Cst plus the capacitance value of the 10 small capacitors C1. Taking the example that the capacitance value of the capacitor Cst is 10 times the capacitance value of the small capacitor C1, the total load value of the second signal line 41 is the sum of the capacitance values of 11 capacitors Cst.

Taking the example where each first signal line 31 is electrically connected to 5 first pixel circuits 11, any two first signal lines 31 in the first group of signal lines 30 are electrically connected. Applicants have found that the small capacitances C1 formed by the plurality of first signal lines 31 and the data lines 60 are in series so long as the plurality of third data lines 31 are electrically connected to each other. Therefore, the load of any one of the first signal lines 31 includes not only the sum of the capacitance values of the 5 capacitors Cst plus the capacitance value of the 5 small capacitors C1, but also the sum of the capacitance values of the small capacitors C1 formed by the other first signal lines 31 and the data line 60 in the first group of signal lines 30. If the load of the first signal line 31 is consistent with the load of the second signal line 41, a small capacitance C1 of 55 is required for any one of the first signal lines 31 to make the load of the first signal line 31 reach the sum of the capacitance values of 11 capacitors Cst corresponding to the total load value of the second signal line 41. That is, the first signal line 31 needs to have an electrical connection relationship with the other 11 first signal lines 31, that is, each group of the first group signal lines 30 needs to include 12 first signal lines 31, and the 12 first signal lines 31 need to have an electrical connection relationship with each other.

Similarly, if the loads of the first signal line 31 and the third signal line 51 are to be kept the same, the number of the first pixel circuits 11 electrically connected to the first signal line 31 and the number of the second pixel circuits 12 electrically connected to the third signal line 51 may determine the number of the first signal lines 31 in the third group of data lines 30 and the number of the groups of the third group of data lines 30 included in the intermediate area a 12. And will not be described in detail herein.

According to the embodiment of the present invention, any two first signal lines 31 in the first group of signal lines 30 in the middle area a12 are electrically connected to each other, which is equivalent to connecting a plurality of small capacitors formed by the first signal lines 31 and the data lines in series, so as to increase the load on the first signal lines 31, so that the load on the first signal lines 31 is as consistent as possible with the load on at least one of the second signal lines 41 and the third signal lines 51 in the second area a2, thereby improving the consistency of the load on the signal lines in different areas of the array substrate, and improving the display uniformity.

Exemplarily, each signal line can be connected with the fixed voltage end through a lead wire respectively, so that the number of lead wires required to be arranged is large, and the narrow frame is not easy to realize. In some embodiments, referring to fig. 3, the array substrate may further include a signal bus 20, and the signal bus 20 may be located at an edge of the array substrate 100 in the first direction X and extend along a second direction Y intersecting the first direction X. The first signal line 31, the second signal line 41, and the third signal line 51 are electrically connected to the signal bus line 20. The signal bus 20 may be electrically connected to a fixed voltage terminal, and a voltage signal may be applied to each signal line through the signal bus 20. Compared with the arrangement that each signal line respectively corresponds to one lead, a plurality of leads need to occupy larger frame space, and the embodiment adopts the mode of the signal bus 20, so that the frame space can be saved, and the screen occupation ratio can be increased.

For example, the number of the first group of signal lines 30 may be multiple, and each group of the first group of signal lines 30 may be electrically connected to the signal bus 20 by one lead. In some optional embodiments, the array substrate 100 may further include a first connection line 71, and the first signal line 31 of the first group of signal lines 30 is electrically connected to the signal bus 20 through the first connection line 71. Compared with the arrangement that each group of the first group of signal lines 30 corresponds to one lead, the plurality of leads occupy a larger frame space, and the arrangement of the plurality of leads also increases the complexity of the process. As shown in fig. 1, in the present embodiment, the first connection line 71 is adopted, so that the frame space of the upper edge of the array substrate 100 can be saved, and the screen occupation ratio can be increased.

As described above, the applicant found that, as long as there is an electrical connection relationship between any two first signal lines 31 in the first group of signal lines 30, the small capacitances formed between each first signal line 31 and the data line 60 in the first group of signal lines 30 are all in a series relationship, so as to achieve the purpose of increasing the load of each first signal line 31. Therefore, the first signal lines 31 in the first group of signal lines 30 may have various connection relationships.

In some embodiments, any two adjacent first signal lines 51 in the first group of signal lines 30 are connected in series with each other. As shown in fig. 1 or fig. 3, the first signal lines 31 are connected in series in an end-to-end connection manner, that is, an "S" type routing manner is formed between the first signal lines 31.

In other embodiments, at least two adjacent first signal lines 31 in the first group of signal lines 30 are connected in parallel, and the first signal lines 31 connected in parallel are connected in series with their adjacent first signal lines 31. As shown in fig. 4, the first group of signal lines 30 includes 5 first signal lines 31, taking the uppermost one as the first example, the first and second first signal lines 31 are connected in parallel, and the first and second parallel first signal lines 31 are connected in series with the third first signal line 31; the third and fourth first signal lines 31 are connected in parallel, and the third and fourth first signal lines 31 connected in parallel are connected in series with the fifth third data line 31. The above is merely an example, and the series-parallel relationship between the first signal lines 31 in the first group of signal lines 30 may be set in other manners.

In still other embodiments, in the first group of signal lines 30, the first signal lines 31 are connected in parallel with each other. For example, as shown in fig. 5, the first signal lines 31 may be connected in parallel by a second connection line 72 extending in the second direction Y.

In the above embodiment, the first signal lines 31 in the first group of signal lines 30 are connected in series, or connected in parallel, or connected in series after being connected in parallel, so that the electrical connection relationship between any two first signal lines 31 in the first group of signal lines 30 can be easily realized, and the load on the first signal lines 31 can be increased, so that the load on the first signal lines 31 can be as consistent as possible with the load on at least one of the second signal lines 41 and the third signal lines 51 in the second area a2, and the consistency of the signal line loads in different areas of the array substrate can be improved, thereby improving the display uniformity.

Illustratively, as shown in fig. 5, the number of the light-transmitting regions a11 is two, the first pixel circuits 11 corresponding to two light-transmitting regions a11 are each partially disposed in the intermediate region a12, and the first pixel circuits 11 corresponding to two light-transmitting regions a11 may each be disposed in a position close to each light-transmitting region a 11. For example, the number of the first pixel circuits 11 per row of the middle area a12 is 2N, N is a positive integer greater than 0, the left N first pixel circuits 11 are used to drive the sub-pixels in the left light-transmitting area a11, and the right N first pixel circuits 11 are used to drive the sub-pixels in the right light-transmitting area a 11. If the second connecting line 72 is disposed on the left or right side of the first signal line 31, the line resistance thereof is increased along with the increase of the length of the signal line in the direction away from the second connecting line, which causes the line resistance corresponding to the two light-transmitting regions a11 to be inconsistent, and affects the display uniformity of the two light-transmitting regions a 11.

Thus, the second connecting line 72 may pass through the center point of the intermediate area a 12. That is, the center point of each first signal line 31 is electrically connected to the second connection line 72. The signal on the second connection line 72 is provided to the two light-transmitting areas a11 corresponding to the first pixel circuits 11 from the middle to the two sides, so that the line resistances corresponding to the two light-transmitting areas a11 are ensured to be consistent, and the brightness consistency of the display of the two light-transmitting areas a11 is ensured.

In some embodiments, the number of pixel circuits electrically connected to the third signal line 51 is much larger than the number of pixel circuits electrically connected to the first signal line 51, and the number of the first signal lines 31 included in the first group of signal lines 30 needs to be large to make the load of the first signal lines 31 and the load of the third signal line 51 consistent as much as possible. In some examples, all the first signal lines 31 included in the middle area a12 are divided into one group, that is, any two first signal lines 31 in all the first signal lines 31 included in the middle area a12 have an electrical connection relationship, and it is possible that the load on the first signal lines 31 still does not reach the load of the third signal line 51.

In some embodiments, one second signal line 41 of the plurality of second signal lines 41 may be multiplexed as the first connection line 71. In this way, the total load of the first signal line 31 also includes the load on the second signal line 41, so that the load of the first signal line 31 and the load of the third signal line 51 can be made to be consistent as much as possible, and the consistency of the load of the signal lines in different areas of the array substrate can be further improved, so as to improve the display uniformity.

In some alternative embodiments, as shown in fig. 6, in the second direction Y, the array substrate 100 includes opposite upper and lower edges, the first region a1 is disposed near the upper edge of the array substrate 100, and one second signal line 41 of the plurality of second signal lines 41 closest to the upper edge is multiplexed as the first connection line 71. In the second direction Y, the space at the position where the first area a1 is adjacent to the second area a2 is very limited, and thus, when the second signal lines 41 are multiplexed as the first connection lines 71, one lead line at the upper edge of the array substrate 100 needs to be provided to connect the second signal lines 41 with the first group of signal lines 30, and one second signal line 41 closest to the upper edge needs to be multiplexed as the first connection line 71, so that the length of the lead line can be reduced without crossing the other second signal lines 41.

As shown in fig. 3, only one signal bus 20 may be provided to reduce the cost, and one signal bus 20 only occupies one edge position of the array substrate 100, so that the narrow frame of the array substrate 100 can be further realized.

In some alternative embodiments, as shown in fig. 1, the signal bus lines 20 may include a first signal bus line 21 and a second signal bus line 22, and the first signal bus line 21 and the second signal bus line 22 are respectively located at one edge of the array substrate 100 in the first direction X. Each of the second signal lines 41 on one side of the first region a1 is electrically connected to the first signal bus 21, and each of the second signal lines 41 on the other side of the first region a1 is electrically connected to the second signal bus 22. One end of each third signal line 51 is electrically connected to the first signal bus line 21, and the other end is electrically connected to the second signal bus line 22. The first connection line 71 is electrically connected to both the first signal bus 21 and the second signal bus 22.

The line resistance on the signal lines is increasingly greater in the direction away from the signal bus. Two signal buses are adopted, signals can be simultaneously provided for the signal lines from two ends of the signal lines respectively, namely, a double-end driving mode is adopted, the line resistance difference on the signal lines can be reduced, and the uniformity of display brightness is further ensured.

As shown in fig. 7, an embodiment of the invention provides a display panel, and the display panel 200 may include the array substrate 100 in any of the embodiments. Since the display panel of the present embodiment includes the array substrate 100 of any one of the above embodiments, the display panel further has the beneficial effects of the array substrate 100 of the above embodiments, and details are not repeated herein.

The display panel 200 may be an Organic Light Emitting Diode (OLED) display panel.

In some optional embodiments, the display panel 200 may further include an encapsulation layer, and a polarizer and a cover plate located above the encapsulation layer, or the cover plate may be directly disposed above the encapsulation layer, without disposing a polarizer, or at least the cover plate may be directly disposed above the encapsulation layer in the light-transmitting region a11, without disposing a polarizer, so as to avoid the polarizer from affecting the light collection amount of the photosensitive element disposed below the light-transmitting region a11, and of course, a polarizer may also be disposed above the encapsulation layer in the light-transmitting region a 11.

As shown in fig. 8, an embodiment of the present invention further provides a display device, and the display device 1000 may include the display panel 200 of any of the above embodiments. The following description will be given taking as an example a display device of an embodiment including the display panel 200 of the above-described embodiment.

Fig. 8 is a schematic top view of a display device according to an embodiment of the present invention, and fig. 9 is a cross-sectional view taken along a line a-a of fig. 8 according to an embodiment of the present invention. In the display device of the present embodiment, the display panel 200 may be the display panel 200 of one of the above embodiments, the display panel 200 has two or more light-transmitting regions a11, and the light transmittance of the light-transmitting region a11 is greater than that of the second region a 2.

The display panel 200 includes a first surface S1 and a second surface S2 opposite to each other, wherein the first surface S1 is a display surface. The display device further includes photosensitive elements 300, the photosensitive elements 300 are located on the second surface S2 side of the display panel 200, and the positions and the number of the photosensitive elements 300 correspond to the light-transmitting regions a 11.

The photosensitive assembly 300 may be an image capturing device for capturing external image information. In this embodiment, the photosensitive assembly 300 is a Complementary Metal Oxide Semiconductor (CMOS) image capture device, and in other embodiments, the photosensitive assembly 300 may also be a Charge-coupled device (CCD) image capture device or other types of image capture devices. It is understood that the photosensitive assembly 300 may not be limited to being an image capture device, for example, in some embodiments, the photosensitive assembly 300 may also be an infrared sensor, a proximity sensor, an infrared lens, a flood sensing element, an ambient light sensor, a dot matrix projector, and the like. In addition, the display device may further integrate other components, such as a handset, a speaker, etc., on the second surface S2 of the display panel 200.

Since the display device of the present embodiment includes the display panel 200 of any one of the above embodiments, the display device also has the beneficial effects of the display panel 200 of the above embodiments, and the description thereof is omitted here.

The display device of this embodiment may include electronic devices such as a mobile phone, a tablet computer, an electronic book reader, a multimedia playing device, a wearable device, and a vehicle-mounted terminal.

In accordance with the above-described embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate having a first region, a second region and a transition region, the second region being at least partially disposed around the first region, the transition region being disposed between the first region and the second region, the first region having two or more light-transmitting regions spaced apart from each other in a first direction by an intermediate region, the light-transmitting regions having a light transmittance greater than that of the second region, the array substrate comprising:

a plurality of second pixel circuits disposed in the second region;

at least one first group of signal lines disposed in the middle region, each first signal line of the first group of signal lines extending in the first direction and electrically connected to the first pixel circuit;

a second group of signal lines located on at least one side of the first region in the first direction, each second signal line of the second group of signal lines extending in the first direction and electrically connected to the second pixel circuit, and a part of the second signal lines extending to the transition region and electrically connected to the first pixel circuit in the transition region;

a third group of signal lines disposed in the second region and located on at least one side of the first region in the second direction, each third signal line of the third group of signal lines extending in the first direction and electrically connected to the second pixel circuit;

2. The array substrate of claim 1, further comprising a signal bus located at an edge of the array substrate in the first direction and extending in a second direction intersecting the first direction, wherein the first signal line, the second signal line, and the third signal line are electrically connected to the signal bus;

3. The array substrate of claim 2, wherein any two adjacent first signal lines in the first group of signal lines are connected in series with each other.

4. The array substrate of claim 2, wherein at least two adjacent first signal lines in the first group of signal lines are connected in parallel, and the first signal lines connected in parallel are connected in series with the adjacent first signal lines.

5. The array substrate of claim 2, wherein in the first group of signal lines, the first signal lines are connected in parallel with each other;

preferably, the first signal lines are connected in parallel by a second connection line extending along the second direction;

preferably, the second connecting line passes through a center point of the middle area.

6. The array substrate of any one of claims 2 to 5, wherein one of the second signal lines is multiplexed as the first connection line.

7. The array substrate of claim 6, wherein in the second direction, the array substrate comprises an upper edge and a lower edge which are opposite to each other, the first region is disposed near the upper edge of the array substrate, and one of the second signal lines which is closest to the upper edge is multiplexed as the first connection line.

8. The array substrate of claim 1, wherein the signal bus comprises a first signal bus and a second signal bus respectively located at one edge of the array substrate in the first direction;

9. A display panel comprising the array substrate according to any one of claims 1 to 8.

10. A display device characterized by comprising the display panel according to claim 9.