CN111815973B - Signalized intersection analysis method and related equipment - Google Patents

Signalized intersection analysis method and related equipment Download PDF

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CN111815973B
CN111815973B CN202010622684.4A CN202010622684A CN111815973B CN 111815973 B CN111815973 B CN 111815973B CN 202010622684 A CN202010622684 A CN 202010622684A CN 111815973 B CN111815973 B CN 111815973B
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sequence
preset
headway
time period
signalized intersection
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CN111815973A (en
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杨双健
李福樑
张译升
高蕾
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Ping An International Smart City Technology Co Ltd
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    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/07—Controlling traffic signals
    • G08G1/081—Plural intersections under common control
    • G08G1/082—Controlling the time between beginning of the same phase of a cycle at adjacent intersections
    • G—PHYSICS
    • G08—SIGNALLING
    • G08G—TRAFFIC CONTROL SYSTEMS
    • G08G1/00—Traffic control systems for road vehicles
    • G08G1/07—Controlling traffic signals
    • G08G1/081—Plural intersections under common control
    • G08G1/083—Controlling the allocation of time between phases of a cycle

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Abstract

The invention relates to artificial intelligence and provides a signalized intersection analysis method and related equipment. The method comprises the following steps: acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection; calculating the head time distance sequence of each preset lane in each preset time period of the signalized intersection according to the passing time sequence; acquiring signal timing data of each preset lane in each preset time period at the signalized intersection; correcting and matching the signal timing data according to the passing time sequence; identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence; removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence; and calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence. The invention can improve the accuracy of the traffic capacity analysis of the signalized intersection.

Description

Signalized intersection analysis method and related equipment
Technical Field
The invention relates to the field of artificial intelligence, in particular to a signalized intersection analysis method and related equipment.
Background
Signal intersections serve as main components of urban road networks, and the overall operation efficiency of an urban road traffic system is greatly restricted. The traffic capacity is one of the most core indexes of the signalized intersection, and directly influences the bearing capacity of the whole traffic network. Therefore, how to correctly analyze and determine the traffic capacity of the signalized intersection is important, and accordingly, the signalized timing scheme is optimized, and the signalized intersection is designed or reconstructed, so that the traffic capacity of the signalized intersection is improved, and the traffic condition of the signalized intersection is improved.
The traffic capacity of a signal intersection is influenced by various aspects such as traffic flow composition, vehicle performance, driving environment, driving behavior, road traffic management conditions and the like, and accurate calculation of the traffic capacity is a very complicated problem. The existing signalized intersection traffic capacity analysis method mainly comprises a regression analysis method, a large amount of off-line data are adopted to carry out linear regression fitting, the real-time requirement cannot be met, the estimation precision is low, and an accurate analysis result cannot be obtained.
Disclosure of Invention
In view of the above, there is a need for a signalized intersection analysis method, device, computer device and storage medium, which can improve the accuracy of the signalized intersection traffic capacity analysis.
A first aspect of the present application provides a signalized intersection analysis method, including:
acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection;
calculating a vehicle headway sequence of each preset lane in each preset time period of the signalized intersection according to the vehicle passing time sequence;
acquiring signal timing data of each preset lane in each preset time period at the signalized intersection;
correcting and matching the signal timing data according to the passing time sequence;
identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence;
and calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
In another possible implementation manner, the performing the correction matching on the signal timing data according to the passing time sequence includes:
mapping the passing time sequence and the signal timing data of each preset lane in each preset time period, calculating the red light running rate of each signal stage of the preset lane in the preset time period, and calculating the total red light running rate of all the signal stages of the preset lane in the preset time period according to the red light running rate of each signal stage of the preset lane in the preset time period;
and adjusting the green light turn-on time of each preset lane in each preset time period to enable the total red light running rate of the preset lane in the preset time period to obtain the minimum value.
In another possible implementation manner, the identifying, according to the headway sequence, a saturated headway sequence of each preset lane in each preset time period at the signalized intersection includes:
calculating the difference delta e (n) of two adjacent headway distances in the headway sequence;
judging whether the expectation of the delta e (n) is 0 or not through hypothesis testing;
and if the expectation of the delta e (n) is 0, judging that the headway sequence is a saturated headway sequence.
In another possible implementation, the determining whether the expectation of Δ e (n) is 0 by hypothesis testing includes:
whether the expectation of Δ e (n) is 0 is judged by DF hypothesis test.
In another possible implementation manner, the removing abnormal data in the saturated headway sequence according to the signal timing data includes:
judging whether each headway in the saturated headway sequence is greater than or equal to the red light duration;
and if the headway is greater than or equal to the red light time length, removing the headway from the saturated headway sequence to obtain a first filtered saturated headway sequence.
In another possible implementation manner, the removing abnormal data in the saturated headway sequence according to the signal timing data further includes:
calculating a preset quantile of the first filtered saturated headway time sequence;
judging whether each headway in the first filtering saturated headway sequence is larger than or equal to the preset quantile or not;
if the headway is larger than or equal to the preset quantile, removing the headway from the first filtered saturated headway sequence to obtain a second filtered saturated headway sequence;
performing DF hypothesis test on the second filtered saturated headway sequence, and if the DF hypothesis test is passed, taking the second filtered saturated headway sequence as the target saturated headway sequence;
and if the DF hypothesis test is not passed, updating the first filtered saturated headway sequence into the second filtered saturated headway sequence and returning to the calculation of the preset quantiles of the first filtered saturated headway sequence.
In another possible implementation manner, the obtaining of the passing time sequence of each preset lane in each preset time period at the signalized intersection includes:
and acquiring the passing time sequence through an electric alarm detector of the electric alarm monitoring system.
A second aspect of the present application provides a signalized intersection analysis device, the device comprising:
the first acquisition module is used for acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection;
the first calculation module is used for calculating a vehicle headway sequence of each preset lane in each preset time period of the signalized intersection according to the vehicle passing time sequence;
the second acquisition module is used for acquiring signal timing data of each preset lane in each preset time period at the signalized intersection;
the correction module is used for correcting and matching the signal timing data according to the passing time sequence;
the identification module is used for identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
the filtering module is used for removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence;
and the second calculation module is used for calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
A third aspect of the application provides a computer device comprising a processor for implementing the signalized intersection analysis method when executing a computer program stored in a memory.
A fourth aspect of the present application provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the signalized intersection analysis method.
The method and the device solve the problem that the existing signalized intersection communication capacity analysis method cannot obtain an accurate analysis result. The invention corrects and matches the signal timing data, corrects the time deviation of the signal timing data and improves the accuracy of the analysis of the communication capacity of the signalized intersection. Due to factors such as peak preset time period, traffic light period alternation and the like, abnormal data can exist in the saturated headway, and the method and the device identify the abnormal data in the saturated headway and eliminate the abnormal data, so that the accuracy of traffic capacity analysis of the signalized intersection is further improved. The invention can obtain accurate signalized intersection analysis results.
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Fig. 1 is a flowchart of a signalized intersection analysis method according to an embodiment of the present invention.
Fig. 2 is a structural diagram of a signalized intersection analysis apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a computer device provided by an embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a detailed description of the present invention will be given below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, and the described embodiments are merely some, but not all embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Preferably, the signalized intersection analysis method of the present invention is applied to one or more computer devices. The computer device is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and the hardware includes, but is not limited to, a microprocessor, an Application Specific Integrated Circuit (ASIC), a Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded device, and the like.
The computer device can be a desktop computer, a notebook, a palm computer, a cloud server and other computing devices. The computer equipment can carry out man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch panel or voice control equipment and the like.
Example one
Fig. 1 is a flowchart of a signalized intersection analysis method according to an embodiment of the present invention. The signalized intersection analysis method is applied to computer equipment. The signalized intersection analysis method analyzes the traffic capacity of the signalized intersection.
The signalized intersection analysis method can be applied to intelligent traffic, is used for accurately analyzing the traffic capacity of signalized intersections, can optimize a signal timing scheme, design or reconstruct the signalized intersections according to the analysis result, improves the traffic capacity of the signalized intersections, and improves the traffic conditions of the signalized intersections, thereby promoting the construction of smart cities.
As shown in fig. 1, the signalized intersection analysis method includes:
101, acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection.
The preset time period and the preset lane can be set as required. In one embodiment, the preset time period is a preset time period of a traffic peak period (e.g. 7 to 9 or 17. For example, the traffic capacity at a signalized intersection of 7 a to 00 a in the morning is analyzed, and 24 preset time periods are set, each of which is 5 minutes. The preset lanes may be one or more lanes of a signalized intersection.
The passing time sequence of each preset lane at each preset time period at the signalized intersection is a time sequence formed by the time when each vehicle of the preset lane passes through the stop line of the signalized intersection at the preset time period. For example, a preset time period is 7-00-7, and a preset lane is denoted as lane 1, then the time for each vehicle on lane 1 to pass through the stop line in lane 1 of 7.
In an embodiment, the obtaining of the passing time sequence of each preset lane for each preset time period at the signalized intersection includes: and acquiring the passing time sequence through an electric alarm detector of the electric alarm monitoring system.
The electric alarm detector is arranged above a road behind a stop line of the signalized intersection, the electric alarm detector is used for collecting the time of the vehicle in each preset lane in each preset time period passing through the stop line, and the time of the vehicle in each preset lane in each preset time period passing through the stop line is formed into the vehicle passing time sequence.
In one embodiment, a detection area is arranged on the road surface close to the stop line behind the stop line, the time when the vehicle passes through the detection area is collected through an electric alarm detector, and the time when the vehicle passes through the detection area is taken as the time when the vehicle passes through the stop line.
The electric alarm detector can be arranged above the road surface 20-30 meters behind the stop line of the signalized intersection, the electric alarm detector captures the time when the vehicle passes through the detection area, and the time when the vehicle passes through the detection area is taken as the time when the vehicle passes through the stop line.
The passing time sequence of each preset lane for each preset time period can be recorded as
Figure BDA0002563582010000071
Figure BDA0002563582010000072
Wherein M (M =1, \ 8230;, M) is a slot number, N (N =1, \ 8230;, N, N + 1) is a vehicle serial number, L (L =1,2, \8230;, L) is a lane number,
Figure BDA0002563582010000073
and the time when the nth vehicle of the ith preset lane passes through the stop line is the mth preset time period.
And 102, calculating a headway sequence of each preset lane in each preset time period at the signalized intersection according to the passing time sequence.
The sequence of the headway of each preset lane in each preset time period at the signalized intersection is a sequence formed by the headways of all vehicles passing through the stop line in the preset time period in the preset lane.
The headway refers to the time difference between adjacent vehicles passing through a stop line. The headway sequence of each preset lane in each preset time period can be recorded as
Figure BDA0002563582010000074
Wherein M (M =1, \8230; M) is a preset time period, N =1, \8230; N is a vehicle serial number, L (L =1,2, \8230; L) is a lane number,
Figure BDA0002563582010000075
the time headway of the nth vehicle of the ith preset lane in the mth preset time period.
The head time distance of the nth vehicle of the ith preset lane in the mth preset time period is calculated according to the following formula:
Figure BDA0002563582010000076
wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0002563582010000077
the time when the (n + 1) th vehicle of the ith preset lane passes through the stop line for the mth preset time period,
Figure BDA0002563582010000078
and the time when the nth vehicle of the ith preset lane passes through the stop line is the mth preset time period.
And 103, acquiring signal timing data of each preset lane in each preset time period at the signalized intersection.
The signal timing data indicates the turn-on time of signal lights (red light and green light) at a signalized intersection. The signal timing data may be obtained from a signal control system.
In order to avoid mutual conflict among traffic flows in different directions, the signal control system distributes the passing time in each direction according to the traffic demands in each direction. The signal timing data of the ith preset lane in the mth preset time period can be expressed as:
Figure BDA0002563582010000081
wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0002563582010000082
the red light turn-on time of the t signal period of the ith preset lane in the mth preset time period,
Figure BDA0002563582010000083
the green light turn-on time of the T signal period of the ith preset lane in the mth preset time period is shown, and T (T =1, \8230; T) is a period number.
And 104, performing correction matching on the signal timing data according to the passing time sequence.
The acquired vehicle passing time sequence and the signal timing data usually have certain time deviation, and the deviation can influence the accuracy of the analysis result of the signalized intersection.
For example, in one embodiment, the passing time sequence is obtained from the electric police monitoring system, the signal timing data is obtained from the signal control system, and the two systems respectively have respective timing mechanisms, and the clocks of the two systems have certain deviation, so that when the passing time sequence is mapped with the corresponding signal timing data, more red light running phenomena exist, that is, more time of the vehicle passing through a stop line is concentrated in a red light time range.
In order to improve the accuracy of analysis of the signalized intersection, the signal timing data of each preset lane in each preset time period is corrected and matched.
In an embodiment, the performing a modified match on the signal timing data according to the passing time sequence includes:
mapping the passing time sequence and the signal timing data of each preset lane in each preset time period, calculating the red light running rate of each signal stage of the preset lane in the preset time period, and calculating the total red light running rate of all the signal stages of the preset lane in the preset time period according to the red light running rate of each signal stage of the preset lane in the preset time period;
and adjusting the green light turn-on time of each preset lane in each preset time period to enable the total red light running rate of the preset lane in the preset time period to obtain the minimum value.
The signal stage is divided according to the changing times of the right of way at the signalized intersection in a signal period, and the right of way has several changing times in the signal period.
The total red light running rate of all signal phases is the sum of the red light running rates of all signal phases. For example, if the signal intersection includes four signal phases, the total red light running rate is the sum of the red light running rates of the first signal phase (i.e., phase 1), the second signal phase (i.e., phase 2), the third signal phase (i.e., phase 3), and the fourth signal phase (i.e., phase 4).
Adjusting the green light turn-on time of each preset lane in each preset time period to make the total red light running rate of the preset lane in the preset time period obtain the minimum value, namely performing target optimization, and can be expressed as:
Figure BDA0002563582010000091
s.t.
0≤o s ≤C(m)
Figure BDA0002563582010000092
wherein red _ occupancy s (M) is the red light running rate of the signal stage S in the mth preset time period, M =1, \8230, M, S =1, \8230, and S is the number of signal stages, o s And C (m) represents the signal period duration of the mth preset time period. O is not less than 0 s C (m) represents that the correction quantity of the green light turn-on time of each signal stage needs to be adjusted between 0 and C (m),
Figure BDA0002563582010000093
Figure BDA0002563582010000094
the sum of the correction amounts of the turn-on time of the green lamp indicating the respective signal stages is equal to 0.
And 105, identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence.
Due to the periodic replacement of traffic light signals at the signalized intersection, the vehicles stop and go through the signalized intersection. When the red light is turned on, the vehicles close to the stop line are parked and queued, the subsequently arriving vehicles are influenced by the front queued vehicles, the speed is gradually reduced to zero, and the vehicles are added at the tail of the queuing queue. When the green light is turned on, vehicles close to the stop line start to drive away from the signalized intersection, and subsequent vehicles in line (4 th vehicle in line starts) drive away from the signalized intersection at the saturation flow rate, and the line is gradually dissipated. Therefore, from the 4 th queued vehicle to the last queued vehicle, the headway should fluctuate within the saturated headway range, and the fluctuation (error) is irregular, i.e., the errors of the headway should be independently and equally distributed, and the average value is 0.
In one embodiment, headway may be represented as:
Figure BDA0002563582010000095
wherein the content of the first and second substances,
Figure BDA0002563582010000096
the time interval is the time interval of the nth vehicle of the ith preset lane in the mth preset time period, mu is the saturated time interval, and e (n) is a random error term. Further, assume that the random error term e (n) satisfies a mean of 0 and a variance of 0
Figure BDA0002563582010000101
The variance of the saturated headway mu and the random error term e (n)
Figure BDA0002563582010000102
As the amount to be estimated, the time headway of the nth vehicle of the ith preset lane in the mth preset time period
Figure BDA0002563582010000103
Is expected to
Figure BDA0002563582010000104
Sum variance
Figure BDA0002563582010000105
Can be expressed as:
Figure BDA0002563582010000106
Figure BDA0002563582010000107
namely the acquired saturated headway sequence
Figure BDA0002563582010000108
Obedience mean is mu and variance is
Figure BDA0002563582010000109
Is normally distributed. The headway of the (n-1) th vehicle may be represented as:
Figure BDA00025635820100001010
according to
Figure BDA00025635820100001011
And
Figure BDA00025635820100001012
the relationship between two adjacent headway distances in the headway sequence can be established:
Figure BDA00025635820100001013
setting Δ e (n) = e (n) -e (n-1),
Figure BDA00025635820100001014
the expectation and variance of Δ e (n) can be expressed as:
e (Δ E (n)) = E (n) -E (n-1)) =0 equation 8
Figure BDA00025635820100001015
According to E (Δ E (n)) = E (n) -E (n-1)) =0 and
Figure BDA00025635820100001016
Figure BDA00025635820100001017
the head time interval error term difference delta e (n) of adjacent vehicles can be obtained, the mean value is 0 and the variance is
Figure BDA00025635820100001018
Is normally distributed.
Based on this, in an embodiment, the identifying, according to the headway sequence, the saturated headway sequence of each preset lane in each preset time period at the signalized intersection includes:
calculating the difference value delta e (n) of two adjacent headway distances in the headway distance sequence;
judging whether the expectation of the delta e (n) is 0 or not through hypothesis testing;
and if the expectation of the delta e (n) is 0, judging that the headway sequence is a saturated headway sequence.
In one embodiment, the expectation of Δ e (n) is determined to be 0 by the DF hypothesis test.
For better checking the headway obtained by observation
Figure BDA00025635820100001019
If the time interval is saturated, setting k (n) = delta e (n),
Figure BDA00025635820100001020
the following expression can be obtained:
Figure BDA0002563582010000111
wherein the content of the first and second substances,
Figure BDA0002563582010000112
and p is a parameter to be estimated, and is a vehicle headway sequence of the ith preset lane in the mth preset time period. Based on the formula
Figure BDA0002563582010000113
And judging whether the detected headway is the saturated headway or not by carrying out hypothesis test on whether rho is equal to 1 or not. If passing hypothesis testing, i.e.
Figure BDA0002563582010000114
Then E (Δ E (n)) = E (k (n)) =0 may be obtained, and thus, it may be possible to obtain
Figure BDA0002563582010000115
Is ready to obtainAnd the observed headway sequence is the saturated headway.
Further, the parameters ρ and k (n) are estimated using a least squares method, the estimators of which are
Figure BDA0002563582010000116
And
Figure BDA0002563582010000117
can be expressed as:
Figure BDA0002563582010000118
Figure BDA0002563582010000119
according to the theory of regression analysis,
Figure BDA00025635820100001110
obey a t distribution with a degree of freedom of (N-2), wherein
Figure BDA00025635820100001111
Is composed of
Figure BDA00025635820100001112
The smaller the standard error is, the closer the acquired headway sequence is to the real saturated headway sequence is, and the closer the estimated parameters are to the real parameters is, namely, the higher the accuracy of the estimated saturated headway is.
Figure BDA00025635820100001113
The specific expression is as follows:
Figure BDA00025635820100001114
Figure BDA00025635820100001115
Figure BDA00025635820100001116
further, according to Dickey and Fuller theory, due to the estimators
Figure BDA00025635820100001117
The statistical headway of the nth and the (n-1) th vehicles is included at the same time, and then the hypothesis test aiming at rho =1 does not satisfy the t test any more, but satisfies the DF test for this, and the DF test statistic is constructed:
Figure BDA00025635820100001118
the DF statistic constructed above obeys DF distribution, and the critical values of different confidence degrees of the DF distribution are met during hypothesis test. In the invention, when the sample amount of the headway sequence is more than 50 and the DF test statistic is [ -2.25,1.66], the test ρ =1 is assumed to be not rejected, that is, the observed headway sequence mean value can be considered as the saturated headway data.
And 106, removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence.
In the above steps, the time headway sequence checked by the DF hypothesis has a potential abnormal time headway due to factors such as a preset time period of receiving a peak, a period alternation of traffic lights, and the like. Therefore, the abnormal headway needs to be filtered, and the estimation precision of the saturated headway is ensured. Common abnormal headway includes the following situations: (1) Due to the red light time, the time interval between the vehicle passing through the stop line in the first period and the vehicle passing through the stop line in the last period is more than or equal to the red light time; (2) The green light is turned on, the vehicle is accelerated to start and leave a stop line, and the time interval of the vehicle head is larger due to the fact that the vehicle is still in an accelerated state; (3) During green light, there may also be a large headway due to random arrival of vehicles, etc.
In an embodiment, the removing abnormal data in the saturated headway sequence according to the modified and matched signal timing data includes:
judging whether each headway in the saturated headway sequence is greater than or equal to the red light duration or not;
and if the headway is greater than or equal to the red light time length, removing the headway from the saturated headway sequence to obtain a first filtered saturated headway sequence.
In an embodiment, removing abnormal data in the saturated headway sequence according to the modified and matched signal timing data further includes:
calculating a preset quantile (e.g., 85% quantile) of the first filtered saturated headway sequence;
judging whether each headway in the first filtered saturated headway sequence is larger than or equal to the preset quantile or not;
if the headway is larger than or equal to the preset quantiles, removing the headway from the first filtered saturated headway sequence to obtain a second filtered saturated headway sequence;
performing DF hypothesis test on the second filtered saturated headway sequence, and if the DF hypothesis test is passed, taking the second filtered saturated headway sequence as a target saturated headway sequence;
and if the DF hypothesis test is not passed, updating the first filtered saturated headway sequence into the second filtered saturated headway sequence and returning to the calculation of the preset quantiles of the first filtered saturated headway sequence.
And 107, calculating the traffic capacity of the signalized intersection according to the target saturated headway.
In an embodiment, an average value of the target saturated headway sequence of each preset lane in each preset time period may be calculated, and the average value is used as the target saturated headway sequence of the preset lane in the preset time period
Figure BDA0002563582010000131
According to
Figure BDA0002563582010000132
The traffic capacity of the preset lane can be obtained:
Figure BDA0002563582010000133
wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0002563582010000134
the traffic capacity of a first preset lane m in a preset time period, S is the saturation flow, t eg The effective green duration.
The unit of the traffic capacity is pcu/h,
Figure BDA0002563582010000135
the larger the value of (a), the stronger the trafficability of the signalized intersection. On the contrary, the method can be used for carrying out the following steps,
Figure BDA0002563582010000136
the smaller the value of (a), the weaker the traffic capacity of the signalized intersection.
In other embodiments, the target saturated headway sequence may be calculated in other manners according to the target saturated headway sequence
Figure BDA0002563582010000137
For example, a median of the target saturated headway sequence of each preset lane in each preset time period may be calculated, and the median is used as the target saturated headway sequence of the preset lane in the preset time period
Figure BDA0002563582010000138
According to
Figure BDA0002563582010000139
And calculating the traffic capacity of the preset lane.
The signalized intersection analysis method solves the problem that an accurate analysis result cannot be obtained by an existing signalized intersection communication capacity analysis method. The signal intersection analysis method is used for correcting and matching the signal timing data, correcting the time deviation of the signal timing data and improving the accuracy of the analysis of the communication capacity of the signal intersection. And abnormal data exist in the saturated head time interval under the factors of the peak preset time period, the traffic light period alternation and the like, and the signalized intersection analysis method identifies the abnormal data in the saturated head time interval and eliminates the abnormal data, so that the accuracy of the signalized intersection traffic capacity analysis is further improved. The signalized intersection analysis method can obtain an accurate signalized intersection analysis result.
Example two
Fig. 2 is a structural diagram of a signalized intersection analysis apparatus according to a second embodiment of the present invention. The signalized intersection analyzing device 20 is applied to computer equipment. The signalized intersection analysis device 20 analyzes the traffic capacity of the signalized intersection.
The signalized intersection analysis device 20 can be applied to intelligent traffic, is used for accurately analyzing the traffic capacity of signalized intersections, can optimize a signal timing scheme according to an analysis result, and can design or reconstruct signalized intersections, so that the traffic capacity of the signalized intersections is improved, the traffic conditions of the signalized intersections are improved, and the construction of intelligent cities is promoted.
As shown in fig. 2, the signalized intersection analyzing apparatus 20 may include a first obtaining module 201, a first calculating module 202, a second obtaining module 203, a correcting module 204, an identifying module 205, a filtering module 206, and a second calculating module 207.
The first obtaining module 201 is configured to obtain a passing time sequence of each preset lane in each preset time period at the signalized intersection.
The preset time period and the preset lane may be set as needed. In one embodiment, the preset time period is a preset time period of a traffic peak period (for example, 7 to 9 or 17. For example, the traffic capacity at a signalized intersection of 7 a to 00 a in the morning is analyzed, and 24 preset time periods are set, each preset time period being 5 minutes. The preset lanes may be one or more lanes of a signalized intersection.
The passing time sequence of each preset lane at each preset time period at the signalized intersection is a time sequence formed by the time when each vehicle of the preset lane passes through the stop line of the signalized intersection at the preset time period. For example, a preset time period is 7-00-7, and a preset lane is denoted as lane 1, then the time for each vehicle on lane 1 to pass through the stop line in lane 1 of 7.
In an embodiment, the obtaining of the passing time sequence of each preset lane at each preset time period at the signalized intersection includes: and acquiring the passing time sequence through an electric alarm detector of the electric alarm monitoring system.
The electric alarm detector is arranged above a road behind a stop line of the signalized intersection, the electric alarm detector is used for collecting the time of the vehicle in each preset lane in each preset time period passing through the stop line, and the time of the vehicle in each preset lane in each preset time period passing through the stop line is formed into the vehicle passing time sequence.
In one embodiment, a detection area is arranged on the road surface close to the stop line behind the stop line, the time when the vehicle passes through the detection area is collected through an electric alarm detector, and the time when the vehicle passes through the detection area is taken as the time when the vehicle passes through the stop line.
The electric alarm detector can be arranged above the road surface 20-30 meters behind the stop line of the signalized intersection, and the electric alarm detector captures the time when the vehicle passes through the detection area, and takes the time when the vehicle passes through the detection area as the time when the vehicle passes through the stop line.
The passing time sequence of each preset lane for each preset time period can be recorded as
Figure BDA0002563582010000151
Figure BDA0002563582010000152
Wherein M (M =1, \8230;, M) is a time slot number, N (N =1, \8230;, N, N + 1) is a vehicle serial number, L (L =1,2, \8230;, L) is a lane number,
Figure BDA0002563582010000153
and the time when the nth vehicle of the ith preset lane passes through the stop line is the mth preset time period.
The first calculating module 202 is configured to calculate a headway sequence of each preset lane in each preset time period of the signalized intersection according to the passing time sequence.
The headway sequence of each preset lane in each preset time period at the signalized intersection is a sequence formed by headways of all vehicles passing through the stop line in the preset time period in the preset lane.
The headway refers to the time difference between adjacent vehicles passing through the stop line. The headway sequence of each preset lane in each preset time period can be recorded as
Figure BDA0002563582010000154
Wherein M (M =1, \ 8230;, M) is a preset time period, N =1, \ 8230;, N is a vehicle serial number, L (L =1,2, \ 8230;, L) is a lane number,
Figure BDA0002563582010000155
and the headway time of the nth vehicle of the ith preset lane in the mth preset time period.
The head time distance of the nth vehicle of the ith preset lane in the mth preset time period is calculated according to the following formula:
Figure BDA0002563582010000156
wherein the content of the first and second substances,
Figure BDA0002563582010000157
the time when the (n + 1) th vehicle of the ith preset lane passes through the stop line for the mth preset time period,
Figure BDA0002563582010000158
and the time when the nth vehicle of the ith preset lane passes through the stop line is the mth preset time period.
The second obtaining module 203 is configured to obtain signal timing data of each preset lane at each preset time period at the signalized intersection.
The signal timing data indicates the turn-on time of signal lights (red and green lights) at the signalized intersection. The signal timing data may be obtained from a signal control system.
In order to avoid mutual conflict among traffic flows in different directions, the signal control system distributes the passing time in each direction according to the traffic demands in each direction. The signal timing data of the ith preset lane for the mth preset time period may be represented as:
Figure BDA0002563582010000161
wherein the content of the first and second substances,
Figure BDA0002563582010000162
the red light turn-on time of the t signal period of the ith preset lane in the mth preset time period,
Figure BDA0002563582010000163
the green light turn-on time of the T signal period of the ith preset lane in the mth preset time period is shown, and T (T =1, \8230; T) is a period number.
And the correcting module 204 is configured to perform correction matching on the signal timing data according to the passing time sequence.
The acquired vehicle passing time sequence and signal timing data usually have certain time deviation, and the deviation can influence the accuracy of the analysis result of the signalized intersection.
For example, in one embodiment, the passing time sequence is obtained from the electric police monitoring system, the signal timing data is obtained from the signal control system, and the two systems respectively have respective timing mechanisms, and the clocks of the two systems have certain deviation, so that when the passing time sequence is mapped with the corresponding signal timing data, more red light running phenomena exist, that is, more time of the vehicle passing through a stop line is concentrated in a red light time range.
In order to improve the accuracy of analysis of the signalized intersection, the signal timing data of each preset lane in each preset time period is corrected and matched.
In an embodiment, said performing a modified match on said signal timing data according to said passing time sequence comprises:
mapping the passing time sequence and the signal timing data of each preset lane in each preset time period, calculating the red light running rate of each signal stage of the preset lane in the preset time period, and calculating the total red light running rate of all the signal stages of the preset lane in the preset time period according to the red light running rate of each signal stage of the preset lane in the preset time period;
and adjusting the green light turn-on time of each preset lane in each preset time period to enable the total red light running rate of the preset lane in the preset time period to obtain the minimum value.
The signal stage is divided according to the number of changes of the right of way at the signalized intersection in a signal period, and the number of the changes of the right of way in the signal period is several.
The total red light running rate of all signal phases is the sum of the red light running rates of all signal phases. For example, if the signal intersection includes four signal phases, the total red light running rate is the sum of the red light running rates of the first signal phase (i.e., phase 1), the second signal phase (i.e., phase 2), the third signal phase (i.e., phase 3), and the fourth signal phase (i.e., phase 4).
Adjusting the green light turn-on time of each preset lane in each preset time period to make the total red light running rate of the preset lane in the preset time period obtain the minimum value, namely performing target optimization, and can be expressed as:
Figure BDA0002563582010000171
s.t.
0≤o s ≤C(m)
Figure BDA0002563582010000172
wherein red _ occupancy s (M) is the red light running rate of the mth preset time period signal stage S, M =1, \8230M, S =1, \8230sis the number of signal stages, o s And C (m) represents the signal period duration of the mth preset time period. O is not less than 0 s C (m) represents that the correction quantity of the green light turn-on time of each signal stage needs to be adjusted between 0 and C (m),
Figure BDA0002563582010000173
Figure BDA0002563582010000174
the sum of the correction amounts of the turn-on time of the green lamp indicating the respective signal stages is equal to 0.
The identifying module 205 is configured to identify a saturated headway sequence of each preset lane in each preset time period at the signalized intersection according to the headway sequence.
Due to the fact that traffic light signals of the signalized intersection are replaced periodically, the vehicles stop and go through the signalized intersection. When the red light is turned on, the vehicles close to the stop line are parked and queued, the subsequently arriving vehicles are influenced by the front queued vehicles, the speed is gradually reduced to zero, and the vehicles are added at the tail of the queuing queue. When the green light is turned on, vehicles close to the stop line start to drive away from the signalized intersection, and subsequent vehicles in line (4 th vehicle in line starts) drive away from the signalized intersection at the saturated flow rate, and the line is gradually dissipated. Therefore, from the point of view of statistics, from the 4 th queued vehicle to the last queued vehicle, the headway should fluctuate within the range of the saturated headway, and the fluctuation (error) is irregular, i.e., the errors of the headway should be independently and equally distributed, and the average value is 0.
In one embodiment, headway may be represented as:
Figure BDA0002563582010000181
wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0002563582010000182
the time interval is the time interval of the nth vehicle of the ith preset lane in the mth preset time period, mu is the saturated time interval, and e (n) is a random error term. Further, assume that the random error term e (n) satisfies a mean of 0 and a variance of 0
Figure BDA0002563582010000183
The variance of the saturated headway mu and the random error term e (n)
Figure BDA0002563582010000184
The time headway of the nth vehicle of the ith preset lane in the mth preset time period is the amount to be estimated
Figure BDA0002563582010000185
Is expected to
Figure BDA0002563582010000186
Sum variance
Figure BDA0002563582010000187
Can be expressed as:
Figure BDA0002563582010000188
Figure BDA0002563582010000189
namely the acquired saturated headway sequence
Figure BDA00025635820100001810
Obedience mean is mu and variance is
Figure BDA00025635820100001811
Is normally distributed. The headway of the (n-1) th vehicle can be expressed as：
Figure BDA00025635820100001812
According to
Figure BDA00025635820100001813
And
Figure BDA00025635820100001814
the relationship between two adjacent headway in the headway sequence can be established:
Figure BDA00025635820100001815
setting Δ e (n) = e (n) -e (n-1),
Figure BDA00025635820100001816
the expectation and variance of Δ e (n) can be expressed as:
e (Δ E (n)) = E (n) -E (n-1)) =0 equation 8
Figure BDA00025635820100001817
According to E (Δ E (n)) = E (n) -E (n-1)) =0 and
Figure BDA00025635820100001818
Figure BDA00025635820100001819
the head time interval error term difference delta e (n) of adjacent vehicles can be obtained, the mean value is 0 and the variance is
Figure BDA0002563582010000191
Normal distribution of (c).
Based on this, in an embodiment, the identifying, according to the headway sequence, the saturated headway sequence of each preset lane for each preset time period at the signalized intersection includes:
calculating the difference value delta e (n) of two adjacent headway distances in the headway distance sequence;
judging whether the expectation of the delta e (n) is 0 or not through hypothesis testing;
and if the expectation of the delta e (n) is 0, judging that the headway sequence is a saturated headway sequence.
In one embodiment, the expectation of Δ e (n) is determined to be 0 by the DF hypothesis test.
For better checking the time headway obtained by observation
Figure BDA0002563582010000192
Whether or not it is a saturated headway, set k (n) = Δ e (n),
Figure BDA0002563582010000193
the following expression can be obtained:
Figure BDA0002563582010000194
wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0002563582010000195
and p is a parameter to be estimated, and is a vehicle headway sequence of the ith preset lane in the mth preset time period. Based on the formula
Figure BDA0002563582010000196
And judging whether the detected headway is the saturated headway or not by carrying out hypothesis test on whether rho is equal to 1 or not. If the hypothesis test is passed, i.e.
Figure BDA0002563582010000197
Then E (Δ E (n)) = E (k (n)) =0 may be obtained, and thus, it may be possible to obtain
Figure BDA0002563582010000198
The observed headway sequence is the saturated headway.
Further, use is made ofLeast squares method to estimate the parameters p and k (n), the estimators of which
Figure BDA0002563582010000199
And
Figure BDA00025635820100001910
can be expressed as:
Figure BDA00025635820100001911
Figure BDA00025635820100001912
according to the theory of regression analysis,
Figure BDA00025635820100001913
obey a t distribution with a degree of freedom of (N-2), wherein
Figure BDA00025635820100001914
Is composed of
Figure BDA00025635820100001915
The smaller the standard error is, the closer the acquired headway sequence is to the real saturated headway sequence is, and the closer the estimated parameters are to the real parameters is, namely, the higher the accuracy of the estimated saturated headway is.
Figure BDA00025635820100001916
The specific expression is as follows:
Figure BDA00025635820100001917
Figure BDA00025635820100001918
Figure BDA0002563582010000201
further, according to Dickey and Fuller theory, due to the estimators
Figure BDA0002563582010000202
The statistical headway of the nth and the (n-1) th vehicles is included at the same time, and then the hypothesis test aiming at rho =1 does not satisfy the t test any more, but satisfies the DF test for this, and the DF test statistic is constructed:
Figure BDA0002563582010000203
the DF statistic constructed above obeys DF distribution, and the threshold values of different confidence degrees of the DF distribution are met during supposition test. In the invention, when the sample amount of the headway sequence is more than 50 and the DF test statistic is [ -2.25,1.66], the test ρ =1 is assumed to be not rejected, that is, the observed headway sequence mean value can be considered as the saturated headway data.
And the filtering module 206 is configured to remove abnormal data in the saturated headway sequence according to the modified and matched signal timing data to obtain a target saturated headway sequence.
In the above steps, the time headway sequence checked by the DF hypothesis has a potential abnormal time headway due to factors such as a preset time period of receiving a peak, a period alternation of traffic lights, and the like. Therefore, the abnormal headway needs to be filtered, and the estimation precision of the saturated headway is ensured. Common abnormal headway includes the following situations: (1) Due to the red light time, the time interval between the vehicle passing through the stop line in the first period and the vehicle passing through the stop line in the last period is more than or equal to the red light time; (2) The green light is turned on, the vehicle is accelerated to start and leave a stop line, and the time interval of the vehicle head is larger due to the fact that the vehicle is still in an accelerated state; (3) During green light, there may also be a large headway due to random arrival of vehicles, etc.
In an embodiment, the removing abnormal data in the saturated headway sequence according to the modified and matched signal timing data includes:
judging whether each headway in the saturated headway sequence is greater than or equal to the red light duration;
and if the headway is greater than or equal to the red light duration, removing the headway from the saturated headway sequence to obtain a first filtered saturated headway sequence.
In an embodiment, removing abnormal data in the saturated headway sequence according to the modified and matched signal timing data further includes:
calculating a preset quantile (e.g., 85% quantile) of the first filtered saturated headway sequence;
judging whether each headway in the first filtered saturated headway sequence is larger than or equal to the preset quantile or not;
if the headway is larger than or equal to the preset quantile, removing the headway from the first filtered saturated headway sequence to obtain a second filtered saturated headway sequence;
performing DF hypothesis test on the second filtered saturated headway sequence, and if the DF hypothesis test is passed, taking the second filtered saturated headway sequence as a target saturated headway sequence;
if the DF hypothesis test is not passed, the iteration factor i = i +1, the first filtered saturated headway sequence is updated to the second filtered saturated headway sequence, and the preset quantile of the first filtered saturated headway sequence is calculated in a returning mode.
And the second calculating module 207 is used for calculating the traffic capacity of the signalized intersection according to the target saturated headway.
In an embodiment, an average value of the target saturated headway sequence of each preset lane in each preset time period may be calculated, and the average value is used as the target saturated headway sequence of the preset lane in the preset time period
Figure BDA0002563582010000211
According to
Figure BDA0002563582010000212
The traffic capacity of the preset lane can be obtained:
Figure BDA0002563582010000213
wherein the content of the first and second substances,
Figure BDA0002563582010000214
the traffic capacity of a first preset lane m in a preset time period, S is the saturation flow, t eg The effective green duration.
The unit of the traffic capacity is pcu/h,
Figure BDA0002563582010000215
the larger the numerical value of (A), the stronger the trafficability of the signalized intersection. On the contrary, the first step is to take the reverse,
Figure BDA0002563582010000216
the smaller the value of (a), the weaker the traffic capacity of the signalized intersection.
In other embodiments, other ways of calculating the target saturated headway from the target saturated headway sequence may be employed
Figure BDA0002563582010000217
For example, a median of the target saturated headway sequence of each preset lane in each preset time period may be calculated, and the median is used as the target saturated headway of the preset lane in the preset time period
Figure BDA0002563582010000218
According to
Figure BDA0002563582010000219
And calculating the traffic capacity of the preset lane.
The signalized intersection analysis device 20 of the second embodiment solves the problem that the existing signalized intersection communication capacity analysis method cannot obtain an accurate analysis result. The passing time sequence and the signal timing data usually have certain time deviation, the deviation can influence the accuracy of the analysis result of the signalized intersection, and the signalized intersection analysis device 20 corrects and matches the signal timing data, corrects the time deviation of the signal timing data and improves the accuracy of the analysis of the communication capacity of the signalized intersection. Due to factors such as a peak preset time period and traffic light period alternation, abnormal data can exist in the saturated head time interval, the signalized intersection analysis device 20 identifies the abnormal data in the saturated head time interval and eliminates the abnormal data, and the accuracy of analyzing the traffic capacity of the signalized intersection is further improved. The signalized intersection analysis device 20 can obtain an accurate signalized intersection analysis result.
EXAMPLE III
The present embodiment provides a storage medium, which stores thereon a computer program, when being executed by a processor, the computer program implementing the steps in the above-mentioned signalized intersection analysis method embodiment, for example, 101 to 107 shown in fig. 1:
101, acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection;
102, calculating a vehicle headway sequence of each preset lane in each preset time period of the signalized intersection according to the vehicle passing time sequence;
103, acquiring signal timing data of each preset lane in each preset time period at the signalized intersection;
104, correcting and matching the signal timing data according to the passing time sequence;
105, identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
106, removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence;
and 107, calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
Alternatively, the computer program, when executed by the processor, implements the functionality of the modules in the above-described apparatus embodiments, such as modules 201-207 in fig. 2:
the first obtaining module 201 is configured to obtain a passing time sequence of each preset lane in each preset time period at the signalized intersection;
the first calculating module 202 is configured to calculate a headway sequence of each preset lane in each preset time period of the signalized intersection according to the passing time sequence;
the second obtaining module 203 is configured to obtain signal timing data of each preset lane at each preset time period at the signalized intersection;
a correction module 204, configured to perform correction matching on the signal timing data according to the passing time sequence;
the identification module 205 is configured to identify a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
the filtering module 206 is configured to remove abnormal data in the saturated headway sequence according to the modified and matched signal timing data to obtain a target saturated headway sequence;
and the second calculating module 207 is used for calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
Example four
Fig. 3 is a schematic diagram of a computer device according to a fourth embodiment of the present invention. The computer device 30 comprises a memory 301, a processor 302 and a computer program 303, such as a signalized intersection analysis program, stored in the memory 301 and executable on the processor 302. The processor 302, when executing the computer program 303, implements the steps in the signalized intersection analysis method embodiments described above, such as 101-107 shown in fig. 1. Alternatively, the computer program may be adapted to perform the functions of the modules of the above-described apparatus embodiments, such as modules 201-207 in fig. 2, when executed by a processor.
Illustratively, the computer program 303 may be partitioned into one or more modules that are stored in the memory 301 and executed by the processor 302 to perform the present method. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 303 in the computer device 30. For example, the computer program 303 may be divided into modules in fig. 2.
The computer device 30 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. Those skilled in the art will appreciate that the schematic diagram 3 is merely an example of the computer device 30 and does not constitute a limitation of the computer device 30, and may include more or less components than those shown, or combine certain components, or different components, for example, the computer device 30 may also include input and output devices, network access devices, buses, etc.
The Processor 302 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor 302 may be any conventional processor or the like, the processor 302 being the control center of the computer device 30 and connecting the various parts of the overall computer device 30 using various interfaces and lines.
The memory 301 may be used to store the computer program 303, and the processor 302 may implement various functions of the computer device 30 by executing or executing the computer program or module stored in the memory 301 and calling data stored in the memory 301. The memory 301 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data created according to the use of the computer device 30. Further, the memory 301 may include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other non-volatile solid state storage device.
The modules integrated by the computer device 30 may be stored in a storage medium if they are implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a storage medium and executed by a processor, to instruct related hardware to implement the steps of the embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying said computer program code, recording medium, U-disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM).
Further, the computer usable storage medium may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the blockchain node, and the like.
The block chain is a novel application mode of computer technologies such as distributed data storage, point-to-point transmission, a consensus mechanism, an encryption algorithm and the like. A block chain (Blockchain), which is essentially a decentralized database, is a series of data blocks associated by using a cryptographic method, and each data block contains information of a batch of network transactions, so as to verify the validity (anti-counterfeiting) of the information and generate a next block. The blockchain may include a blockchain underlying platform, a platform product service layer, an application service layer, and the like.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical functional division, and other divisions may be realized in practice.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a mode of hardware and a software functional module.
The integrated module implemented in the form of a software functional module may be stored in a storage medium. The software functional module is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present invention.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned. Furthermore, it is to be understood that the word "comprising" does not exclude other modules or steps, and the singular does not exclude the plural. A plurality of modules or means recited in the system claims may also be implemented by one module or means in software or hardware. The terms first, second, etc. are used to denote names, but not to denote any particular order.
Finally, it should be noted that the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the same, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims (8)

1. A signalized intersection analysis method, comprising:
acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection;
calculating a vehicle headway sequence of each preset lane in each preset time period of the signalized intersection according to the vehicle passing time sequence;
acquiring signal timing data of each preset lane in each preset time period of the signalized intersection, wherein the signal timing data represents the red light turn-on time and the green light turn-on time of each signal cycle of the signalized intersection;
and correcting and matching the signal timing data according to the passing time sequence, wherein the method comprises the following steps: mapping the passing time sequence and the signal timing data of each preset lane in each preset time period, calculating the red light running rate of each signal stage of the preset lane in the preset time period, and calculating the total red light running rate of all the signal stages of the preset lane in the preset time period according to the red light running rate of each signal stage of the preset lane in the preset time period; adjusting the green light turn-on time of each preset lane in each preset time period to enable the total red light running rate of the preset lane in the preset time period to obtain the minimum value;
identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence, wherein the method comprises the following steps: judging whether each headway in the saturated headway sequence is greater than or equal to the red light duration or not; if the headway is greater than or equal to the red light duration, removing the headway from the saturated headway sequence to obtain a first filtered saturated headway sequence;
and calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
2. The signalized intersection analysis method according to claim 1, wherein the identifying the saturated headway sequence for each preset lane for each preset time period at the signalized intersection according to the headway sequence comprises:
calculating the difference value delta e (n) of two adjacent headway distances in the headway distance sequence;
judging whether the expectation of the delta e (n) is 0 or not through hypothesis testing;
and if the expectation of the delta e (n) is 0, judging that the headway sequence is a saturated headway sequence.
3. The signalized intersection analysis method of claim 2, wherein the determining whether the expectation of Δ e (n) is 0 by hypothesis testing comprises:
whether Δ e (n) is expected to be 0 is judged by the DF hypothesis test.
4. The signalized intersection analysis method according to claim 1, wherein the removing of the abnormal data in the saturated headway sequence according to the signalized timing data further comprises:
calculating a preset quantile of the first filtered saturated headway sequence;
judging whether each headway in the first filtering saturated headway sequence is larger than or equal to the preset quantile or not;
if the headway is larger than or equal to the preset quantile, removing the headway from the first filtered saturated headway sequence to obtain a second filtered saturated headway sequence;
performing DF hypothesis test on the second filtered saturated headway sequence, and if the DF hypothesis test is passed, taking the second filtered saturated headway sequence as the target saturated headway sequence;
and if the DF hypothesis test is not passed, updating the first filtered saturated headway sequence into the second filtered saturated headway sequence and returning to the step of calculating the preset quantiles of the first filtered saturated headway sequence.
5. The signalized intersection analysis method according to claim 1, wherein the obtaining of the passing time sequence of each preset lane for each preset time period at the signalized intersection comprises:
and acquiring the passing time sequence through an electric alarm detector of the electric alarm monitoring system.
6. A signalized intersection analysis device, the device comprising:
the first acquisition module is used for acquiring a passing time sequence of each preset lane in each preset time period at the signalized intersection;
the first calculation module is used for calculating a vehicle headway sequence of each preset lane in each preset time period of the signalized intersection according to the vehicle passing time sequence;
the second acquisition module is used for acquiring signal timing data of each preset lane in each preset time period of the signalized intersection, wherein the signal timing data represents the red light turn-on time and the green light turn-on time of each signal cycle of the signalized intersection;
the correction module is used for correcting and matching the signal timing data according to the passing time sequence and comprises: mapping the passing time sequence and the signal timing data of each preset lane in each preset time period, calculating the red light running rate of each signal stage of the preset lane in the preset time period, and calculating the total red light running rate of all the signal stages of the preset lane in the preset time period according to the red light running rate of each signal stage of the preset lane in the preset time period; adjusting the green light turn-on time of each preset lane in each preset time period to enable the total red light running rate of the preset lane in the preset time period to obtain the minimum value;
the identification module is used for identifying a saturated headway sequence of each preset lane in each preset time period of the signalized intersection according to the headway sequence;
the filtering module is used for removing abnormal data in the saturated headway sequence according to the corrected and matched signal timing data to obtain a target saturated headway sequence, and comprises the following steps: judging whether each headway in the saturated headway sequence is greater than or equal to the red light duration; if the headway is greater than or equal to the red light duration, removing the headway from the saturated headway sequence to obtain a first filtered saturated headway sequence;
and the second calculation module is used for calculating the traffic capacity of the signalized intersection according to the target saturated headway sequence.
7. A computer device comprising a processor for executing a computer program stored in a memory to implement a signalized intersection analysis method according to any one of claims 1 to 5.
8. A storage medium having stored thereon a computer program for implementing the signalized intersection analysis method according to any one of claims 1 to 5 when the computer program is executed by a processor.
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