CN111813374A - Method and device for generating pseudo-random sequence based on DSP (digital Signal processor), and storage medium - Google Patents
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Abstract
The invention discloses a method and a device for generating a pseudo-random sequence based on a DSP (digital signal processor), and a storage medium. The method comprises the following steps: obtaining a first shift value stored in a first register of the DSP, wherein the first shift value is formed by a first m sequence x1(n) shifting the initial value by Nc times to obtain a shift value, the first shift value being used to represent x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+ 31); obtaining a second m-sequence x2(N) initial value, and obtaining x stored in N registers of the DSP2(N) N polynomial coefficients, each for determining x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); in DSP according to x2Initial value of (n) and x2(N) determining a second shift value, second shiftThe value being used to represent x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); and generating a target pseudo-random sequence in the DSP according to the first shift value and the second shift value.
Description
Technical Field
The invention relates to the field of communication, in particular to a method and a device for generating a pseudo-random sequence based on a DSP (digital signal processor), and a storage medium.
Background
Pseudo-random sequences are widely used in communication systems, and both New Radio (NR) and Long Term Evolution (LTE) in The 3rd generation Partnership Project (3 GPP) standard protocol use Gold sequences as pseudo-random sequences. The pseudo-random sequence in the communication system plays an important role in the aspects of channel estimation, signal scrambling, reference signal generation, signal descrambling, interference resistance and the like.
In the 3GPP standard, a large state offset exists in a pseudo random sequence generation formula, and the storage space occupied and the execution time of a conventional bit pattern generation method significantly increase with the increase of the sequence length, which finally results in the disadvantage of long time consumption in the pseudo random sequence generation.
Therefore, an effective technical scheme has not been proposed yet for the problem of long time consumption in the generation of the pseudo-random sequence in the related art.
Disclosure of Invention
The embodiment of the invention provides a method and a device for generating a pseudo-random sequence based on a DSP (digital signal processor), and a storage medium, which are used for at least solving the technical problem of long time consumption in the generation of the pseudo-random sequence in the related technology.
According to an aspect of the embodiments of the present invention, a method for generating a pseudo random sequence based on a DSP is provided, including: obtaining a first shift value stored in a first register of the DSP, wherein the first shift value is formed by a first m sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2),…,x1(Nc+31), above x1The initial value of (n) is 31 bits; obtaining a second m-sequence x2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2The initial value of (n) is 31 bitsEach of the polynomial coefficients is 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); in the DSP according to x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is 32 bits and said second shift value is derived from said x2The initial value of (n) is shifted Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); and generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value.
According to another aspect of the embodiments of the present invention, there is also provided a device for generating a pseudo random sequence based on a DSP, including: a first obtaining unit, configured to obtain a first shift value stored in a first register of the DSP, where the first shift value is formed by a first m-sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(N1+2),…,x1(Nc+31), above x1The initial value of (n) is 31 bits; a second obtaining unit for obtaining a second m-sequence x2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+ 31); a determination unit for determining x in the DSP2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is 32 bits and said second shift value is derived from said x2(n) start ofThe initial value is shifted Nc times to obtain a shift value, and the second shift value is used to represent x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+ 31); and a generating unit configured to generate a target pseudorandom sequence in the DSP according to the first shift value and the second shift value.
According to still another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the above-mentioned method for generating a pseudo-random sequence based on DSP when running.
According to another aspect of the embodiments of the present invention, there is also provided an electronic apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the method for generating the pseudo-random sequence based on the DSP by using the computer program.
In the embodiment of the invention, a first shift value pre-stored in a first register of the DSP is obtained, wherein the first shift value is formed by a first m sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits; obtaining a second m-sequence x2(N) initial value, and acquiring the x values stored in advance in N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); then, in the DSP, according to the x2(n) initial value and x2(N) determining a second shift value, wherein said second shift value is 32 bits,the second shift value is derived from x2The initial value of (n) is shifted Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); and finally, generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value. By adopting the technical scheme, the first m sequence x stored in advance is directly obtained1(n) and a second m-sequence x2(N) N polynomial coefficients, avoiding the need for the first m-sequence x in generating the target pseudorandom sequence1(n) the initial value of (n) is shifted Nc times to reduce the amount of calculation, and the second m-sequence x is passed2(N) N polynomial coefficients and x obtained2And (n) determining the second shift value by the initial value, so that the calculated amount can be reduced, the technical effect of reducing the calculated amount is achieved, and the technical problem that the time consumption is long in the generation of the pseudo-random sequence in the related technology is solved.
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The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of an application environment of a method for generating a pseudo-random sequence based on a DSP according to an embodiment of the invention;
FIG. 2 is a flow chart illustrating an alternative method for generating a pseudo-random sequence based on DSP according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an alternative apparatus for generating a pseudo-random sequence based on DSP according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an alternative electronic device according to an embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The method embodiments provided in the embodiments of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking the example of being operated on a mobile terminal, fig. 1 is a hardware structure block diagram of the mobile terminal of a data processing method according to an embodiment of the present invention. As shown in fig. 1, the mobile terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and a memory 104 for storing data, wherein the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the data processing method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.
Optionally, in this embodiment, the terminal device may include, but is not limited to, at least one of the following: mobile phones (such as Android phones, iOS phones, etc.), notebook computers, tablet computers, palm computers, MID (Mobile internet devices), PAD, desktop computers, etc. Such networks may include, but are not limited to: a wired network, a wireless network, wherein the wired network comprises: a local area network, a metropolitan area network, and a wide area network, the wireless network comprising: bluetooth, WIFI, and other networks that enable wireless communication. The server may be a single server or a server cluster composed of a plurality of servers. The above is only an example, and the present embodiment is not limited to this.
Optionally, as an optional implementation manner, as shown in fig. 2, a flow of the method for generating a pseudo random sequence based on a DSP may include the steps of:
step S202, obtaining a first shift value stored in a first register of the DSP, wherein the first shift value is a first m-sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits;
optionally, the pseudo-random sequence used in the 3GPP standard NR is defined by a Gold sequence with a 31-bit length, and x is as described above1The initial value of (n) is 31 bits, and thus, the first m-sequence x can be stored using a 32-bit first register1A first shift value of (n).
Wherein the first shift value is represented by x1The initial value of (n) is shifted Nc times, and the first shift value is used to represent x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31)，x1The initial value of (n) is 31 bits.
Step S204, a second m sequence x is obtained2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)；
Optionally, a second m-sequence x is obtained2(n) initial value of (x)2The initial value of (N) needs to be initialized according to different application scenes, and x stored in N registers of the DSP in advance respectively is obtained2N polynomial coefficients of (N). Wherein N is 32 and x is2(n) has an initial value of 31 bits, each of the polynomial coefficientsFor 32 bits, the above N polynomial coefficients are used to determine x respectively2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)。
Step S206, in the Digital Signal processing (DSP for short), based on the above x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is 32 bits and said second shift value is derived from said x2The initial value of (n) is shifted Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)；
Alternatively, it may be according to x2(n) initial value and x2(N) to determine a second shift value, wherein the second shift value is 32 bits and the second shift value is used to represent x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)。
Step S208, generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value.
Optionally, the target pseudorandom sequence is generated in the DSP according to the first shift value and the second shift value.
Optionally, the obtained first shift value and second shift value are input into the following formula to determine the target pseudorandom sequence:
c(n)＝(x1(n+Nc)+x2(n+Nc))mod2 (1)
x1(n+31)＝(x1(n+3)+x1(n))mod2 (2)
x2(n+31)＝(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2 (3)
wherein c (N) is the target pseudorandom sequence, and N iscIs the first m-sequenceAnd a state offset between said second m-sequence, said NcThe maximum value of the values of n is used to indicate the sequence length of the target pseudorandom sequence, and the value of n is a positive integer 1600.
Optionally, the method for generating the pseudo random sequence based on the DSP may be applied to, but not limited to, channel estimation, signal scrambling, reference signal generation, signal descrambling, interference resistance, and other scenarios in a communication system.
With the present embodiment, a first shift value pre-stored in a first register of the DSP is obtained, wherein the first shift value is formed by a first m-sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits; obtaining a second m-sequence x2(N) initial value, and acquiring the x values stored in advance in N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); then, in the DSP, according to the x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is 32 bits and said second shift value is derived from said x2The initial value of (n) is shifted Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); and finally, generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value. By adopting the technical scheme, the first m sequence x stored in advance is directly obtained1(n) and a second m-sequence x2(N) N polynomial coefficients, avoiding the need for the first m-sequence x in generating the target pseudorandom sequence1(n) the initial value of (n) is shifted Nc times to reduce the amount of calculation, and the second m-sequence x is passed2(N) N polynomial coefficients and x obtained2And (n) determining the second shift value by the initial value, so that the calculated amount can be reduced, the technical effect of reducing the calculated amount is achieved, and the technical problem that the time consumption is long in the generation of the pseudo-random sequence in the related technology is solved.
In an optional embodiment, before the obtaining the first shift value stored in the first register of the DSP, the method further includes: storing the first shift value in the first register, wherein the first register is a 32-bit register, and the lowest bit of the first register is used for storing the x1(Nc) Or, the lowest bit in the first register is used for storing the x1(Nc+31)。
Optionally, it should be noted that, when the pseudo-random sequence c (n) is generated based on the DSP according to the protocol standard, since each bit of the sequence is a binary bit 0 or 1, each bit of data may be stored as 8-bit unsigned integer data in the implementation process, that is, each bit sequence value is stored in a DSP minimum data type (1 byte), and then a bit type algorithm is designed according to a formula in the protocol. Although the algorithm is simple to implement, when the pseudo-random sequence code needs to be generated, a large amount of storage space is occupied, and each byte is used for storing 1-bit sequence information, so that 7-bit waste is caused.
Optionally, in this embodiment, the first register may be a 32-bit register, and each 32 bits of the first shift value are placed in 32-bit unsigned shaping data (DSP register type 32 bit). The lowest order bit in the first register may be set to store the x1(Nc) Or, the lowest bit in the first register is set for storing the x1(Nc+31)。
With the embodiment, the data storage space is greatly reduced by storing the first shift value through the 32-bit register.
In an alternative embodiment, before storing the first shift value in the first register, the method further includes: mixing the first m-sequence x1The initial value of (n) is shifted Nc times to obtain the first shift value.
Alternatively, the first m-sequence x may be previously expressed according to the above formula (1) and formula (2)1The initial value of (n) is shifted Nc times to obtain the first shift value.
In an alternative embodiment, x is determined in the DSP according to the above2(n) initial value and x2(N) determining a second shift value comprising: according to the above x2(n) initial value and x2(N) determining said second shift value based on the logical relationship between the N polynomial coefficients.
Optionally, x is first obtained2(N) initial value, then obtaining the x stored in N registers of DSP by searching table2N polynomial coefficients of (N), and finally, according to x2The sum of the initial value of (n) and the above x2(N) determining the second shift value based on a complex logical relationship between the N polynomial coefficients.
In addition, x is2The sum of the initial value of (n) and the above x2(N) the logical relationship between the N polynomial coefficients needs to be determined through a plurality of logical operations, and after the logical relationship is determined, the logical relationship can be passed, and x2(n) initial value and x2The N polynomial coefficients of (N) directly result in the second shift value, and there is no need to shift the cyclic N in calculating the second shift valuec1600 times.
In an alternative embodiment, generating the target pseudorandom sequence in the DSP according to the first shift value and the second shift value includes: and carrying out exclusive OR operation on the first shift value and the second shift value in the DSP to obtain the target pseudorandom sequence.
Alternatively, the target pseudorandom sequence may be obtained by performing an exclusive or operation on the first shift value and the second shift value in the DSP according to the formula (1), the formula (2), and the formula (3).
In an alternative embodiment, the above-mentioned obtaining the second m-sequence x2(n) initial values comprising: determining the second m-sequence x according to the usage scenario of the target pseudorandom sequence2(n) initial value.
Optionally, under different usage scenarios, the second m-sequence x2The initial value of (n) is different, and the second m sequence x can be determined according to a specific use scene2(n) initial value.
In an alternative embodiment, the second m-sequence x is determined according to the usage scenario of the target pseudorandom sequence2(n) initial values comprising: in the case that the usage scenario is the physical downlink broadcast channel PBCH, the second m-sequence x is determined by the following formula2Initial value of (n):
wherein, the above-mentioned CinitIs the second m-sequence x2(n) initial value of the above
Is a cell ID; or, in the case that the usage scenario is a downlink physical control channel PDCCH, determining the second m-sequence x by the following formula2Initial value of (n): cinit＝(nRNTI·216+nID)mod231。
Optionally, a second m-sequence x2(n) it needs to be initialized according to different application scenarios, for example, it is used in a Physical Broadcast Channel (PBCH) in the NR protocol
The cell ID is initialized, and the Physical Downlink Control Channel (PDCCH) is used as Cinit＝(nRNTI·216+nID)mod231And (5) initializing.
It should be noted that, the pseudo-random sequence usage scenarios are very many, almost every channel is used, and the two determinations x are used2The manner of the initial value of (n) is merely an example, and the present embodiment is not limited thereto.
The following describes a flow of a method for generating a DSP-based pseudorandom sequence in connection with an alternative example, where the method may include the following steps:
it should be noted that the pseudo-random sequence used in the NR of the 3GPP standard is defined by a Gold sequence with a 31-bit length, and the Gold sequence is obtained by shifting two m sequences and then performing modulo two addition, and the specific formula is as follows:
c(n)＝(x1(n+Nc)+x2(n+Nc) Mod2 formula (1)
x1(n+31)＝(x1(n+3)+x1(n)) mod2 equation (2)
x2(n+31)＝(x2(n+3)+x2(n+2)+x2(n+1)+x2(n)) mod2 formula (3)
Wherein N isc1600 is the state offset that is purposely added to ensure non-correlation between different sequences. c the length of the (n) sequence is MPNIn standard, sequence x1The initial values of (n) are: x is the number of1(0)＝1，x1(n) 0, n 1,2, … …,30, and a second sequence x2(n) needs to be initialized according to different application scenarios, for example, in the downlink physical broadcast channel PBCH in the NR protocol
(cell ID) and C in PDCCHinit＝(nRNTI·216+nID)mod231And (5) initializing.
It should be noted that, the conventional implementation method:
when the pseudo-random sequence c (n) is generated based on the DSP according to the protocol standard, each bit of the sequence is binary bit 0 or 1, and each bit of data can be stored as 8-bit unsigned integer data in the implementation process, that is, each bit sequence value is stored in a DSP minimum data type (1 byte), and then a bit type algorithm is designed according to a formula in the protocol. Although the algorithm is simple to implement, when the pseudo-random sequence code needs to be generated, a large amount of storage space is occupied, and each byte is used for storing 1-bit sequence information, so that 7-bit waste is caused.
As can be seen from the above equations (1), (2) and (3), the pseudo-random sequence c (N) is due to NcThe presence of 1600 results in two m-sequences x1(n) and the sequence x2(N) in the conventional algorithm, each iterates N firstc1600 times. In NR communication systems, Gold sequences are used in many applications as pseudo-random sequences, and there are applications where the pseudo-random sequences generated by the system are very short. For example, in some scenarios of NR systems, the length of the pseudo-random sequence that needs to be generated is MPNWhen 32 bits are formed, a pseudo-random sequence is generated by using a conventional method, and the system firstly needs to shift and iterate Nc1600 times, then 32 bits of information of sequence length can be generated. That is, when a 32-bit pseudo-random sequence is generated by using the conventional method, it needs to cyclically shift 1632 times, which results in a long sequence generation time, wastes a large amount of system resources, and is not favorable for real-time data processing.
The above conventional implementation method has the following two problems:
1. bit is stored through the minimum storage unit (byte) of the DSP, so that the storage space is wasted, and the data storage space is increased.
2. Shift iteration N is required in generating pseudorandom sequencescThe actual Gold sequence is generated after 1600 times, which results in an increased amount of system computation and waste of data processing time.
Aiming at the characteristics of a pseudo-random sequence used by NR, a pseudo-random sequence generation method based on a DSP platform is provided, and in order to solve the problems, the method puts every 32 bits of a Gold sequence into 32-bit unsigned shaping data (DSP register type 32 bits). By increasing the data processed per operationAnd the data storage space can be greatly reduced. At the same time, the patent can directly obtain NcThe loop iteration is saved and the data processing rate can be effectively improved as the m sequence after 1600.
The specific implementation process is as follows:
step one, determining a sequence x1(n) initial value.
In the standard, sequence x1The initial values of (n) are: x is the number of1(0)＝1，x1And (n) is 0, n is 1,2, … …,30, and each bit information is stored in a 32-bit register in the DSP processor. Defining an unsigned shaping variable x1_initAs registers for storing x1The initial value of (n) is 31 bits of information.
If the lowest bit in the 32-bit register of the DSP is defined as x1(0) By analogy, x can be obtained1The initial values of (n) are: x is the number of1_init＝0x00000001。
Step two, determining a sequence x1(N) iteration Nc1600 times later.
In the standard, sequence x1The calculation method of (n) is as follows:
x1(n+31)＝(x1(n+3)+x1(n))mod2
due to the sequence x1(n) is known for its initial value, then x can be calculated by means of an iterative loop1(Nc)，x1(Nc+1),x1(N1+2),…,x1(Nc+31) bit information value, where Nc＝1600。
Unsigned shaping variable x1 is also defined as a register to store x1(1600)～x1The value of (1600+31) is 32 bits of information. The value of x1 and x can be known by observation1_initAnd Nc1600 is relevant, because these two values are fixed values in the standard, so the x1 value is also fixed, so we can calculate the value in advance in the DSP implementation process, store it in the form of table, each time when calculating the pseudo random sequence, it is only necessary to directly look up the table and call it, and save the sequence x1(N) shift cycle Nc1600 times, the time consumption is reduced. And the value can be stored only by a 32-bit register, and the waste of the memory is not caused.
Step three, determining a sequence x2(n) initial value.
In the standard, sequence x2The initial value of (n) may be different depending on different scenes, like CinitThe values are related. But with a total of 31 bits of initial value, an unsigned shaping variable x is also defined in the DSP processor2_initAs registers for storing x2(n) initial value.
If the lowest bit in the 32-bit register of the DSP is defined as x2(0) By analogy, x can be obtained2The initial values of (n) are: x is the number of2_init＝Cinit。
Step four, determining the sequence x2(N) iteration Nc1600 times later.
In the standard, sequence x2The calculation method of (n) is as follows:
x2(n+31)＝(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2
wherein, the sequence x2The initial value of (n) is different in different scenarios, defined as x2(0)，x2(1),……,x2(30)。
with x2(31) For example, the following steps are carried out:
wherein the coefficient knCan be represented as k0＝k1＝k2＝k3＝1,k4＝k5＝…k29＝k300. Will sequence x2The initial value of (n) is considered a polynomial, the coefficient knAre the coefficients of the polynomial.
Defining unsigned shaping register k in a DSP processorcoefFor storing the coefficient knThus k iscoef0x0000000F, so it can pass the sequence x2Initial value C of (n)initSum polynomial coefficient kcoefAnd directly calculating a sequence value.
temp＝(kcoef&Cinit)&0x7FFFFFFF, and then performing exclusive OR on all bits of the register temp, or finding out the number of 1 in the binary number of 32 bits of the register temp, if the even number result is 0, and if the odd number result is 1, thus obtaining x2(31) The value of (c).
By analogy, the following can be obtained:
x2(32) value of (c), corresponding coefficient register kcoef＝0x0000001E，
x2(33) Value of (c), corresponding coefficient register kcoef＝0x0000003C，
…
x2(1600) Value of (c), corresponding coefficient register kcoef＝0x0099110E，
x2(1601) Value of (c), corresponding coefficient register kcoef＝0x0132221C，
…
x2(1631) Value of (c), corresponding coefficient register kcoef＝0x0707FF5A。
Defining unsigned shaping variable x2 as a register to store x2(1600)～x2The value of (1600+31) is 32 bits of information. To obtain the value of x2, x may be calculated2(1600)～x2The coefficient of (1600+31) value is stored in table form, and the corresponding value can be obtained only by simple calculation of table lookup.
The pseudo code is as follows:
the iterative loop N is omitted in the implementation processc1600 times, the time consumption is reduced.
And step five, determining the value of the pseudo-random sequence c (n).
In the standard, the sequence c (n) is calculated by the following method:
c(n)＝(x1(n+Nc)+x2(n+Nc))mod2
the two m-sequences x are already known in the first few steps1(n) and x2N of (N)cAs a result, the c (n) sequence can be calculated directly from the length, which is 1600 offset values. Here, the bit information value is stored by adopting a compact arrangement mode of a 32-bit register, and the 32-bit information can be directly calculated each time.
Directly obtaining the sequence x by table look-up1(n) and x2And (n) carrying out exclusive OR on the deviation value to obtain the first 32bit sequence value of the pseudorandom sequence c (n).
The subsequent bit information needs to calculate the sequence x according to the formula1(n), recalculating the sequence x2And (n) finally obtaining the product by means of XOR of the two products. We found the sequence x1(n) and the sequence x2(n) only 28-bit information can be obtained in a mode of shifting XOR every time, the remaining 4-bit information needs to use the current calculated value, and here, a mode of calculating 16 bits every time and then splicing is adopted to obtain complete information of 32 bits.
The pseudo code is as follows:
fori＝0:length
// calculate x1
seq＝x1；
temp0＝seq^(seq<<3)；
seq＝(seq<<16)|(temp>>16)；
temp1＝seq^(seq<<3)；
x1＝(temp0&0xffff0000)|((temp1>>16)&0x0000ffff)；
// calculate x2
seq＝x2；
temp0＝seq^(seq<<1)^(seq<<2)^(seq<<3)；
seq＝(seq<<16)|(temp>>16)；
temp1＝seq^(seq<<1)^(seq<<2)^(seq<<3)；
x2＝(temp0&0xffff0000)|((temp1>>16)&0x0000ffff)；
// calculate c
c＝x1^x2；
end
In addition, the Nc-1600 correspondence table for X1 and the Nc-1600 correspondence table for X2 are specifically as follows:
with the present embodiment, the x1 sequence Nc-1600 corresponding value is obtained by using direct query, according to the initial value CinitAnd polynomial coefficients of a lookup table are calculated to obtain an Nc 1600 corresponding value of the x2 sequence, and a compact splicing method is used for calculating a pseudorandom sequence, so that the data amount of each calculation process can be increased, and the data storage space can be greatly reduced. Meanwhile, by adopting the technical scheme, the m sequence after the Nc is 1600 can be directly obtained, the loop iteration is saved, and the data processing rate can be effectively improved.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
According to another aspect of the embodiments of the present invention, there is also provided an apparatus for generating a pseudo random sequence based on a DSP, as shown in fig. 3, the apparatus including:
a first obtaining unit 302, configured to obtain a first shift value stored in a first register of the DSP, where the first shift value is formed by a first m-sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits;
a second obtaining unit 304, configured to obtain a second m-sequence x2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
A determining unit 306 for determining x in the DSP2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is determined from said x2The initial value of (n) is shifted Nc times to obtain a shift value, the second shift value is 32 bits, and the second shift value represents x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31；
A generating unit 308, configured to generate a target pseudorandom sequence in the DSP according to the first shift value and the second shift value.
Alternatively, the first acquiring unit 602 may be configured to execute step S202, the determining unit 604 may be configured to execute step S204, the second determining unit 606 may be configured to execute step S206, and the first processing unit 606 may be configured to execute step S206.
With the present embodiment, the acquisition is performed in advance in the first register of the DSPA first stored shift value, wherein the first shift value is represented by a first m-sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits; obtaining a second m-sequence x2(N) initial value, and acquiring the x values stored in advance in N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); then, in the DSP, according to the x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is 32 bits and said second shift value is derived from said x2The initial value of (n) is shifted Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+ 31); and finally, generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value. By adopting the technical scheme, the first m sequence x stored in advance is directly obtained1(n) and a second m-sequence x2(N) N polynomial coefficients, avoiding the need for the first m-sequence x in generating the target pseudorandom sequence1(n) the initial value of (n) is shifted Nc times to reduce the amount of calculation, and the second m-sequence x is passed2(N) N polynomial coefficients and x obtained2And (n) determining the second shift value by the initial value, so that the calculated amount can be reduced, the technical effect of reducing the calculated amount is achieved, and the technical problem that the time consumption is long in the generation of the pseudo-random sequence in the related technology is solved.
As an alternative solution, it is possible to provide,the above-mentioned device still includes: a third obtaining unit, configured to store the first shift value in the first register, where the first register is a 32-bit register, and a lowest bit in the first register is used to store the x bit1(Nc) Or, the lowest bit in the first register is used for storing the x1(Nc+31)。
As an optional technical solution, the apparatus further includes: a first processing unit for converting the first m-sequence x1The initial value of (n) is shifted Nc times to obtain the first shift value.
As an optional technical solution, the apparatus further includes: and a storage unit for storing the N polynomial coefficients in the N registers, respectively.
As an optional technical solution, the determining unit is further configured to determine x according to the above description2(n) initial value of the above x2(N) determining said second shift value based on the logical relationship between the N polynomial coefficients.
As an optional technical solution, the generating unit is further configured to perform an exclusive or operation on the first shift value and the second shift value in the DSP to obtain the target pseudorandom sequence.
As an optional technical solution, the second obtaining unit is further configured to determine the second m-sequence x according to a usage scenario of the target pseudorandom sequence2(n) initial value.
As an optional technical solution, the second obtaining unit is further configured to determine, when the usage scenario is a physical downlink broadcast channel PBCH, the second m-sequence x according to the following formula2Initial value of (n):
wherein, the above-mentioned CinitIs the second m-sequence x2(n) initial value of the above
Is a cell ID; or in the above-mentioned fields of useWhen the scene is a downlink physical control channel PDCCH, the second m sequence x is determined by the following formula2Initial value of (n): cinit＝(nRNTI·216+nID)mod231。
According to a further aspect of embodiments of the present invention, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.
Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s1, obtaining a first shift value stored in a first register of the DSP, wherein the first shift value is formed by a first m sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits;
s2, obtaining a second m sequence x2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
S3, in the DSP according to the x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is determined from said x2The initial value of (n) is shifted Nc times to obtain a shift value, the second shift value is 32 bits, and the second shift value represents x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
S4, generating a target pseudo random sequence in the DSP according to the first shift value and the second shift value.
Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
alternatively, in this embodiment, a person skilled in the art may understand that all or part of the steps in the methods of the foregoing embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, ROM (Read-Only Memory), RAM (Random access Memory), magnetic or optical disks, and the like.
According to yet another aspect of the embodiments of the present invention, there is also provided an electronic device for implementing the method for generating a DSP-based pseudo-random sequence, as shown in fig. 4, the electronic device includes a memory 402 and a processor 404, the memory 402 stores a computer program, and the processor 404 is configured to execute the steps in any one of the method embodiments through the computer program.
Optionally, in this embodiment, the electronic apparatus may be located in at least one network device of a plurality of network devices of a computer network.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s1, obtaining a first shift value stored in a first register of the DSP, wherein the first shift value is formed by a first m sequence x1A shift value obtained by shifting the initial value of (n) Nc times, wherein the first shift value is 32 bits, and the first shift value indicates x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), above x1The initial value of (n) is 31 bits;
s2, obtaining a second m sequence x2(N) and obtaining the x stored in the N registers of the DSP2(N) N polynomial coefficients, wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
S3, in the DSP according to the x2(n) initial value and x2(N) determining a second shift value from said N polynomial coefficients, wherein said second shift value is determined from said x2The initial value of (n) is shifted Nc times to obtain a shift value, the second shift value is 32 bits, and the second shift value represents x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
S4, generating a target pseudo random sequence in the DSP according to the first shift value and the second shift value.
Alternatively, it can be understood by those skilled in the art that the structure shown in fig. 4 is only an illustration, and the electronic device may also be a terminal device such as a smart phone (e.g., an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile Internet Device (MID), a PAD, and the like. Fig. 4 is a diagram illustrating the structure of the electronic device. For example, the electronic device may also include more or fewer components (e.g., network interfaces, etc.) than shown in FIG. 4, or have a different configuration than shown in FIG. 4.
The memory 402 may be used to store software programs and modules, such as program instructions/modules corresponding to the method and apparatus for generating a pseudo-random sequence based on a DSP in the embodiment of the present invention, and the processor 404 executes various functional applications and data processing by running the software programs and modules stored in the memory 402, that is, implements the method for generating a pseudo-random sequence based on a DSP as described above. The memory 402 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 402 may further include memory located remotely from the processor 404, which may be connected to the terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof. The memory 402 may be, but not limited to, specifically configured to store information such as a target height of the target object. As an example, as shown in fig. 4, the memory 402 may include, but is not limited to, the first obtaining unit 302, the second obtaining unit 304, the determining unit 306, and the generating unit 306 of the DSP-based pseudo random sequence generating apparatus. In addition, the device may further include, but is not limited to, other module units in the apparatus for generating a pseudo random sequence based on a DSP, which is not described in detail in this example.
Optionally, the transmission device 406 is used for receiving or sending data via a network. Examples of the network may include a wired network and a wireless network. In one example, the transmission device 406 includes a Network adapter (NIC) that can be connected to a router via a Network cable and other Network devices to communicate with the internet or a local area Network. In one example, the transmission device 406 is a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
In addition, the electronic device further includes: a display 408 and a connection bus 410 for connecting the various modular components of the electronic device described above.
In other embodiments, the terminal or the server may be a node in a distributed system, wherein the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting a plurality of nodes through a network communication form. Nodes can form a Peer-To-Peer (P2P, Peer To Peer) network, and any type of computing device, such as a server, a terminal, and other electronic devices, can become a node in the blockchain system by joining the Peer-To-Peer network.
Alternatively, in this embodiment, a person skilled in the art may understand that all or part of the steps in the methods of the foregoing embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The integrated unit in the above embodiments, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in the above computer-readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, and including instructions for causing one or more computer devices (which may be personal computers, servers, or network devices) to execute all or part of the steps of the method according to the embodiments of the present invention.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that it is obvious to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.
Claims (10)
1. A method for generating a pseudo-random sequence based on DSP is characterized by comprising the following steps:
obtaining a first shift value stored in a first register of a DSP, wherein the first shift value is represented by a first m-sequence x1(n) is shifted by Nc times, the first shift value is 32 bits, and the first shift value is used to represent x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), said x1The initial value of (n) is 31 bits;
obtaining a second m-sequence x2(N) initial value, and acquiring the x stored in the N registers of the DSP, respectively2(N), wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)；
According to the x in the DSP2Initial value of (n)And said x2(N) determining a second shift value, wherein the second shift value is 32 bits, and the second shift value is determined by the x2(n) is shifted by Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)；
Generating a target pseudorandom sequence in the DSP according to the first shift value and the second shift value.
2. The method of claim 1, wherein prior to said obtaining the first shift value stored in the first register of the DSP, the method further comprises:
storing the first shift value in the first register, wherein the first register is a 32-bit register, and the lowest bit in the first register is used for storing the x1(Nc) Or, the lowest order bit in the first register is used to store the x1(Nc+31)。
3. The method of claim 2, wherein prior to storing the first shift value in the first register, the method further comprises:
the first m-sequence x1Shifting the initial value of (n) Nc times to obtain the first shift value.
4. The method of claim 1, wherein the x stored in the N registers of the DSP are obtained separately2(N), the method further comprising, prior to the N polynomial coefficients:
storing the N polynomial coefficients in the N registers, respectively.
5. The method of claim 1, wherein the DSP determines the x2(n) and the initial value of x2(N) N polynomial coefficients, determiningA second shift value comprising:
according to the x2(n) and the initial value of x2(N) determining the second shift value based on a logical relationship between the N polynomial coefficients.
6. The method of claim 1, wherein generating a target pseudorandom sequence in the DSP based on the first shift value and the second shift value comprises:
and carrying out exclusive OR operation on the first shift value and the second shift value in the DSP to obtain the target pseudorandom sequence.
7. The method of claim 1, wherein obtaining the second m-sequence x is performed by a first processor2(n) initial values comprising:
determining the second m sequence x according to the following formula under the condition that the usage scenario of the target pseudorandom sequence is a physical downlink broadcast channel PBCH2Initial value of (n):
wherein, the CinitIs the second m-sequence x2(n) an initial value of (n), said
Is a cell ID; or
Determining the second m-sequence x according to the following formula under the condition that the use scene of the target pseudo-random sequence is a Physical Downlink Control Channel (PDCCH)2Initial value of (n): cinit＝(nRNTI·216+nID)mod231。
8. An apparatus for generating a pseudo-random sequence based on a DSP, comprising:
a first obtaining unit, configured to obtain a first shift value stored in a first register of the DSP, wherein the first shift value is formed by a first m-sequence x1(n) start ofThe initial value is shifted Nc times to obtain a shift value, the first shift value is 32 bits, and the first shift value is used for representing x1(Nc)，x1(Nc+1),x1(Nc+2)，…,x1(Nc+31), said x1The initial value of (n) is 31 bits;
a second obtaining unit for obtaining a second m-sequence x2(N) initial value, and acquiring the x stored in the N registers of the DSP, respectively2(N), wherein N is 32 and x is2(N) has an initial value of 31 bits, each of the polynomial coefficients has 32 bits, and the N polynomial coefficients are used to determine x2(Nc)，x2(Nc+1),x2(Nc+2)，…,x2(Nc+31)；
A determination unit for determining x in the DSP2(n) and the initial value of x2(N) determining a second shift value, wherein the second shift value is 32 bits, and the second shift value is determined by the x2(n) is shifted by Nc times to obtain a second shift value representing x2(Nc)，x2(Nc+1),x2(Nc+2),…,x2(Nc+31)；
And the generating unit is used for generating a target pseudo-random sequence in the DSP according to the first shift value and the second shift value.
9. A computer-readable storage medium, comprising a stored program, wherein the program is operable to perform the method of any one of claims 1 to 7.
10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to execute the method of any of claims 1 to 7 by means of the computer program.
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| WO2022001427A1 (en) * | 2020-07-01 | 2022-01-06 | 浙江三维利普维网络有限公司 | Dsp-based pseudo random sequence generating method and device, and storage medium |
| CN114091121A (en) * | 2022-01-18 | 2022-02-25 | 苏州浪潮智能科技有限公司 | Message abstract storage method, system, storage medium and equipment |
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| CN103812596A (en) * | 2012-11-09 | 2014-05-21 | 联芯科技有限公司 | Pseudo random sequence generation method and apparatus |
| CN109375897A (en) * | 2017-08-03 | 2019-02-22 | 普天信息技术有限公司 | The generation method of pseudo-random sequence |
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| CN114091121A (en) * | 2022-01-18 | 2022-02-25 | 苏州浪潮智能科技有限公司 | Message abstract storage method, system, storage medium and equipment |
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