CN111798902A - Method for obtaining soft information of charge trapping type 3D NAND flash memory - Google Patents
Method for obtaining soft information of charge trapping type 3D NAND flash memory Download PDFInfo
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- CN111798902A CN111798902A CN202010593839.6A CN202010593839A CN111798902A CN 111798902 A CN111798902 A CN 111798902A CN 202010593839 A CN202010593839 A CN 202010593839A CN 111798902 A CN111798902 A CN 111798902A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses a method for obtaining soft information of a charge trapping type 3D NAND flash memory, which is characterized in that the soft information of target page data is corrected by reading data of adjacent memory units of a target page and keeping interference influence on charges of the adjacent memory units according to offline training, so that the accuracy of the soft information is improved, and higher error correction performance is obtained. The method has important significance for improving the performance, the service life and the stability of the charge trapping type 3D NAND flash memory and reducing occupied resources and delay time.
Description
Technical Field
The invention relates to the technical field of NAND flash memories, in particular to a method for obtaining soft information of a charge trapping type 3D NAND flash memory.
Background
NAND flash memory has advantages of high storage density, large capacity, low cost, fast access speed, etc., and occupies an increasing market share of the storage market. In order to ensure the reliability and the scalability of the device, the storage structure of the NAND flash memory is upgraded from planar (2D) to three-dimensional (3D), the device structure is changed from floating gate type to charge trapping type, and the charge trapping type 3D NAND is widely used by samsung, kelan, western data and the like.
However, as the process size of the flash memory is continuously reduced, the number of layers of the 3D NAND flash memory is continuously increased, and the data error rate of the NAND flash memory is continuously increased, so that a better error correction algorithm is required. In recent years, a lot of researches on Low-Density Parity-Check (LDPC) codes have been carried out due to their excellent performance close to shannon limit and Low decoding complexity, and the Low-Density Parity-Check codes are now becoming mainstream error correction algorithms for large-scale application in NAND flash memories, thereby reducing the ever-increasing data error rate of the NAND flash memories and ensuring the reliability of data.
LDPC code error correction can be divided into hard decision decoding and soft decision decoding. The hard decision decoding takes shorter time and is faster, but stronger LDPC soft decision decoding is needed to exert the whole error correction performance of the LDPC. In an AWGN channel, soft-decision decoding has 2-3dB more soft-decision gain than hard-decision decoding. However, the NAND flash memory controller can only read the discrete information composed of '0' and '1' from the standard interface of the NAND flash memory chip, and cannot directly provide the required soft information for the LDPC. Soft information of LDPC soft decision decoding is obtained from the NAND flash memory, the accuracy of the soft information is improved, and soft decision decoding is carried out. Becomes the key to improve the LDPC error correction capability and the performance of the NAND flash memory controller.
Disclosure of Invention
The invention provides a method for obtaining charge trapping type 3D NAND flash memory soft information, which corrects the soft information of target page data by reading data of adjacent memory cells of a target page, improves the accuracy of the soft information and obtains higher LDPC soft decision decoding error correction performance.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a method of obtaining charge trapping 3D NAND flash memory soft information, comprising the steps of: s01), carrying out I times of hard reading and I times of hard decoding according to different hard decoding voltages, wherein I is a positive integer, obtaining a hard decoding result, if one time of hard decoding is successful, returning to the step of successful reading, and if not, entering the next step; s02), carrying out J times of soft reading according to different soft decoding voltages, and generating a soft information sequence P according to the reading result0[n]Performing LDPC soft decoding, if the soft decoding is successful, returning to the reading success, otherwise, entering the next step; s03), reading cell information of upper and lower adjacent memory cells, combining the N times of reading data in the step S02 to generate a soft information sequence P1[n]And performing LDPC soft decoding, and if the decoding is successful, returning to the reading success, otherwise, returning to the reading failure.
Furthermore, the results obtained by J times of soft reading are Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft \ (J-1) [ n ], the cell information of the read upper and lower adjacent storage units is Q _ near [ n ], a mapping relation table of Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft \ (J-1) [ n ] and P0[ n ], a mapping relation table of Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft \ (J-1) [ n ], Q _ near [ n ] and P1[ n ], and a soft information sequence of P46 1[ n ] is determined through an offretiring and a table.
Furthermore, when the soft information sequence has 4bit precision, the value intervals of P0[ n ] and P1[ n ] are [ -7, -6, -5, … …,5,6,7 ].
Furthermore, when the soft information sequence has the precision of 5bit, the value intervals of P0[ n ] and P1[ n ] are [ -15, -14, -13, … … 13,14,15 ].
Further, step S02 is repeatedly performed 1 to 3 times as needed.
Furthermore, I is more than or equal to 1 and less than or equal to 10, and J is more than or equal to 2 and less than or equal to 5.
The invention has the beneficial effects that: the invention provides a method for obtaining soft information of a charge trapping type 3D NAND flash memory, which is characterized in that the soft information of target page data is corrected by reading data of adjacent memory units of a target page and keeping interference influence on charges of the adjacent memory units according to offline training, so that the accuracy of the soft information is improved, and higher error correction performance is obtained. The method has important significance for improving the performance, the service life and the stability of the charge trapping type 3D NAND flash memory and reducing occupied resources and delay time.
Drawings
FIG. 1 is a functional block diagram of a NAND flash read;
FIG. 2 is a flowchart of example 1.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The embodiment discloses a method for obtaining charge trapping type 3D NAND flash memory soft information, which is used in the technical field of 3D NAND flash memories, and is a simplified functional block diagram of a memory controller device of the embodiment, as shown in fig. 1, wherein a NAND flash memory controller includes an LDPC code decoder, and is mainly responsible for data reading and writing, data storage and other functions. The NAND flash memory controller obtains data from a host, and the data generated by encoding operation of the data through the LDPC code decoder is stored in the NAND flash memory. If the host computer wants to obtain the data in the NAND flash memory, the NAND flash memory controller is needed to read the data from the NAND flash memory, and the data generated by decoding operation of the LDPC decoder is input to the host computer.
As shown in fig. 1, for the whole decoding process of the LDPC code, firstly, the default voltage is read, three times of hard reading are performed by changing the threshold voltage, 3 times of hard decoding are performed, and then soft information is generated according to the three times of hard reading results, and the soft decoding is performed, specifically, the process is as follows:
1. receiving a read request;
2. reading hard data according to the reading voltage V _ hard _0, and then carrying out LDPC hard decoding;
3. if the hard decoding is successful, returning to the reading success, otherwise, entering the next step;
4. reading hard data according to the reading voltage V _ hard _1, and then carrying out LDPC hard decoding;
5. if the hard decoding is successful, returning to the reading success, otherwise, entering the next step;
6. reading hard data according to the reading voltage V _ hard _2, and then carrying out LDPC hard decoding;
7. if the hard decoding is successful, returning to the reading success, otherwise, entering the next step;
8. reading for 3 times according to the reading voltages V _ soft _0, V _ soft _1 and V _ soft _2, then generating a soft information sequence P0[ n ], and carrying out LDPC soft decoding;
9. if the soft decoding is successful, returning to the reading success; otherwise, entering the next step;
10. reading cell information of adjacent upper and lower adjacent memory cells, combining the data read for the last three times, generating a soft information sequence P1[ n ], and performing LDPC soft decoding;
11. if the decoding is successful, a read success is returned. Otherwise, a read failure is returned.
In this embodiment, a binary LDPC code with a code length N and an information bit length K is considered, and for a NAND flash memory, a threshold voltage Vt is used to perform a decision to obtain a binary hard decision sequence Z [ N ]]= [z0, z1,…,zN-1]。
Because the hard decision and the LDPC hard decoding according to the reading of the NAND flash memory need to occupy memory resources, the NAND reading resources and the power consumption of the LDPC decoder are all smaller than those of the LDPC soft decision, under the condition of low error rate, the hard decision and the LDPC hard decoding are firstly adopted for error processing. Since the cells including the same memory bit have different threshold voltages due to noise, Z _ hard _0[ n ], Z _ hard _1[ n ], and Z _ hard _2[ n ] are sequentially generated using different hard decoding read voltages V _ hard _0, V _ hard _1, and V _ hard _2 … …, and are read a plurality of times and hard decoded.
When the error correction performance of the LDPC hard decoding cannot meet the requirement, the LDPC soft decoding needs to be started. To function requires providing soft information of the read data as input. In general, a soft information sequence P _ soft _0[ n ] is generated using preset soft decoding read voltages V _ soft _0, V _ soft _1, and V _ soft _ 2. If decoding fails, different soft decoding read voltages or different soft information generation methods may be tried, but in general, the soft information generation method is generated based on only the data of the read target page. In the invention, a new group of soft information sequences P _ soft _1[ n ] is generated by reading data of physically adjacent memory unit sequences and combining the data generated by V _ soft _0, V _ soft _1 and V _ soft _ 2. Adjacent memory cells will interact so that the generated soft information sequence will be more accurate, providing error correction capability for soft decoding.
Is normally softRead result Z _ soft _0[ n ]]、Z_soft_1[n]、Z_soft_2[n]Are all binary sequences, i.e. z0i、z1i、z2iTo be 0 or 1, a new soft information sequence P _ soft _1[ n ] needs to be generated according to the soft reading result and the reading result of the adjacent memory cell]. In this embodiment, tables 1 and 2 are obtained through offline NAND test statistics, where table 1 is Z _ soft _0[ n ]]、Z_soft_1[n]、Z_soft_2[n]……Z_soft_(J-1)[n]And P0[ n ]]In the table 2, Z _ soft _0[ n ]]、Z_soft_1[n]、Z_soft_2[n]……Z_soft_(J-1)[n]、Q_neibor[n]And P1[ n ]]By determining the soft information sequence P0[ n ] from a table look-up]、P1[n]。
P0 n, P1 n is 4bit or 5bit precision, when the soft information sequence is 4bit precision, the value range of P0 n, P1 n is [ -7, -6, -5, … …,5,6,7], when the soft information sequence is 5bit precision, the value range of P0 n, P1 n is [ -15, -14, -13, … … 13,14,15 ]. As shown in table 1 and table 2, when the precision is 5bits, the corresponding relations of Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft _ (J-1) [ n ], Q _ neobor [ n ], P0[ n ], and P1[ n ] are:
table 1:
table 2:
in this embodiment, the number of hard decoding rounds is set to 3 times, and may be set differently according to the requirement, and is generally set to 1 to 10 times. In this embodiment, the number of soft decoding rounds is set to be 1, the number of soft decoding rounds is set to be 3, and different settings can be performed according to requirements, generally 1 to 3 rounds, and one round is set to be 2 to 5 times. The scheme for reading the adjacent memory cells is set to 1 time, but can be set differently according to requirements. The hard decoding read voltage and the soft decoding read voltage may or may not be the same.
In the embodiment, the soft information of the target page data is corrected by reading the data of the adjacent memory cells of the target page and keeping the interference influence of the adjacent memory cells on the charges of the adjacent memory cells obtained by off-line training, so that the accuracy of the soft information is improved, and higher error correction performance is obtained. The method has important significance for improving the performance, the service life and the stability of the charge trapping type 3D NAND flash memory and reducing occupied resources and delay time.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (6)
1. A method of obtaining charge trapping 3D NAND flash memory soft information, comprising: the method comprises the following steps: s01), carrying out I times of hard reading and I times of hard decoding according to different hard decoding voltages, wherein I is a positive integer, obtaining a hard decoding result, if one time of hard decoding is successful, returning to the step of successful reading, and if not, entering the next step; s02), performing J times of soft reading according to different soft decoding voltages, generating a soft information sequence P0[ n ] according to a reading result, performing LDPC soft decoding, if the soft decoding is successful, returning to the reading success, otherwise, entering the next step; s03), reading cell information of upper and lower adjacent memory cells, combining the N times of reading data in the step S02 to generate a soft information sequence P1[ N ], carrying out LDPC soft decoding, if the decoding is successful, returning to read success, otherwise, returning to read failure.
2. The method of claim 1, wherein the method further comprises: the J times of soft reading result is Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft \ (J-1) [ n ], the cell information of the read upper and lower adjacent memory cells is Q _ neibor [ n ], a mapping relation table of the Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft \ (J-1) [ n ] and P0[ n ] is obtained through offline NAND test statistics, the table 2 is a mapping relation table of Z _ soft _0[ n ], Z _ soft _1[ n ], Z _ soft _2[ n ] … … Z _ soft _ (J-1) [ n ], Q _ neibor [ n ] and P1[ n ], and the table is looked up through determining soft n information sequence P4625 [ P ] and P1[ n ].
3. The method of claim 2, wherein the soft information comprises at least one of: when the soft information sequence has 4bit precision, the value intervals of P0[ n ] and P1[ n ] are [ -7, -6, -5, … …,5,6,7 ].
4. The method of claim 2, wherein the soft information comprises at least one of: when the soft information sequence has 5bit precision, the value ranges of P0[ n ] and P1[ n ] are [ -15, -14, -13, … … 13,14,15 ].
5. The method of claim 1, wherein the method further comprises: step S02 is repeatedly performed 1 to 3 times as needed.
6. The method of claim 1, wherein the method further comprises: i is more than or equal to 1 and less than or equal to 10, and J is more than or equal to 2 and less than or equal to 5.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4213396A1 (en) * | 2022-01-11 | 2023-07-19 | Silicon Motion, Inc. | Method and apparatus for performing access control of memory device with aid of aggressor bit information |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120224421A1 (en) * | 2011-03-01 | 2012-09-06 | Sandisk Technologies Inc. | System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements |
| CN104750571A (en) * | 2013-12-30 | 2015-07-01 | 慧荣科技股份有限公司 | Method for error correction, memory device and controller of memory device |
| US20170229186A1 (en) * | 2014-11-20 | 2017-08-10 | Western Digital Technologies, Inc. | Calibrating optimal read levels |
| CN108563534A (en) * | 2018-04-24 | 2018-09-21 | 山东华芯半导体有限公司 | LDPC interpretation methods suitable for nand flash memory |
| CN110444242A (en) * | 2018-05-03 | 2019-11-12 | 爱思开海力士有限公司 | There are the storage system and operating method of the interference correction ability based on deep learning |
| CN110515760A (en) * | 2019-08-29 | 2019-11-29 | 北京计算机技术及应用研究所 | A kind of LDPC flash error correction method based on machine learning |
| CN110797074A (en) * | 2018-08-02 | 2020-02-14 | 爱思开海力士有限公司 | Dynamic neighbor and bit line assist correction for NAND flash memory devices |
| CN111190764A (en) * | 2020-01-13 | 2020-05-22 | 山东华芯半导体有限公司 | Method for obtaining soft information of LDPC code of NAND flash memory |
-
2020
- 2020-06-28 CN CN202010593839.6A patent/CN111798902A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120224421A1 (en) * | 2011-03-01 | 2012-09-06 | Sandisk Technologies Inc. | System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements |
| CN104750571A (en) * | 2013-12-30 | 2015-07-01 | 慧荣科技股份有限公司 | Method for error correction, memory device and controller of memory device |
| US20170229186A1 (en) * | 2014-11-20 | 2017-08-10 | Western Digital Technologies, Inc. | Calibrating optimal read levels |
| CN108563534A (en) * | 2018-04-24 | 2018-09-21 | 山东华芯半导体有限公司 | LDPC interpretation methods suitable for nand flash memory |
| CN110444242A (en) * | 2018-05-03 | 2019-11-12 | 爱思开海力士有限公司 | There are the storage system and operating method of the interference correction ability based on deep learning |
| CN110797074A (en) * | 2018-08-02 | 2020-02-14 | 爱思开海力士有限公司 | Dynamic neighbor and bit line assist correction for NAND flash memory devices |
| CN110515760A (en) * | 2019-08-29 | 2019-11-29 | 北京计算机技术及应用研究所 | A kind of LDPC flash error correction method based on machine learning |
| CN111190764A (en) * | 2020-01-13 | 2020-05-22 | 山东华芯半导体有限公司 | Method for obtaining soft information of LDPC code of NAND flash memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4213396A1 (en) * | 2022-01-11 | 2023-07-19 | Silicon Motion, Inc. | Method and apparatus for performing access control of memory device with aid of aggressor bit information |
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